Customer Specific Device from ON Semiconductor DPA001 DPA001 - ATX-Dedicated PWM Controller

OFFLINE CONTROLLER FEATURING AUTOMATIC DUTYCYCLE CONTROL

The DPA001 controller offers everything needed to build cheap and reliable acdc switching converter dedicated to powering ATX systems. The controller includes an automatic dutycycle adjustment to enhance its performance in forward type applications during wide input variations but also a CVR management signal for 2switch forward applications. When the input voltage goes too low, a BrownOut input detects this condition and efficiently protects the converter by shutting it off. With an adjustable softstart period, the controller smoothly ramps up the current upon startup and reduces the poweron stress on the MOSFETs. An adjustable timerbased protection monitors the output power level and detects any abnormal over current conditions. Finally, an onboard precise 5 V reference offers a mean to improve feedback biasing conditions on the optocoupler. It can also serve as a bias supply to the surrounding elements if necessary.
Features

14 1 SO14 CASE 751A SUFFIX D

PIN CONNECTIONS
CS GND DRV VCC Vref Rt FB (Top View) CVRI CVROK Delay BOH BO Fault SS

Adjustable Switching Frequency, Peak Currentmode

Control Adjustable Softstart Associated with a Shutdown Function Latched External Fault Timerbased Detection Delayed Operation upon Startup via a Timer Autorecovery BrownOut Detection Adjustable Internal Ramp Compensation Programmable Maximum Dutycycle Adjustment versus Bulk Level Opencollector CVR_OK Signal for 2switch Forward Applications 9 V and 10 V UVLO Levels for Auxiliary Power Supply Connection VCC Range from 9 V to 28 V with Autorecovery UVLO Onboard 5 V / 2% Reference at TJ = 25C Internal 130 ns Leading Edge Blanking 1 A / 1 A Sourcesink Capability SO14 Package This is a PbFree Device This Device uses HalogenFree Molding Compound

MARKING DIAGRAM
14 DPA001 AWLYWWG 1 DPA001 A WL Y WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = PbFree Package

ORDERING INFORMATION
Device DPA001 Package SO14 (PbFree) Shipping 2500/Tape & Reel

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

Typical Applications

Power Supplies for Offline Adapters, PC Silver Boxes...

Semiconductor Components Industries, LLC, 2009

April, 2009 Rev. 1

Publication Order Number: DPA001/D

DPA001
Pin Function Description
Pin No. 1 Pin Name CS Function Current sense Pin Description Monitors the primary current and triggers the fault if needed. By inserting a resistor in series with the pin, you control the amount of ramp compensation you need. The controller ground This pin connects to the MOSFET gate This pin accepts voltages ranging from 9 V up to 28 V This pin delivers a stable voltage that can be used for various application purposes. A resistor connected to ground fixes the switching frequency. This pin directly connects to an optocoupler collector and a pullup resistor. A capacitor connected to ground selects the softstart. When brought below 1 V, the controller does not issue pulses. Shortcircuit / fault delayed detection This pin monitors the input voltage image to offer a BrownOut protection. It also offers a mean to change the maximum dutycycle. This pin toggles to Vref when the brownout is left. A precise resistor from this pin to the BO input creates the necessary hysteresis. A capacitor connected to this pin delays the delivery of driving pulses when the UVLO and the BO levels are reached. This pin is asserted low depending on the CVR level When the BO voltage is above this pin voltage, the CVR_OK signal is asserted low. If CVRI pin is grounded the ramp compensation feature is disabled.

2 3 4 5 6 7 8 9 10 11 12 13 14

GND Drv VCC Vref Rt FB SS Fault BO BOH Delay CVR_OK CVRI

Driver VCC Reference voltage Timing element Feedback Softstart Fault delay Brownout input Brownout hysteresis Startup delay CVR control signal CVR input

Vbulk CVR switch Vout + Vref = 5 V

SS Fault BO BOH SD Delay CVROK CVRI

FB Rt Vref VCC DRV GND CS Rcomp Aux. VCC

Rt Brown Out

Figure 1. Typical Application Diagram

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DPA001
+ + Vfault Vdd ITimerC Q S FCS + + Nfilter Rt Rt

Fsw adjustment Vcc management UVLO UVLO reset 2V 0V Buffered Ramp Ct 30 V Active Clamp 13.5 V Boot strap 15 V ref UVLO

S Q Q R

Vref Vref

Fault Cfault

Q R

Grand Reset

fsw ITimerD Vref FB Grand Reset 2R R Buffered Ramp + LEB Grand Reset BO shutdown Vdd Idelay BO Hyste + Vdelay + 1V SS

Vcc

S Q Q R

Drv

Rramp Rcomp Rsense Vbulk Delay CS Delay

Grand Reset

UVLO reset

GND BOK

+ Nfilter

+ VBO

BOH BOH open when Vbulk < VBO BOH closed when Vbulk > VBO Softstart is reset as long as delay cap. is discharged > pulses are stopped When delay is expired > softstart sequence > circuit pulses Vref CVRI/ADC + CVR setpoint Vdd

CVR OK Vref IC pulses only when Vss > 1 Vss < 1 no pulse IC is ready opendrain AND CVR OK pin is high impedance if VBO < VCVR > CVR OK CVR OK pin is low impedance if VBO > VCVR > CVR NOT_OK

SS ISS Soft Start

+ Vr_off Nfilter + DCmax set CVR/ADC signal comp. is low if VBO < VCVRI > max dc = 61% comp. is high if VBO > VCVRI > max dc = 47%

Figure 2. Internal Circuit Architecture http://onsemi.com

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DPA001
MAXIMUM RATINGS (Notes 1 and 2)
Symbol VCC VCC ICVR_OK_max Vref_max RJA TJMAX Rating Power Supply voltage, VCC pin, continuous voltage Power Supply voltage, VCC pin, transient voltage: 10 ms with IVcc < 20 mA Maximum current injected into pin 13 Maximum voltage on low power pins (except pin 4 and pin 3) Maximum voltage on pin 8 Thermal Resistance, JunctiontoAir Maximum Junction Temperature Storage Temperature Range ESD Capability, HBM model (All pins except HV) ESD Capability, Machine Model Value 28 30 30 10 0.3 to 10 5 120 150 60 to +150 2 190 Unit V V V mA V V C/W C C kV V

VCVR_OK_max Maximum voltage on pin 13

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series contains ESD protection and exceeds the following tests: Pin 114: Human Body Model 2000 V per MilStd883, Method 3015. Machine Model Method 200 V 2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = 5C to +125C, VCC = 15 V unless
otherwise noted) Symbol SUPPLY SECTION AND VCC MANAGEMENT VCCon VCCmin VCChyste ICC1 ICC2 ICC3 VCC increasing level at which driving pulses are authorized VCC decreasing level at which driving pulses are stopped Hysteresis between VCCON and VCCmin Startup current Internal IC consumption switching at 100 kHz, CL = 0 (Note 3) Internal IC consumption switching at 100 kHz, CL = 1 nF (Note 3) Input Bias Current @ 0.5 V input level on pin 1 (Note 4) Maximum internal current setpoint Propagation delay from CS detected to gate turned off, CL = 1 nF Leading Edge Blanking Duration 4 4 4 4 4 4 9.4 8.4 0.95 1.5 1.5 10 9.0 1.0 2.3 3.7 10.6 9.6 250 2.7 4.5 V V V mA mA mA Rating Pin Min Typ Max Unit

CURRENT COMPARATOR IIB ILimit1 TDEL CS TLEB FOSC1 FOSC2 Dmax1 Dmax2 1 1 1 1 0.93 0.02 1.0 70 130 1.07 150 mA V ns ns

INTERNAL OSCILLATOR Oscillation frequency Rt = 20 kW DRV pin = 47 kW Oscillation frequency Rt = 10 kW DRV pin = 47 kW Maximum dutycycle Vpin BO < Vpin CVRI @ Rt = 20 kW (Note 5) Maximum dutycycle Vpin BO > Vpin CVRI @ Rt = 20 kW (Notes 5 and 6) 6 6 3 3 90 59 45 100 190 61 47 110 63 49 kHz kHz % %

FEEDBACK SECTION FBdiv RFB 3. 4. 5. 6. 7. Internal voltage division from FB to CS setpoint Internal feedback impedance from FB to GND 7 5.0 3 6.0 7.0 na kW

1 mA load on Vref. Measured when the output DRV is in OFF state Max Duty cycle versus frequency will be trace the characterization section If CVRI pin is grounded then duty cycle limit will be Dmax2. Parameter guaranteed by design

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DPA001
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25C, for min/max values TJ = 5C to +125C, VCC = 15 V unless
otherwise noted) Symbol INTERNAL RAMP COMPENSATION Vramp Rramp Vr_off Vr_off_hyst Internal ramp level @ 25C (Note 7) Internal ramp resistance to CS pin (Note 7) CVRI pin level at which the ramp compensation is disabled Comparator hysteresis level 1 1 2 2 1.8 2.0 15 0.5 50 2.2 V kW V mV Rating Pin Min Typ Max Unit

DRIVE OUTPUT VCC = 15 V Tr Tf ROH ROL VCL VDRP Output voltage risetime @ CL = 1 nF, 1090% of a 12 V output signal Output voltage falltime @ CL = 1 nF, 1090% of a 12 V output signal Source resistance Sink resistance Clamping voltage for VCC = 25 V (maximum gate voltage) Highstate voltage drop, VCC = VCCmin + 100 mV, Rpulldown = 47 kW Reference voltage, Iout = 8 mA TJ = 25C VCC rejection capability, Iout = 8 mA TJ = 25C DVCC = 1 V Reference variation with load changes, 1 mA < Iref < 10 mA, TJ = 25C Maximum output current capability Decoupling capacitor connected to Vref Softstart charging current TJ = 25C Softstart ending voltage (Note 7) Voltage level on SS pin that enables SoftStart when SS pin voltage is rising from 0 V Voltage level on SS pin that resets the SoftStart Delay timer charging current C = 0.1 mF, Tdelay 50 ms Timer charge ending voltage Fault timer charging current Fault timer discharging current Fault level at which the controller latchesoff Noise filter on BO, Fault, CVR pins and internal fault signal Current sense fault level triggering the timer Pulldown current of 2 mA Internal pulldown switch RDS(on) Comparator hysteresis on CVR comparator Brownout voltage Brownout hysteresis pin level TJ = 25C @ noload Brownout hysteresis internal impedance 3 3 3 3 3 3 11 15 15 7.0 7.0 13.5 0.5 15 15 16 1.0 ns ns W W V V

REFERENCE VOLTAGE Vref VrefLineReg VrefLoadReg IrefOut Cref PROTECTION ISS VSS VSS_en VSS_dis Idelay Vdelay ITimerC ITimerD Vfault Nfilter FCS CVR_OK sat CVR_OK res CVRhyste VBO VBOH RBOH 3. 4. 5. 6. 7. 8 8 8 8 12 12 9 9 9 9 13 13 2 10 11 11 9.0 1.8 0.9 0.67 8.0 2.7 85 42.5 3.15 0.9 150 0.974 4.9 2.0 10 2.0 1.0 VSS_en 0.2 10 3.0 100 50 3.5 25 0.97 200 10 1.0 5.0 3.0 11 2.2 1.1 0.96 12 3.3 115 57.5 3.85 1.04 0.4 250 1.026 5.1 4.0 mA V V V mA V mA mA V ms V V W mV V V kW 5 5 5 5 5 4.9 10 5.0 5.0 10 5.1 50 25 0.1 V mV mV mA mF

1 mA load on Vref. Measured when the output DRV is in OFF state Max Duty cycle versus frequency will be trace the characterization section If CVRI pin is grounded then duty cycle limit will be Dmax2. Parameter guaranteed by design

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DPA001
TYPICAL CHARACTERISTICS
250 200 ICC3 (mA) 0 25 50 75 100 125 150 100 50 0 25 3.5 3.0 2.5 ICC1 (mA) 2.0 1.5 1.0 0.5 0 25 0 25 50 75 100 125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 3. ICC1 vs. Junction Temperature

10.7 10.5 10.3 10.1 9.9 9.7 9.5 25 9.7 9.5 9.3 9.1 8.9 8.7 8.5 25

Figure 4. ICC3 vs. Junction Temperature

25

50

75

100

125

VCC(min) (V)

VCC(on) (V)

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 5. VCC(on) vs. Junction Temperature

1.08 1.06 1.04 FOSC1 (kHz) ILimit1 (V) 1.02 1.00 0.98 0.96 0.94 0.92 25 0 25 50 75 100 125 89 25 104 109

Figure 6. VCC(min) vs. Junction Temperature

99

94

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 7. ILimit1 vs. Junction Temperature

Figure 8. FOSC1 vs. Junction Temperature

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DPA001
TYPICAL CHARACTERISTICS
62.9 62.4 61.9 Dmax1 (%) Dmax2 (%) 0 25 50 75 100 125 61.4 60.9 60.4 59.9 59.4 58.9 25 48.9 48.4 47.9 47.4 46.9 46.4 45.9 45.4 44.9 25 0 25 50 75 100 125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 9. Dmax1 vs. Junction Temperature

2.19 2.14 2.09 Rramp (kW) Vramp (V) 2.04 1.99 1.94 1.89 1.84 1.79 25 0 25 50 75 100 125 11 17 15 13 21 19

Figure 10. Dmax2 vs. Junction Temperature

9 25

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 11. Vramp vs. Junction Temperature

160 140 5.04 120 TdeICS 100 80 4.94 60 40 25 4.89 25 Vref (V) 4.99 5.09

Figure 12. Rramp vs. Junction Temperature

25

50

75

100

125

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 13. TdeICS vs. Junction Temperature

Figure 14. Vref vs. Junction Temperature

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TYPICAL CHARACTERISTICS
1.05 1.03 1.01 FCS (V) 0.99 0.97 0.95 0.93 0.91 0.89 25 0 25 50 75 100 125 VBO 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 25 0 25 50 75 100 125

TJ, JUNCTION TEMPERATURE (C)

TJ, JUNCTION TEMPERATURE (C)

Figure 15. FCS vs. Junction Temperature

5.09

Figure 16. VBO vs. Junction Temperature

5.04

VBOH

4.99

4.94

4.89 25

25

50

75

100

125

TJ, JUNCTION TEMPERATURE (C)

Figure 17. VBOH vs. Junction Temperature

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DPA001
Application Information
Introduction

The DPA001 hosts a highperformance currentmode controller specifically developed to drive lowcost power supplies for the ATX and the adapter market: Currentmode operation: implementing peak currentmode control topology, the circuit offers UC384Xlike features to build rugged power supplies. Adjustable switching frequency: a resistor to ground precisely sets the switching frequency between 50 kHz and a maximum of 200 kHz. There is no synchronization capability. Wide VCC excursion: the controller allows operation up to 28 V continuously and accept transient voltage up to 30 V during 10 ms with IVcc < 20 mA. Gate drive clamping: a lot of power MOSFETs do not allow their driving voltage to exceed 20 V. The controller includes a lowloss clamping voltage which prevents the gate from going beyond 13.5 V typical. Automatic dutycycle control: by monitoring the brownout pin, hence indirectly the bulk level, the designer has the ability to toggle the maximum dutycycle setpoint in relationship to the input voltage. Thanks to a dedicated pin, this voltage can easily be adjusted via a biasing network hooked to the reference point Vref. If the BO voltage is below the CVRI setpoint, then the dutylimit goes to 61%. When BO is above the CVRI level, the dutycycle limit goes back to 47%. If the CVRI pin is grounded thus the duty cycle limit will be 47%. CVR signal: the 2switch forward topology can implement a special circuitry which requires a signal turning it off or on, depending on the bulk conditions. The CVR_OK pin delivers such signal in an opendrain configuration: when the brownout level (the image of the bulk capacitor) reaches the adjustable voltage set on the CVRI pin, the CVR_OK pin is asserted low. To the opposite, when the bulk voltage image passes below the CVR level, the internal transistor blocks and the CVR_OK pin becomes high impedance. Low startupcurrent: The startup current is guaranteed to be less than 250 mA maximum, helping the designer to reach a low standby power level. Onboard reference voltage: pin 5 delivers a precise 5 V level that can be used as a logic housekeeping supply or to connect the optocoupler pullup resistor. Shortcircuit protection: by monitoring the currentsense voltage when it exceeds 1 V, the

controller detects a fault and starts to charge an external capacitor connected to pin 9. In case the level on this capacitor exceeds 3.5 V, the controller permanently latchesoff. Reset occurs when a) a BO reset is sensed b) VCC is cycled down below VCC(min). Startup delay: as soon as VCC reaches the turnon level and provided the BO input senses enough voltage, the controller starts to charge the capacitor connected to pin 12. During this time, the controller stays idle and does not deliver output pulses. After the capacitor has reached an internal level (delay is finished), then the softstart sequence can commence and driving pulses width is slowly rampingup. In shutdown mode via the BO pin brought low, the delay capacitor is reset. Adjustable softstart: the softstart is activated upon a startup sequence (VCC goingup) but also when the brownout pin is reset. The output pulses start to appear on the driver when the softstart voltage goes beyond 1 V. A 10% precision is required on internal parameters affecting the softstart. Softstart maximum duty cycle follows CVR_OK pin status. Shutdown: if an external transistor brings the softstart pin down, the controller is shut down, but all internal biasing circuits are alive, keeping the controller ready for an immediate restart. When the pin is released, a softstart sequence takes place above 1 V on the SS pin. A similar shutdown occurs if the BO pin is brought low. After a BO shutdown the restarts go through a delay capacitor charging and a complete softstart activation. BrownOut protection: pin 10 permanently monitors a fraction of the input voltage. When this image is below the VBO threshold, the circuit stays off and does not switch. As soon the voltage image comes back within safe limits, the pulses are restarted via a startup sequence including softstart. The hysteresis is implemented in a precise manner by using the reference voltage routed to pin 11, BOH: connecting a resistor from this BOH voltage to the BO pin helps to precisely select the hysteresis level. Ramp compensation: by inserting a resistor between the currentsense (CS) pin and the actual sense resistor, it becomes possible to inject a given amount of ramp compensation since the internal sawtooth clock is routed to the CS pin. Subharmonic oscillations in Continuous Conduction Mode (CCM) can thus be compensated via a single resistor. Ramp compensation can be disabled by grounding CVRI pin.

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DPA001
Startup Sequence

When the VCC voltage is reaching the VCC(on) level and the controller confirms that enough voltage is present on the bulk capacitor (via the internal brownout circuitry), the controller starts to wakeup: a currentsource charges a capacitor connected to the DELAY pin. During this time, no output pulses are allowed. Once the delay has elapsed, the controller assumes the power factor correction output voltage is properly settled and the softstart (SS) sequence is initiated: pulses are delivered with a current limit smoothly increased. If we assume a 100 ms delay, the capacitor value should be calculated via the following equation:
450 350 250 150 50.0 14.0 10.0 6.00 2.00 2.00 7.00 5.00 3.00 1.00 1.00 7.00 5.00 3.00 1.00 1.00 79.7 m B Startup Delay Plot 1 Vbulk in Volts A BO Level is Reached

C delay + I delay Dt DV

C delay + 10 m

100 m + 330 nF 3

The below curves illustrate a typical startup sequence when the bulk voltage reaches the brownout level (see point A). Between point A and B, a delay linked to the noise filter can be seen, around 25 ms. At point B the current source generating the startupup delay is activated. When the delay pin voltage reaches the Vdelay level, the softstart sequence commences (see point C) and pin 8 voltage starts to rise. When it reaches 1 V, drive pulses are authorized and the duty cycle smoothly increases until the SS pin reaches VSS level (see point D), confirming the softstart end.
Bulk Voltage DRV Pulses Start Only when SS Pin 1

Plot 2 Drv in Volts

DRV Pin Pulses C Delay Pin Voltage

Plot 3 Delay in Volts

Plot 4 VSS in Volts

Noise Filter Delay

SS Pin Voltage

239 m

399 m (Time in seconds)

558 m

718 m

Figure 18. Startup Sequence when the Brown Out is Activated

The following curve illustrates the same startup sequence except that the bulk voltage is now established and the VCC is externally applied. Point A: when the bulk voltage reaches the BO level, nothing happens since VCC < VCC(on). Point B: VCC reaches VCC(on), the startup sequence can start. The internal grand reset signal is disabled, Idelay can fuel the delay capacitor.

Point C: when delay pin reaches Vdelay level (# 3 V), it indicates the delay completion. The soft start ramp begins. Point D: when the SS pin reaches 1 V, driver pulses are allowed with a smooth duty cycle increase from almost 0 to the nominal value.

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DPA001
A Plot 2 Plot 1 VCC in Volts Vbulk in Volts 450 350 250 150 50.0 14.0 12.0 10.0 8.00 6.00 14.0 10.0 6.00 2.00 2.00 7.00 5.00 3.00 1.00 1.00 7.00 5.00 3.00 1.00 1.00 209 m 628 m Bulk Voltage BO Level is Reached

B D DRV Pulses Start Only when SS Pin 1

VCC Voltage

Plot 3 Drv in Volts

DRV Pin Pulses

Plot 5 Plot 4 Delay in Volts VSS in Volts

SS Pin Voltage C

Startup Delay

Delay Pin Voltage

1.05 m (Time in seconds)

1.46 m

1.88 m

Figure 19. Startup Sequence when the VCC Level is Reached

A 3.50 Plot 1 VSS, Voscillator in Volts 2.50 1.50 500m No Pulse until VSS = 1 V CSS2 CSS1 SS Ramp Internal Oscillator Saw Tooth

500m

14.0 Plot 2 Drv in Volts 10.0 6.00 2.00 DRV Pin Pulses 2.00 538 m 597 m 655 m (Time in seconds) 713 m 771 m

Figure 20. Detailed View on the Duty Cycle Variation

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DPA001
Soft Start Time Brownout Protection and CVR_OK Pin Feature

In the startup sequence, the designer has the ability to adjust both the delay before the driver pulses actually occur, and also the softstart duration itself. During the soft start time the duty cycle is increased from zero to the maximum or the nominal value, as depicted by Figure 20. To guarantee a full zero dutycycle at the beginning, no pulses are allowed until the SS pin reaches 1 V. Figure 20 depicts a full softstart sequence, made of two events: 1. the capacitor charges up from 0 to 1 V. During this time, no pulses occur on the DRV pin. 2. when 1 V is reached, pulses start to appear on the DRV pin and last until the SS pin touches 3 V One can thus consider the full duration (CSS2) or the softstart duration, with pulses, alone. Both timing duration can be calculated as follows:
C SS1 + I SS C SS2 + I SS tSS 20 m + 10 m + 100 nF 3*1 V SS * V SD tSS 20 m + 10 m + 66 nF 3 V SS

By monitoring the level on BO pin, the controller protects the 2switch power supply against low input voltage conditions. When the BO pin level falls below the VBO level, the controllers stops pulsing until the input level goes back to normal and resumes the operation via a new startup sequence. The brownout comparator features a fixed voltage reference level (VBO). The hysteresis is implemented by using the internal 5 V reference routed to BOH pin. By connecting a resistor from this BOH voltage to the BO pin, it helps to precisely select the hysteresis level. If BO pin level is below the CVRI pin level, the CVR_OK pin is set to high impedance and the maximum dutycycle toggles to 61% instead of 47% in normal operation. An additional comparator connected to the CVRI permanently monitors the level on this pin. If it falls below 0.5 V (e.g. via external grounding), the controller detects it and disables the ramp compensation feature. In this configuration, the maximum dutycycle does not exceed 47%.

Vref Vbulk BOH Rupper RH + + VBO Noise Filter BOK Opendrain CVR OK CVR OK pin is high impedance if VBO < VCVRI CVR OK CVR OK pin is low impedance if VBO > VCVRI CVR NOT_OK

BO Vref Rlower

Rref CVRI + Rgnd Noise Filter

Figure 21. Brown Out and CVRI Pins Setup

With the following lines of algebra, we can determine the resistor values externally setup to fit the brownout requirements. Brown out specifications: VBO(on) = 350 V VBO(off) = 250 V VBO = 1 V VH = Vref = 5 V Ibridge = 83 mA, current inside the BO resistor divider (Rlower and Rupper)

Rlower and Rupper will be determined with the Ohm law as follows:
R lower + I bridge V BO R upper + V BO(on) * V BO I bridge

R lower + 12.048 kW

R upper + 4.205 MW

The resistor connected from the reference voltage to BO pin (RH) sets the required hysteresis level. It can be extracted from the following formula (superposition theorem applied on the BO pin):

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DPA001
R HR lower R upperR lower

V BO + V BO(off)

R H)R lower

R upper ) R

R HR lower
H)R lower

) V HYS

R upper)R lower

RH ) R

R upperR lower
upper)R lower

RH +

R upperR lower(V HYS * V BO(off)) V BO(off)R upper ) V BO(off)R lower ) V BO(off)R lowe

R H + 168.2 kW

Now to fix the CVR voltage, it is necessary to account for the hysteresis applied on the BO pin, once the controller starts to pulse. CVR specifications: Vbulk = 340 V when the CVR is activated. We arbitrarily select a ground resistor Rgnd of 10 kW. By using the previous formula:
R HR lower R upperR lower

Figure 22 illustrates the previous brownout and CVR specification. Point A: when the bulk voltage reaches BOON level (350 Vdc), the startup sequence is initiated. At the same time, a step appears on the BO pin due to the activation of the 5 V reference and the hysteresis it brings. Point B: when the bulk voltage is decreasing and reaches the CVRI level (340 Vdc), the CVR_OK pin is moving from low impedance to high impedance. Point C: if the bulk voltage is falling down to BOOFF level (250 Vdc), drive pulses are stopped. A certain delay exists though, because of the noise filtering circuit in place ( 25 ms).

V pinBO + V bulk

R H)R lower

R upper ) R

R HR lower
H)R lower

) V HYS

R upper)R lower

RH ) R

R upperR lower
upper)R lower

V pinBO + 1.24 V V ref * V pinBO V pinBO

R ref + R gnd

R ref + 30.3 kW
450 350 250 150 50.0 1.40 1.00 600m 200m 200m 6.50 4.50 2.50 500m 1.50 14.0 10.0 6.00 2.00 2.00 200 m A BOON = 350 V BOOFF = 250 V B C Bulk Voltage

Plot 4 Plot 3 VCVR_OK in Volts VBO, VCVRI in Volts

Plot 1 Vbulk in Volts

Hysteresis at the Switch ON

CVRI = 340 V

Hysteresis at the Switch OFF

BO Pin & CVRI Pin

CVR_NOT_OK CVR_OK CVR_OK Noise Filtering Delay Delay

CVR_OK Pin

Plot 2 Drv in Volts

DRV Pin Pulses 600 m 1.00 m (Time in seconds) 1.40 m 1.80 m

Figure 22. Brownout and CRV_OK Pin Feature

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DPA001
Figure 23 illustrates the maximum duty cycle change when the CVR_OK pin is moving from low impedance to high impedance.
6.50 Plot 4 VCVR_OK in Volts 4.50 2.50 CVR_NOT_OK 500m 1.50 CVR_OK CVR_OK Pin

16.0 Plot 3 VDRV in Volts 12.0 8.00 4.00 0 1.31 m

DC max 47%

DC max 61% DRV Pin Pulses

1.33 m

1.35 m (Time in seconds)

1.37 m

1.39 m

Figure 23. Maximum Duty Cycle Change when the CVR_OK Pin Changes

The following figure illustrates the possibility to shutdown the controller by grounding BO pin.
Vbulk BOH Vref

Shut down

Rupper

RH BO Rlower + + VBO

Noise Filter BOK

Q1

Figure 24. Shutdown Feature on BO Pin Short Circuit or Over Load Protection

If the current sense (CS) pin exceeds 1.0 V, the controller detects a fault and starts to charge an external capacitor connected to the Fault pin. If the fault disappears before reaching the fault level (Vfault) the capacitor is discharged with a constant current. If the fault pin reaches the fault level, the controller latchesoff: the driver pulses are permanently stopped. The controller can be reset if a BO reset is sensed or if VCC is cycled down to VCC(min). Figure 25 illustrates the short circuit protection. Point A: before this point, the controller operates normally. At this time a short circuit or an overload

appears; the ITimerC current source on fault pin activates and charges the capacitor connected to this pin. Point B: at this time, the short circuit disappears, then the capacitor is discharged by the ITimerD current source. Point C: the short circuit comes back, the fault capacitor is thus charged again by ITimerC until the short circuit or the over load disappears. Point D: the fault is still there and the fault pin reaches the Vfault level: the controller latchesoff and the fault capacitor is discharged by the ItimerD current source.

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DPA001
4.00 Plot 1 Vfault in Volts 2.00 0 2.00 4.00 1.60 Plot 3 v(13) in Volts 1.20 800m 400m 0 14.0 Plot 2 Drv in Volts 10.0 6.00 2.00 2.00 328 m 984 m 1.64 m (Time in seconds) 2.30 m 2.95 m DRV Pin Pulses Current sense is reduced, discharge by the 50 mA source Fault comes back Vfault is reached latchedoff Fault Pin A B C D

CS Pin

Figure 25. Short Circuit or Over Load Protection

As this protection is a cumulative protection (illustrated in Figure 25), narrow repetitive short circuit is also taken into account until the fault pin reaches the fault level and finally latch off the controller.

Shut Down

The first has already been illustrated on Figure 24; if

There are 2 possibilities to shut down the controller:

the brown out pin is grounded the controller is disabled The second one consists of grounding the soft start pin via a simple bipolar transistor as illustrated by the following figure:
Vdd

Shut down

ISS Soft Start Delay Ending

Figure 26. Shutdown Feature through the SS Pin Ramp Compensation

Ramp compensation is a known mean to cure subharmonic oscillations. These oscillations take place at half of the switching frequency and occur only during Continuous Conduction Mode (CCM) with a dutycycle greater than 50%. To lower the current loop gain, one usually

injects between 50 and 100% of the inductor downslope. Figure 27 depicts how internally the ramp is generated: The ramp compensation applied on CS pin is from the internal oscillator ramp buffered. A switch placed between the buffered internal oscillator ramp and Rramp disconnects the ramp compensation during the OFF time DRV signal.

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2 V 0 V Buffered Ramp Rramp Rcomp CS LEB CCS + + Vr_off From Set Point

S Q Q

DRV Path

R +

Rsense

Vref

BO

CVRI/ADC CVR Setpoint +

Noise Filter CRV Path

Figure 27. Ramp Compensation Internal Diagram

As we explained before, grounding the CVRI pin disables the ramp compensation and fixes the dutycycle below 50%. In the Blondie, the internal ramp swings with a slope of:
S int + V ramp F [V s] DC max SW

In a forward application the secondaryside downslope viewed on a primary side requires a projection over the sense resistor Rsense. Thus:
S sense + (V out ) V f) N s R [V s] N p sense L out

The previous ramp compensation calculation does not take into account the natural primary ramp created by the transformer magnetizing inductance. In some case illustrate here after the power supply does not need additional ramp compensation due to the high level of the natural primary ramp. The natural primary ramp is extracted from the following formula:
S natural + V bulk R [V s] L mag sense S natural [%] S sense

Then the natural ramp compensation will be:

natural_comp +

where: Vout is output voltage level Vf the freewheel diode forward drop Lout, the secondary inductor value Ns/Np the transformer turn ratio Rsense: the sense resistor on the primary side Assuming the selected amount of ramp compensation to be applied is comp, then we must calculate the division ratio to scale down Sint accordingly:
Ratio + S sense comp [1] S int Ratio [W] 1 * Ratio

If the natural ramp compensation (natural_comp) is higher than the ramp compensation needed (comp), the power supply does not need additional ramp compensation. If not, only the difference (compnatural_comp) should be used to calculate the accurate compensation value. Thus the new division ratio is:
if natural_comp t comp Ratio + S sense( comp * natural_comp) S int [1]

A few line of algebra determined Rcomp:

R comp + R ramp

Then Rcomp can be calculated with the same equation used when the natural ramp is neglected.

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Ramp Compensation Design Example:

2 switchForward Power supply specification: Regulated output: 12 V Lout = 10 mH Vf = 0.7 V (drop voltage on the regulated output) Current sense resistor: 0.18 W Switching frequency: 100 kHz Vbulk = 250 V, minimum input voltage at which the power supply works. Secondaryside downslope projected over the sense resistor is:
S sense (V out ) V f) N s R N p sense L out V bulk R L mag sense

Duty cycle max: DCmax = 63% Vramp = 2 V, Internal ramp level. Transformer specification:
Lmag = 20 mH Np = 75 turns Ns = 7 turns Internal ramp compensation level
S int + V ramp F DC max SW

S int + 2 100 kHz + 317 mV m 0.63

S sense +

(12 ) 0.7) 7 0.18 + 21.33 mV ms 10 @ 10 *6 75 250 0.18 + 2.25 mV ms 20 @ 10 *3

Natural primary ramp:

S natural + S natural +

Thus the natural ramp compensation is:

natural_comp + S natural S sense natural_comp + 2.25 + 10.5% 21.33 S sense( comp * natural_comp) S int

Here the natural ramp compensation is lower than the desired ramp compensation, so an external compensation should be added to prevent subharmonics oscillation.
Ratio + 21.33 @ (0.50 * 0.10) + 0.027 317

Ratio +

We can know calculate external resistor (Rcomp) to reach the correct compensation level.
R comp + R ramp Ratio 1 * Ratio R comp + 15 @ 10 3 0.027 + 415 W 1 * 0.027

Thus with Rcomp = 470 W, 50% compensation ramp is applied on the CS pin. The following example illustrates a power supply where the natural ramp offers enough ramp compensation to avoid external ramp compensation. 2 switchForward Power supply specification: (high lighted in bold the change compare to the previous example) Regulated output: 12 V Lout = 22 mH Vf = 0.7 V (drop voltage on the regulated output) Secondaryside downslope projected over the sense resistor is:
S sense + (V out ) V f) N s R N p sense L out V bulk R L mag sense

Current sense resistor: 0.18 W Switching frequency: 100 kHz Vbulk = 250 V, minimum input voltage at which the
power supply works. Duty cycle max: DCmax = 63% Vramp = 2 V, Internal ramp level. Transformer specification: Lmag = 10 mH Np = 75 turns Ns = 7 turns

S sense +

(12 ) 0.7) 7 0.18 + 9.70 mV ms 22 @ 10 *6 75

The natural primary ramp is:

S natural + S natural + 250 0.18 + 4.50 mV ms 10 @ 10 *3

And the natural ramp compensation will be:

natural_comp + S natural S sense natural_comp + 4.50 + 46.4% 9.70

So in that case the natural ramp compensation due to the magnetizing inductance of the transformer will be enough to prevent any subharmonics oscillation in case of duty cycle above 50%.

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PACKAGE DIMENSIONS
SOIC14 CASE 751A03 ISSUE J
A
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

P 7 PL 0.25 (0.010)
M

G C T
SEATING PLANE

R X 45 _

D 14 PL 0.25 (0.010)

K
M

M
S

T B

SOLDERING FOOTPRINT*
7X

DIM A B C D F G J K M P R

MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50

INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019

7.04 1 0.58
14X

14X

1.52

1.27 PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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