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ECE 261 Project Presentation 2: Eric Wang Federico Gonzalez Bryan Flemming Jep Barbour

This document summarizes an ECE 261 project to design an 8-bit Booth multiplier using Booth's algorithm. It includes a block diagram showing the key components: Booth encoders/selectors, 16-bit carry save adders, and partial product generators. It provides schematics and layout views for the Booth encoder, decoder, and other components. It also presents simulation results demonstrating the correctness of the design for different input cases and analyzing the propagation time, which is 6ns worst case, and power consumption, which is an average of 94.96nW.

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96 views24 pages

ECE 261 Project Presentation 2: Eric Wang Federico Gonzalez Bryan Flemming Jep Barbour

This document summarizes an ECE 261 project to design an 8-bit Booth multiplier using Booth's algorithm. It includes a block diagram showing the key components: Booth encoders/selectors, 16-bit carry save adders, and partial product generators. It provides schematics and layout views for the Booth encoder, decoder, and other components. It also presents simulation results demonstrating the correctness of the design for different input cases and analyzing the propagation time, which is 6ns worst case, and power consumption, which is an average of 94.96nW.

Uploaded by

ajith.ganesh2420
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE 261 Project Presentation 2 8-bit Booth Multiplier

Eric Wang Federico Gonzalez Bryan Flemming Jep Barbour

Abstract
The purpose of this project is to create a 8 by 8 multiplier using Booths multiplication algorithm. The 8-bit multiplicand and 8-bit multiplier are input signals into four Booth encoders/selectors. After applying Booths algorithm to the inputs, simple addition is done to produce a final output.
Our main goal is to produce a working 8 by 8 bit multiplier with correct simulations and layout while attempting to maximize the speed in which the multiplier performs the calculation.
2

Schematic Block Diagram


8 Bit Multiplicand

16 Bit Carry Save Adder

Booth Encoder/ Selector for bits [0 1 2]

8 Bit Multiplier

Product Out

Booth Encoder/ Selector for bits [2 3 4] 16 Bit Carry Save Adder 16 Bit Carry Save Adder

Booth Encoder/ Selector for bits [4 5 6]

Booth Encoder/ Selector for bits [6 7 8]


3

Booth Encoder
Schematic

Booth Encoder

Booth Decoder Schematic

Booth Decoder Layout

Partial product generator


Schematic

Partial product generator


Booth Encoder 8 Booth Decoders

Full Adder

Full Adder

16 bit Carry Save Adder

16 bit Carry Save Adder

CSA16

4 bit Carry Save Adder

CSA16

4 bit Carry Save Adder

CSA16

Top Level Diagram

Top Level Layout

Functional Simulations
Our Eldo would not simulate the top level diagram with all three adders included Therefore, for simulations, we deleted the third adder, and took the outputs at the ends of the inner adders. To verify functionality through simulation, we simply took the two outputs we found and added them ourselves.

Test 1:
Multiplier input: 00001010 = 10 Multiplicand input: 00000101 = 5 Output 1: 1111111111011110 Output 2: 0000000001010100 Sum of outputs: 0000000000110010 = 50 As we can see, the output equals the product of the two inputs

Test 2
Multiplier input: 01011101 = 93 Multiplicand input: 0001101010 = 26 Output 1: 1111111110100110 Output 2: 0000100111000100 Sum of outputs: 0000100101101010 = 2418 Once again the final output is equal to the product of the inputs as expected.

Timing Simulations
Propagation time? Only 6ns worst case

Propagation Time continued


Extra adder! 2ns additional propagation time.

Power Consumption
Simulation of top level block (minus the final adder of course) showed an average power consumption of 73.72 nano Watts. Simulation of the adder gave a power consumption of 21.24 nW. Therefore the total power consumption of our circuit is expected to be an average of 94.96nW.

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