CSE140L: Components and Design Techniques for Digital Systems Lab Timing, Mux, Demux, Adders
Tajana Simunic Rosing
Outline
Review of CMOS Non-ideal gate behavior (3.5)
Rise/fall time Delay Pulse width
Pass gates (Appendix B) Muxes & Demuxes (chap 4.2 pp. 171-183) Adders (chap 5.6)
CMOS gate design
Implement F using CMOS: F=[A*(B+C)*(AB+C)]
CMOS delay review
Implement F using CMOS: F=A*(B+C)
When is non-ideal gate behavior a good thing?
Can be useful pulse shaping circuits Can be a problem incorrect circuit operation Example: pulse shaping circuit
A A = 0 delays matter
A B C D F
D remains high for three gate delays after A changes from low to high
F is not always 0 pulse 3 gate-delays wide
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Oscillatory behavior
Another pulse shaping circuit
+ A open switch close switch initially undefined open switch C D B resistor
CSE140: Components and Design Techniques for Digital Systems Muxes and demuxes
Tajana Simunic Rosing
Pass transistor Mux building block
Connects X & Y when A=1, else X & Y disconnected
A_b = not(A)
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Fig source: Prof. Subhashish Mitra
Multiplexor (Mux)
Mux routes one of its N data inputs to its one output, based on binary value of select inputs
4 input mux needs 2 select inputs to indicate which input to route through 8 input mux 3 select inputs N inputs log2(N) selects
Mux Internal Design
21 21 21
A B
i0 i1 s0
A Y B
i0 i1 s0 0
A B
i0 i1 s0 1
2x1 mux
Selects input to connect to Y
selA == 1: connects A to Y selB == 1: connects B to Y
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Fig source: Prof. Subhashish Mitra
Multiplexers/selectors
2:1 mux: 4:1 mux: 8:1 mux: Z = A'I0 + AI1 Z = A'B'I0 + A'BI1 + AB'I2 + ABI3 Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 + AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
2 n -1 (m k=0
In general: Z =
kIk)
in minterm shorthand form for a 2n:1 Mux
I0 I1 I2 I3 4:1 mux A B
I0 I1
2:1 mux A
I0 I1 I2 I3 I4 I5 I6 I7
8:1 mux
A B C
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N-bit Mux Example
Four possible display items
Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide Choose which to display using two inputs x and y Use 8-bit 4x1 mux
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Mux example: Logical function unit
C0 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C2 0 1 0 1 0 1 0 1 Function 1 A+B (A B)' A xor B A xnor B AB (A + B)' 0 Comments always 1 logical OR logical NAND logical xor logical xnor logical AND logical NOR always 0
0 1 2 3 8:1 MUX 4 5 6 7 S2 S1 S0 C0 C1 C2
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Multiplexers as general-purpose logic
A 2n-1:1 multiplexer can implement any function of n variables
with n-1 variables used as control inputs and the data inputs tied to the last variable or its complement
Example: F(A,B,C) = ABC + ABC+ABC+ABC
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Demultiplexers/decoders
Decoders/demultiplexers: general concept
single data input, n control inputs, 2n outputs control inputs (called selects (S)) represent binary index of output to which the input is connected data input usually called enable (G)
1:2 Decoder: O0 = G S O1 = G S 2:4 Decoder: O0 = G S1 O1 = G S1 O2 = G S1 O3 = G S1
S0 S0 S0 S0
O0 O1 O2 O3 O4 O5 O6 O7
3:8 Decoder: = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0
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Demultiplexers as general-purpose logic (contd)
F1 = A'BC'D + A'B'CD + ABCD F2 = ABC'D' + ABC F3 = (A' + B' + C' + D')
0 1 2 3 4 5 6 4:16 7 DEC 8 9 10 11 12 13 14 15 A B C D A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD
Enable
CSE140: Components and Design Techniques for Digital Systems Arithmetic circuits
Tajana Simunic Rosing
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Design example: 1-bit binary adder
Inputs: A, B, Carry-in Outputs: Sum, Carry-out
Sum = A xor B xor Cin Cout = A B + A Cin + B Cin = A B + Cin (A xor B)
A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin Cout S 0 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 1 A B Cin Cout Cin A B S A B S A B S A B S A B S
S Cout
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Ripple-carry adder critical delay path
@0 A @0 B @N Cin @0 A @0 B late arriving signal @1 @N+1 Cout @N+2 @1 two gate delays to compute Cout A0 B0 A1 B1 A2 B2
S3, C4 Valid
S0 @2 C1 @2
4 stage adder
S1 @3 C2 @4 S2 @5 C3 @6 A3 B3 S3 @7 Cout @8
S0, C1 Valid
S1, C2 Valid
S2, C3 Valid
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T0 T2 T4 T6 T8
Carry-lookahead
Evaluate Sum and Ci+1
Sum = Ai xor Bi xor Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai xor Bi)
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Carry-lookahead implementation
Adder with propagate and generate outputs
Ai Bi Ci Pi @ 1 gate delay Si @ 2 gate delays Gi @ 1 gate delay
increasingly complex logic for carries
C0 P0 P1 P2 P3 G0 P1 P2 P3 G1 P2 P3 G2 P3 G3
C0 P0 G0 C0 P0 P1 G0 P1 G1
C1 @ 3
C0 P0 P1 P2 G0 P1 P2 G1 P2 G2 C3 @ 3
C2 @ 3
C4 @ 3
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Carry-lookahead implementation (contd)
Carry-lookahead logic generates individual carries
sums computed much more quickly in parallel however, cost of carry logic increases with more stages
0 0 A0 B0 S0 @2 C1 @2 C1 @3 A1 B1 S1 @3 C2 @4 C2 @3 A2 B2 S2 @5 C3 @6 C3 @3 A3 B3 S3 @7 Cout @8 C4 @3 S3 @4 C4 @3 22 S2 @4 S1 @4 S0 @2
A0 B0
A1 B1
A2 B2 A3 B3
Carry-lookahead adder with cascaded carry-lookahead logic
Carry-lookahead adder
G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 P = P3 P2 P1 P0
4 four-bit adders with internal carry lookahead second level carry lookahead unit extends lookahead to 16 bits
4 C12
4 A[11-8] P 4 S[11-8] @8 @5 C3
4 B[11-8] G C8
4 A[7-4] P 4 S[7-4] @7 @5 C2
4 B[7-4] G C4
4 A[3-0] P 4 S[3-0] @4 @4 C1
4 B[3-0] G C0 @0
A[15-12] B[15-12] 4-bit Adder P 4 S[15-12] @8 @2 P3 C16 C4 @4 G
4-bit Adder
4-bit Adder
4-bit Adder
@3 G3
@2 P2
@3 G2
@2 P1
@3 G1
@2 P0
@3 G0 C0 C0 @0
Lookahead Carry Unit P3-0 G3-0 @3 @5 C2 = G1 + P1 G0 + P1 P0 C0
C1 = G0 + P0 C0
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Carry-select adder
Redundant hardware to make carry calculation go faster
compute two high-order sums in parallel while waiting for carry-in one assuming carry-in is 0 and another assuming carry-in is 1 select correct result once carry-in is finally computed
C8
4-bit adder [7:4]
adder high
C8
4-bit adder [7:4]
adder low
five 2:1 mux
1 0 1 0
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1 0 1 0
C4
4-Bit Adder [3:0] S3 S2 S1 S0
C0
C8
S7
S6
S5
S4
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What weve covered thus far
Transistor design Delay estimates Pass transistors Muxes Demuxes Adders
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