Page: 1

Solution
ECE-438, MOS Transistor
Chapter 3, Digital Integrated Circuits, J. M. Rabaey, 2
nd
Edition
1) Given the data in the table below for a short channel NMOS transistor with
V
DSAT
=0.6V and k'=100A/V
2
, calculate V
T0
, , , 2|
f
( and W/L.
V
GS
V
DS
V
BS I
D
(A)
1 2.5 1.8 0 1812
2 2 1.8 0 1297
3 2 2.5 0 1361
4 2 1.8 -1 1146
5 2 1.8 -2 1039
For Short-Channel device:
2
min
min
( ) (1 )
2
D GS T DS
W V
I k V V V V
L

(
' = +
(

,
where V
min
= min(V
GS
-V
T
, V
DS
, V
DSAT
).
To begin with: the operation regions need to be determined.
For any of these data to be in saturation:
V
T
should be: V
GS
V
T
> V
DSAT
2- V
T
> 0.6 => 1.4 > V
T
This is a quite high value in our process. Thus, we can assume that all data are taken in
velocity saturation. We will check this assumption later.
In Velocity Sat.:
) 1 )(
2
(
DS
DSAT
T GS DSAT D
V
V
V V V
L
W
k I + ' = Eq.1
V
DSAT
and V
DS
are constant in 1 & 2 =>
2
2
2
1
2
1
DSAT
T GS
DSAT
T GS
D
D
V
V V
V
V V
I
I


= =>
3 . 0 2
3 . 0 5 . 2
1297
1812


=
T
T
V
V
=> V
T0
= 0.44V
Page: 2
In 2 & 3 V
DSAT
and V
GS
are constant =>
1
1297 1 1.8
0.08
1361 1 2.5
V

+
= =
+
Using data 2 & 4: V
T
= 0.587 V (1)
Using data 2 & 5: V
T
= 0.691 V (2)
Both these values satisfy V
T
< 1.4 V so all the data in our table were taken in velocity
saturation.
( )
F SB F T T
V V V | | 2 2
0
+ + =
(1) and (2) can be used along with V
T0
= 0.44 V to conclude:
1
2
0.29V = and 2 0.6
F
| = V
also using 2
nd
set of data
I
D
= 1297A and Eq.1 => 15
W
L
=
2) An NMOS device is plugged into the test configuration shown below in Figure P1.
The input V
in
=2V and the current source draws a constant current of 50A. R is a
variable resistor that can assume values between 10kO and 30kO. Transistor M
1
experiences short channel effects and has following transistor parameters:
k'=11010
-6
V/A
2
, V
T
=0.4 and V
DSAT
=0.6V. The transistor has a W/L=2.5/0.25. For
simplicity, body effect and channel length modulation can be neglected.
a) When R=10kO find the operation region, V
D
and V
S
.
b) When R=30kO again determine the operation region, V
D
and V
S
.
Figure P1
Page: 3
(a) R=10 O K therefore V V
D
2 05 . 0 10 5 . 2 = =
we can assume transistor is in SAT.
( )
2
2
T GS D
V V
L
W k
I
'
=
( )
2
6
6
4 . 0 2
25 . 0
5 . 2
2
10 110
10 50

S
V
Therefore, 3 . 1 =
S
V V.
As 3 . 0 =
T GS
V V , 7 . 0 =
DS
V and 6 . 0 =
DSAT
V , our assumption is correct and the
device is in saturation region.
(b) O = K R 30 therefore V V
D
1 05 . 0 30 5 . 2 = =
It is obvious that in this case the transistor is not in velocity saturation (because
S
V
Would be 1.22 which is greater than
D
V ) .
Assuming the device is in linear region
2
( )
2
DS
D DS GS T
V W
I k V V V
L
' =
( )
2
6 6
1
50 10 110 10 10(1 )(2 0.9 )
2
S
S S
V
V V

=
93 . 0 =
S
V
To check our assumption:
07 . 1 93 . 0 2 = =
GS
V
07 . 0 =
DS
V
So our first assumption is correct and 93 . 0 =
S
V
Page: 4
3) Consider the circuit shown in Figure P2.
a) Write down the equations (and only those) which are needed to determine the
voltage at node X. Do NOT plug in any values yet. Neglect short channel effects
and assume that
p
= 0.
b) Draw the (approximate) load lines for both PMOS transistor and resistor. Mark
some of the significant points.
c) Determine the required width of the transistor (for L = 0.25m) such that X
equals 1.5 V.
d) We have, so far, assumed that M1 is a long-channel device. Redraw the load
lines Assuming that M1(PMOS) is velocity-saturated. Will the voltage at X rise or
fall?
(Use Table 3-2, Page 103)
Figure P2
PMOS is always in Saturation.
a)
( )
2
2.5
2
p
X
X Tp
k
W V
V V
L R
'

=
b)
c)
( )
6
2 30 10 1
1.5 0.4
2 20
x W
L k

=
O
VSD, VX
VDD/R
=2.5/20k=125uA
Page: 5
W/L = 2.755 , W = 0.69 m
d)
Voltage at node X would go up since the current drive of PMOS is lower.
4) The circuit of Figure P3 is known as a source-follower configuration. It achieves a DC
level shift between the input and output. The value of this shift is determined by the
current I
0
. Assume device is in saturation = 0.4, 2||
f
| = 0.6 V, V
T0
= 0.43 V, k' = 115
A/V
2
, and = 0. The NMOS device has W/L = 5.4/1.2 such that the short channel
effects are not observed.
a) Derive an expression giving V
i
as a function of V
o
and V
T
(V
o
). If we neglect
body effect, what is the nominal value of the level shift performed by this circuit?
b) The NMOS transistor experiences a shift in V
T
due to the body effect. Find V
T
as a function of V
o
for V
o
ranging from 0 to 1.5V with 0.25 V intervals. Plot V
T
vs.
V
o
.
c) Plot V
o
vs. V
i
as V
o
varies from 0 to 1.5 V with 0.25 V intervals. Plot two
curves: one neglecting the body effect and one accounting for it. How does the
body-effect influence the operation of the level converter? At V
o
(body effect) =
1.5 V, find V
o
(ideal) and, thus, determine the maximum error introduced by body
effect.
Figure P2
VSD, VX
Page: 6
a)
2
( )
2
n
D i o t
k W
I V V V
L
'
=
2
D
i o T
n
I
V V V
W
k
L
=
'
Neglecting body effect V
T
=V
T0
T0
2
D
i o
n
I
V V V
W
k
L
= + +
'
0
2
D
t
n
I
Level Shift V
W
k
L
= +
'
LS = 0.8V
b)
( )
F SB F T T
V V V | | 2 2
0
+ + =
( )
0.43 0.4 0.6 0.6
T o
V V = + +
Page: 7
c)
2
D
o i t
n
o
I
V V V
W
k
L
=
'
Plot Vi versus Vo for two different cases:
1) V
T
= V
T0
(neglecting body effect, =0)
If body effect is neglected, Vi=Vo+constant (linear relation)
Vo=1.5 V ==> Vi=2.3V
2) V
T
= V
T
(V
o
) (accounting for body effect, =0.4)
Vo=1.5V ==> Vi=2.57 V
Maximum error due to body effect=2.57-2.3=0.27 V.
Page: 8
5) The curves below in Figure P4 represent the gate voltage (V
GS
) vs. drain current (I
DS
)
of two NMOS devices, which are on the same die and operate in sub-threshold region.
Due to process variations on the same die the curves do not overlap.
Also assume that the transistors are within the same circuit configurations as Figure P5 in
If the input voltages are both V
in
= 0.2V. What would be the respective durations to
discharge the load of C
L
= 1pF attached to the drains of these devices.
(Assume voltage charge for C
L
is 1V)
Figure P4
Figure P5
Page: 9
V
in
= 0.2
I
DS
= 3 e8 A (1)
Or
V
in
= 0.2
I
DS
= 5 e9 A (2)
V
t C
I
A
A =
1
8
1
1 33.3
3 10
t pF s
x

A = =
2 9
1
1 200
5 10
t pF s
x

A = =
6) Compute the gate and diffusion capacitances for transistor M1 of Figure P6.
Assume that drain and source areas are rectangular, and are 1 m wide and 0.25 m long.
Use the parameters of Example 3.5 to determine the capacitance values. Assume m
j
= 0.5
and m
jsw
= 0.44. Also compute the total charge stored at input node, for the following
initial conditions:
a) V
in
= 2.5 V, V
out
= 2.5 V, 0.5 V, and 0 V.
b) V
in
= 0 V, V
out
= 2.5 V, 0.5 V, and 0 V.
Figure P6
0.5
Page: 10
Cox = 6 fF/m
2
, MOS dimensions L = 0.25m and W = 1m
Cut-off : C
g
= C
ox.
WL + 2C
o.
W
Linear : C
g
= C
ox.
WL + 2C
o.
W
Sat-Vel.Sat: C
g
= 0.66C
ox.
WL + 2C
o.
W
Diffusion Cap (C
d
) NOTE: Ldrain=0.5um (drain length) is not L for the MOSFET
(2 )
d j D D jsw P D
C C L W C L W = + +
0
0
1
j
j
DS
j
C
C
V
m
|
=
| |
+
|
\ .
0
0
1
jsw
jsw
DS
jsw
C
C
V
m
|
=
| |
+
|
\ .
a) V
in
= 2.5V,
V
out
= 2.5V Vel. Saturation.
C
g
= 1.62 fF , Q = 4.05 fC = 4.05 e 15 C
C
d
= 0.827 fF
V
out
= 0.5 V Linear Reg.
C
g
= 2.12 fF , Q = 5.3 fC
C
d
= 1.263 fF
V
out
= 0 V Linear Reg.
C
g
= 2.12 fF , Q = 5.3 fC
C
d
= 1.56 fF
b) V
in
= 0V => Cut off
Regardless of V
DS
C
g
= C
ox.
WL
C
g
= 2.12 fF, Q =0
And C
d
s are the same as Part a.
V
in
= 2.5V => C
d
= 0.827 fF
V
out
= 0.5 V => C
d
= 1.263 fF
V
out
= 0 V => C
d
= 1.56 fF
D
D
-
-
mj
mjsw
Cd=Cj*Area+Cjsw*perimeter
Drain Area=W*Ldrain
Drain Perimeter=W+2Ldrain