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Zero Address Instructions

Zero address instructions contain no address fields and implicitly use a stack to access operands. One address instructions use an accumulator register and one memory operand address. Two address instructions specify two registers or memory locations as source operands and one destination register or location. Three address instructions specify three register or memory addresses for two source operands and one destination.

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4K views3 pages

Zero Address Instructions

Zero address instructions contain no address fields and implicitly use a stack to access operands. One address instructions use an accumulator register and one memory operand address. Two address instructions specify two registers or memory locations as source operands and one destination register or location. Three address instructions specify three register or memory addresses for two source operands and one destination.

Uploaded by

Salman Muhammad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Zero Address Instructions

An instruction that contains no address fields; operand sources and destination are both implicit. It may for example enable stack processing: a zero-address instruction implies that the absolute address of the operand is held in a special register that is automatically incremented (or decremented) to point to the location of the top of the stack. Example: ADD The above instruction consists of an operation code only. It has no addrss field. The operation has the effect of popping the two top numbers from the stack, adding the numbers and pushing the sum into the stack. Here all operands are performed within stack. To evaluate arithmetic expressions, they must be first converted into reverse polish notation. The operand at address X is pushed on to the top of the stack. Automatically the stack pointer is incremented. Example: X=(A + B) + (C + D) PUSH A ; TOS <- A top of the stack PUSH B ; T0S <- B ADD ; TOS <- A + B PUSH C ; TOS <- C PUSH D ; TOS <- D ADD ADD ; ; TOS <- C + D TOS <- (C + D) + (A + B) M [X] <- TOS

POP X ;

One Address Instructions


One address instructions computers needs one address field. An implied accumulator (AC) register is used for all data manipulation. Here all the operations are carried out between the accumulator register and a memory operand. ADD X It denotes the operation, AC <-- AC+ M[X] Where AC = Accumulator register

M[X] = Memory operand at address X.

Example: X=(A + B)X(C + D) LOAD A ; ADD B ; AC <- M [A] AC <- AC + M[B]

STORE T ; M [T] <- AC LOAD C ; AC <- M [C] ADD D MUL T ; ; AC <- AC + M[D] AC <- ACxM[T]

STORE X ; M[X] <- AC

Two Address Instructions


In this format each address field specify either a processor register or a memory word i.e., they contain two address fields. ADD R1, R2 It denotes the operation, R1 <-- R1 + R2 Here the destination register is the same as any one of the source registers. Mov R1, R2 It denotes the operation, R1 <-- R2 It transfers the content of register R2 to register R1. ADD R1, X It denotes the operation, R1 <-- R1 + M[X] Where R1 = Processor register M[X] = Memory operand at address X.

Example: X=(A + B)-(C + D) MOV R1,A ; ADD R1,B ; MOV R2,C ; ADD R2, D ; SUB R1,R2 ; MOV X,R1 ; R1 <- M[A] R1 <- R1 + M [B] R2 <- M [C] R2<-R2 + M[D] R1 <- R1 - R2 M[X] <- R1

Three Address Instructions


Three address instructions computer needs three register address fields. The register address field may be a processor register or a memory operand. Cyber 170 computer needs three address instructions . ADD R1, R2, R3 The above instruction denotes the operations, R1 <-- R2 + R3 (arithmetic addition) Where R2, R3 = Source registers R1 = Destination register For Example: ADD R1, A, B R1M[A] + M[B]

As shown, it is clear that in the instruction 3 addresses are specified. In the above instruction one register address and two memory addresses are specified. Example of computer using this type of instructions Cyber 170.

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