CAD for VLSI Design - I
Lecture 15 V. Kamakoti and Shankar Balachandran
Overview of this Lecture
Understanding Behavioural Modeling
The highest level of abstraction Close to procedural languages Used for modeling and also testbench creation
Behavioral Modeling
Learning Objectives
Use of structured procedures always and initial Delay-based, Event-based and Level-sensitive timing controls Conditional statements if and else Multiway branching case, casex and casez Looping Statements while, for, repeat and forever Blocks sequential and parallel blocks, naming and disabling blocks.
The initial Statement
An initial block (initial begin end) may consist of a group of statements (within begin end) or one statement Each initial block starts at execution time 0 All initial blocks starts concurrently executing and finishes independent of each other. Typically used for initialization, monitoring, waveforms and to execute one-time executable processes.
The always statement
Model a block of activity that is repeated continuously in a digital circuit Equivalent to an infinite loop Stopped only by $finish (power-off) or $stop (interrupt)
Timing Controls
Delay-Based
Regular delay control Intra-assignment delay control Zero delay control
Regular Delay Control
parameterlatency=20; parameterdelta=2; reg x,y,z,p,q; initial begin x=0;//nodelaycontrol #10y=1;//delaycontrolwithaconstant #latencyz=0;//delaycontrolwithidentifier #(latency+delta)p=1;//delaycontrolwithexpression #yx=x+1;//delaycontrolwithidentifier #(4:5:6)q=0;//delaywithmin,typ,andmaxvalues end
Intra-assignment delay control
Assigning delay to the right of the assignment operator The intra-assignment delay computes the righthand-side expression at the current time and defer the assignment of the computed value to the left-hand-side variable. Equivalent to regular delays with a temporary variable to store the current value of a righthand-side expression
Intra-assignment Delay
reg x,y,z; initial begin x=0;z=0; y=#5x+z;//Takevalueofxandzatthetime=0,evaluate x+zandthen //wait5timeunitstoassignvaluetoy.Anychangetoxandz after //time=0andbefore5willnotaffectthevalueofy end //Theabovecodeisequivalentto //x=0;y=0;temp_xz =x+z;#5y=temp_xz; //where,temp_xz isatemporaryvariable
Zero delay control
Procedural statements inside different always-initial blocks may be evaluated at the same simulation time. The order of execution of these statements in different always-initial blocks is nondeterministic and might lead to race conditions. Zero delay control ensures that a statement is executed last, after all other statements in that simulation time are executed. This can eliminate race conditions, unless there are multiple zero delay statements, in which case again nondeterminism is introduced.
Zero delay control
initial begin x = 0; y = 0; end initial begin #0 x = 1; //zero delay control #0 y = 1; end //At time = 0, x = 1 and y = 1
Event-based timing control
Regular event control Named event control Event OR control
Regular Event Control
@(clock) q = d; @(posedge clock) q = d; @(negegde clock) q = d; q = @(posedge clock) d;
Named event control
event received_data always @(posedge clock) begin if (last_data_packet) -> received_data; end always @(received_data) data_buf = {data_pkt[0], data_pkt[1]};
Event OR control
// Sensitivity list always @(reset or clock or d) // if any one of reset,clock,d changes its value begin if (reset) q = 1b0; else if (clock) q = d; end
Level-Sensitive Timing Control
always wait (count_enable) #20 count = count + 1; This monitors the variable count_enable and if it is zero, it will not enter. When it becomes one, then after 20 units of time it will increment the variable count. If count_enable stays at 1, then count is incremented every 20 units
Conditional Statements
The if-else statement if (logical_expression) then <block> else <block> <block> = single statement or begin <block> end Nested if-else
if <block> else if <block> else if <block>
Multiway Branching
The case statement The casex and casez statements
The case statement
This compares 0,1,x and z of the condition, bit by bit with the different case options. If width of condition and a case option are unequal, they are zero filled to match the bid width of the widest of both.
The case Statement
//A 4-to-1 Multiplexer always @(s1 or s0 or i0 or i1 or i2 or i3) case ({s1,s0}) 2d0: out = i0; 2d1: out = i1; 2d2: out = i2; 2d3: out = i3; 2bx0, 2bx1, 2bxx,2b0x,2b1x: out = 1bx; 2bxz, 2bzx, 2bzz: out = 1bz; default: $display(Invalid Control signals); endcase
The casex and casez statements
casez does not compare z-values in the condition and case options. All bit positions with z may be represented as ? in that position. casex does not compare both x and zvalues in the condition and case options
An example
casex (encoding) 4b1xxx: next_state = 3; 4bx1xx: next_state = 2; 4bxx1x: next_state = 1; 4bxxx1: next_state = 0; endcase //encoding = 4b10xz will cause next_state=3
Parallel Blocks
initial begin fork x = 1b0; #5 y = 1b1; //After 5 units #10 z = {x,y}; //After 10 units join #20 w = {y,x}; end
Named Blocks
initial begin j = 0; begin:block1 //Naming while (j < 16) begin if (flag[j]) begin $display(Encountered TRUE bit at %d,j); disable block1; end j = j + 1; end //while end //block1 end//initial
Loops
while (condition) <block> for (count = 0; count < 128; count = count + 1) <block>
repeat (value) <block>
The value should be a constant or variable, and the evaluation of the variable will be done at start of loop and not during execution
forever loop
initial begin clk = 1b0; forever #10 clock = ~clock; end
Questions and Answers
Thank You
