Control Unit Design
Decoder & Sequencer S Operation Code (inc. addr. mode) ALU PC +1 IR MAR ACC X
ME WR OE
Address
Data
RAM
Here the operand is separate from the opcode, it may be loaded into the MAR for direct/indirect addressing or used in a calculation for immediate/indexed addressing. This is typical for CISC machines employing a variable instruction length.
76
Control Unit Design
Decoder & Sequencer Feedback from ALU Control to other units Combinational Logic
S T A T E
Operation Code
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Control Unit Design
Control Memory Bus Enable Reg, OE, Load IR, WR, Sel PC. Register O/P Bus Enable ACC, Enable X, Enable S, Enable PC. Register I/P Bus Load ACC, Load X, Load S, Load PC, Inc PC, Load MAR. ALU F0-F5 (ALU function), Multiword, Plus 1, Arithmetic Shift. Update C, Update V, Update N, Update Z. Feedback Condition Codes C, V, N, Z.
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Instruction Set Summary
Arithmetic Instructions
Inherent Immediate Direct Indirect Indexed Indexed Indirect Stack (pull)
#2
#2
#3
#4
#3
#4
#4
CLR INC DEC NEG COM LSL LSR ASR ROL ROR ADD SUB ADC SBC AND OR EOR
79
Instruction Set Summary
Load Register from Memory
Immediate Direct Indirect Indexed Indexed Indirect Stack (pull)
#2
#3
#4
#3
#4
#4
LDA LDX LDS
Store Register to Memory
Direct Indirect Indexed Indexed Indirect Stack (push)
#3
#4
#3
#4
#3
STA STX STS
80
Instruction Set Summary
Control Transfer Instructions1
PC Relative Direct Indirect Stack (pull)
#2
#4
#2
#4
#3
#5
#4
BRA BRN BCC BCS BVC BVS BEQ BNE BLT BGE BGT BLE BSR JMP JSR RTS
note that the BSR & JSR are identical to the BRA & JMP instructions except that BSR & JSR store the old PC value on the stack for later retrieval by RTS.
1
81
Control Unit Design
Complexity Consider the complexity for an implementation using synchronous memory2: 28 Control signals 4 Feedback signals 8-bit State (205 States) 7-bit Opcode (97 Operation Codes) - - 39 Instructions - - 9 Addressing Modes Combinational logic has 19 (4+7+8) inputs and 36 (28+8) outputs.
2
ME = CLK hence no wait states
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Control Unit Design
Options Hardwired Logic Computer assisted formal methods for random logic Large & complex PLA More compact Size limited even this problem is too big for a single PLA Microcode Simple implementation of complex control task Control is reduced to a software problem
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Control Unit Design
Microcode
Decoder & Sequencer Control to other Microcode Memory units
Microinstruction PC +1 Address Select Logic Feedback from ALU
Operation Code
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Control Unit Design
Microcode Instructions
Memory Reg O/P Reg I/P ALU Control Jump Address Cond Control to other units To address select
a new microinstruction is executed every cycle each instruction contains all the control signals required during a particular clock cycle the signals are usually arranged into elds according to function
85
Control Unit Design
Microcode Execution Operation code maybe simply a microcode address. In each cycle the Microinstruction Program Counter may be loaded with one of the following: PC + 1 execute next microinstruction (default) Opcode begin execution of next macroinstruction after instruction fetch Jump Address jump to another section of microcode may be dependent on ALU feedback
86
Control Unit Design
Field Encoding Even for this simple example we have a very wide microinstruction. To reduce the size of the microcode memory it is usual to encode the microinstruction elds. Since only one register may drive the Register O/P bus we can encode the eld from four bits down to two3:
Encoded Field
0 0 1 1
3
0 1 0 1
Enable_ACC Enable_X Enable_S Enable_PC
although the microcode memory is now smaller we will need some form of additional decoding
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Control Unit Design
Two Level Microcode Many microinstructions will have the same control signals. With a two level microcode/nanocode system we can merge such instructions. Microcode - - large number of narrow microinstructions - - controls sequence of microinstructions - - controls selection of nanoinstructions Nanocode - - small number of wide nanoinstructions - - provides control to other units
88
Control Unit Design
Nanocode System
Decoder & Sequencer
Microcode Memory Nanocode Memory Control to other units
Microinstruction PC +1 Address Select Logic Feedback from ALU
Operation Code
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Control Unit Design
To simplify the control unit for use in high clock rate modern microprocessors we can rst separate the tasks of sequencing and decoding:
Sequencer Decoder Feedback from ALU S T A T E
Combinational Logic
Combinational Logic
Control to other units
Operation Code
Here the sequencer merely keeps track of instruction execution.
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Control Unit Design
The majority of the controller state is in the instruction register. Careful choice of opcodes can signi cantly reduce decoder complexity4.
Macroinstruction elds
Function Type of instruction - Arithmetic/Logic - Load - Store - Control Transfer Addressing Mode Immediate Data
Division of the instruction into elds will simplify the decoder and sequencer at the expense of a less ef cient instruction coding. The best results are obtained for RISC style architectures.
4
choice of opcodes is now a problem in state allocation.
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RISC
SHIFTER
ALU Decoder & Sequencer
IR
R0 (=0) R1 R2 R3 R4 R5 R6 R7 PC MAR
ME WR OE
Address
Data
RAM
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RISC Typical RISC
Register register architecture Few instructions Very few addressing modes The processor described here is based on a subset of the SPARC speci cation5.
set
5
note that SPARC is not an architecture only a speci cation based around a complete instruction
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RISC
F4 F1 F0
Co
D Q
Vo
D Q
Dest[31:0]
S1 F2
S2
Dest[31]
D Q
D Q
Clk
Co
F3 C F1:F0
32 bit Adder
Vo
00
01
10
11
Dest
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RISC
The ALU supports a small number of functions based on only ve control signals. A separate barrel shifter supports three simple shift instructions.
ALU instructions
F1:F0 F4:F3:F2
000 001 010 011 100 101 110 111
Shift instructions
00 ADD SUB ADDX SUBX ADDcc SUBcc ADDXcc SUBXcc
01 AND ANDN ANDcc ANDNcc
10 OR ORN ORcc ORNcc
11 XOR XNOR XORcc XNORcc
SLL SRL SRA
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RISC
All ALU and shift instructions take two operands (either two registers or one register and one immediate) and return a single register result. SUBX R3,R7,R5 R5 R3 ; R7 ; C ADD R4,5,R1 R1 R4 + 5 for special cases we have a pseudo register, R0, which always contains zero. SUB R0,R2,R2 R2 ;R2 we may even execute an instruction merely for its side effects
0 0 0
SUBcc R5,201,R0
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RISC Instruction Format
Arithmetic and logic instructions contain all the relevant elds for register selection and ALU control. The decoder is responsible for enabling these elds during the correct cycle.
Format field Function Code Addressing mode
10
rd
Destination
F4:F0
ALU function
rs1
Source 1
ignored
rs2
Source 2
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RISC Variable Instruction Format
The use of variable elds allows us to specify more information within a limited instruction width6. For simplicity the signed immediate may only be used on the s2 bus.
10 rd 0
F4:F0
rs1
ignored
rs2
Addressing mode
10
6
rd
F4:F0
rs1
simm13
note that the rs2 eld is not always present but when present it is always in the same place.
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RISC
Shift instructions are indicated by a different function code. The decoder will use a part of the function code in order to select which functional unit drives the destination bus.
Format field Function Code
10
rd
1001
rs1
0 1
ignored
rs2
simm13
01 = SLL 10 = SRL 11 = SRA
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RISC
Load and store instructions use similar instruction formats.
LD R3+R7],R5 ST R1, R4+5]
Format field Function Code
MAR R3 + R7 R5 mem(MAR) MAR R4 + 5 mem(MAR) R1
0 0 0 0
11
rd
000
00
rs1
0 1
ignored
rs2
simm13
0 = LD Destination (LD) 1 = ST Source (ST)
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RISC
Control Transfer instructions.
Format field
CALL
01 disp30
Since instructions are word aligned, any location within the 4 GByte address space may be accessed via the CALL instruction7.
CALL label
R15 PC
PC PC + (disp30
101
4)
A price is paid for this facility R15 is xed as the register storing the return address
RISC
Control Transfer instructions.
Format field Function Code
Bicc
0 0 a cond 0 1 0
0000 = BN 0001 = BE 0010 = BLE 0011 = BL 0100 = BLEU 0101 = BCS 0110 = BNEG 0111 = BVS
disp22
1000 = BA 1001 = BNE 1010 = BG 1011 = BGE 1100 = BGU 1101 = BCC 1110 = BPOS 1111 = BVC
The conditional branch instructions have a shorter range since they need eight bits to specify the branch condition and the annul8 status. BNE label If (Z = 0) then PC PC + (disp22 4)
0
not documented here
102
RISC
Control Transfer instructions.
Format field Function Code
JMPL
10 rd 111000 rs1 0 1
ignored
rs2
simm13
This instruction allows a register indirect jump. Since it saves the old program counter it may be used to jump to or return from a subroutine. JMPL rs1+rs2,rd rd PC PC rs1 + rs2
0 0
The documentation given here for control transfer instructions has omitted any mention of the pipelining and register window features of the SPARC speci cation. The resulting description is self consistent but inaccurate.
103
RISC
Using an ADD instruction we can set the value of a register in the range -4096 to +40959.
ADD R0,simm13,rd
rd
simm13
The SETHI instruction enables the setting of the more signi cant register bits.
Format field Function Code
00
rd
100
0
imm22
SETHI imm22,rd
9
rd < 31 : 10 > rd < 9 : 0 >
104
imm22
note that the signed immediate is sign extended before placement on the s2 bus
RISC
Manipulation of immediate and displacement values:
Sign Extended s s s s s s s s s s s s s s s s s s s s s Word Aligned disp30 disp30 Sign Extended & Word Aligned s s s s s s s s s s Shift Left by 10 imm22 imm22 0 0 0 0 0 0 0 0 0 0 0 0 simm13 simm13
ADD
CALL
BVC
disp22 disp22 0 0
SETHI
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