Addressing Mixed-Signal SoC Physical Design Challenges Ernie Koeroghlian Mentor Graphics Corporation April 2010

ABSTRACT Design teams have adopted the mixed signal simulation flow to address the increased demand for mixed mode functionality on a single chip. The physical design environment could benefit from a similar approach to managing two domains in a single environment. Logic driven layout for analog design is becoming more widely adopted and polygon pushing is taking a back seat to parameterized cells and callback functions. There is a great opportunity now to incorporate the tools for managing the mixed language flow into the physical world to provide better design planning and area utilization for IC design. SECTION 1: MIXED-SIGNAL PHYSICAL DESIGN CHALLENGES The growing complexity and functionality of SoC designs continues to increase the number of mixed signal SoC chips. End user applications, including cell phones, mp3 players, cameras and hearing aids are driving demand for broader functionality on single devices. This demand for increasingly diverse capabilities on a single device, combined with the need for longer battery life, lower power consumption and smaller sizes has driven the development of mixed-signal devices on a single chip. More design teams, both digital and analog, are incorporating foreign blocks into their design. The methodology for planning, implementing and assembling digital blocks is well-defined and understood. In cases where the digital component comprises the majority of the design, analog blocks are generally included as abstractions and handled as black boxes, isolated from the rest of the layout. For analog design teams the problem is more complex, as both the analog and small digital blocks are often implemented by the same group. Analog design teams generally do not create abstractions of analog blocks and move them into a digital design environment. SECTION 2: CONVERGING DESIGN AND SIMULATION METHODOLOGIES The integration of language and schematics for mixed mode simulation is well defined and widely used by SoC design teams today. The simulation process has become streamlined with utilities that enable registration of analog and digital blocks in the same environment making it easier for the design team to manage both domains and the interfaces between them. This integration on the design side enables teams to verify the functionality on a completely integrated system much earlier in the design process. Issues found earlier in the process are much easier to fix, saving time and potentially expensive silicon spins to see if the final integration is correct.

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This methodology has not yet been carried over to the physical design planning and implementation flow. The layout flow from chip planning to implementation for SOC design is split into a few disconnected design methodologies.

Figure 1: The mixed signal design flow takes two separate paths during the physical implementation phase making it difficult to perform accurate floor planning and area estimation.

SECTION 3: LOGIC DRIVEN PHYSICAL PLANNING AND IMPLEMENTATION Managing the logic sources the physical design environment in a similar method to the mixed signal simulation flow would provide many benefits to the project team. Chip and block planning could be done much more precisely earlier in the project enabling tradeoffs early in the planning cycle as well as accelerate block implementation and integration. Mixed signal SoC floor planning and area estimation are still done manually. Analog block area is calculated by hand and then combined with the digital block area which is calculated in a separate tool. This requires a conversion step of the digital block from an external tool. This is true even when the logic sources are managed in a common environment for design and simulation. Block layout implementation is split into two methodologies. Digital blocks are passed off to an automated place and route tool, sometimes in another group. Analog custom layout is done with a mixture of polygon editing and more recently parameterized cells and interactive routing utilities.

Analog designers start with schematic capture which is converted to SPICE for simulation and physical verification. The logic source is either used to drive layout through a schematic driven layout flow or as a guide for manual polygon editing, although this is becoming less common as the newer technologies are forcing more control over the layout process.

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There is still no standard methodology for building a full chip, including chip planning, using the mixed language flow. This is a big opportunity for end users and EDA vendors to provide a structure and methodology to improve this process. SECTION 4: SMALL TECHNOLOGIES ARE CATALYST FOR LOGIC DRIVEN CUSTOM LAYOUT The effects of smaller technologies are driving a dramatic increase in design rules. This is stretching layout designers ability to memorize and apply the rules while keeping pace with project sch edules. As a result there is more willingness to adopt parameterized cells and callbacks for custom layout, even at the expense of some flexibility to the layout designer. Parameterized cells alone enable layout designers to be more efficient by reducing the steps to create individual devices, although they limit the flexibility of full custom polygon pushing. However, they offer a much more valuable benefit for physical planning and layout. Eliminating hand drawn devices makes it much easier to adopt a logic driven flow for analog layout and enables design teams to deliver more predictable results both in schedule and circuit performance. The parameterized cells are design rule and electrically correct. They require no manual changes once they have been constructed and can be regenerated when the logic changes. For a given set of device parameters, driven from the logic source their area can be calculated and can be incorporated into the floorplan before blocks are fully implemented. They also provide built-in connectivity information which can support placement and custom routing. This provides an opportunity to introduce guided semi automation for the layout designer without eliminating their ability to achieve handcrafted results. SECTION 5: THE INTEGRATED MIXED SIGNAL ENVIRONMENT Having an environment that supports registering logic models for the various levels of the design makes it possible to specify how blocks are constructed for the mixed signal layout flow. Once the blocks are registered it is a matter of building an associated hierarchical model in the layout environment and distributing the blocks for implementation. Analog blocks have historically been built using a bottom up full custom approach while digital blocks are built top down through a synthesis flow. An integrated environment that can handle floor planning with area estimation and power planning for the hierarchical design model is ideal for mixed signal design. Digital block area estimation is calculated using the information in the standard cell library and the analog block area estimation is calculated using the parameterized cells with a routing overhead. Once blocks have been created and pin placed layout can begin. In the mixed signal layout environment both digital and analog blocks can be created and assembled without the need for data conversion. The integrated logic source can be used to drive both sides of the flow. Once the logic is constructed for the custom analog blocks logic driven layout with parameterized cells and callbacks can be used to create and place devices. This can be done either manually or through an automated placer. Once the cells have been placed fly lines provide guidance for the user for build interconnect. This can be accomplished either manually or with automation tools.

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Once the block is verified it can be assembled with the other blocks within the same integrated environment. Top level block interconnect can be done either manually or using automatic or semi automatic routing tools.

Figure 1: The mixed signal design flow takes two separate paths during the physical implementation phase making it difficult to perform accurate floor planning and area estimation. SECTION 6: SUMMARY Combining the digital and analog domains in a single unified physical design environment can reduce much of the manual integration that is done today. Waiting until the end of the project to integrate and verify a design can have a negative schedule impact. The adoption of logic driven analog layout and device generators is the first step in applying automation to a flow that has historically been done by hand. The effects introduced with smaller technologies are driving the need to push analysis closer to the front end of the physical design process. Adoption of a logic driven flow provides an entry point for design tools to integrate the logic and physical data sooner in the process with analysis tools. This will help identify and address integration problems sooner in the design process. ICassemble provides such an integrated chip assembly environment.

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