3.

3 Analysis and Optimization of Accumulation-Mode Varactor for RF ICs

Theerachet Soorapanth, C. Patrick Yue, Derek K. Shaeffer, Thomas H. Lee, S. Simon Wong Center for Integrated Systems, Stanford University, Stanford, CA 94305
Abstract- This paper presents a novel RF IC varactor implemented in standard CMOS process. This device has shown a remarkable tuning range of 150%, sensitivity of 300%/V, and quality factor of 23 at 1 GHz. A physical model of t h e varactor is presented and confirmed with measured data. Using the model derived, optimization has shown that a Q as high as 200 can be achieved.

, s p

I S/D
Fig. 1. Cross-section of accumulation-mode varactor

I. INTRODUCTION
High quality on-chip varactors are essential to monolithic integration of voltage-controlled oscillators in a Si-based RF ICs. Conventionally, on-chip varactors have been implemented with pn junctions under reverse bias or MOS capacitors in depletion-inversion regime. PN-junction varactors have been reported with quality factor (0) of less than 7 for capacitance of 1-10 pF at 0.9-2.4 GHz. Typical MOS capacitors can achieve higher Q (14/GHz/pF) with larger capacitance per area [l]. In this paper, we present a novel varactor based on an NMOS-like structure biased in accumulation-depletion regime. A physical model is presented and verified with measured data. Based on the derived model, device optimization is performed. 11. PHYSICAL MODELS A cross-sectional view of the accumulation-mode varactor is shown in Fig. 1. The structure is similar to an nchannel MOSFET with the exception of being fabricated in an n-well instead of the normal p-substrate. This choice was made to eliminate the parasitic pn-junction capacitances at source and drain that would otherwise limit the tuning range. An alternative structure using a p-channel MOSFET in a p-well/substrate has inferior quality due to lower carrier mobility. The basic operation of this device is similar to a standard MOS structure [2]. When the applied voltage (V,) is far above the flatband voltage (VFB), the silicon surface is accumulated with electrons provided by the n+ regions and the capacitance seen from the gate is simply the oxide capacitance. As V, is decreased towards VFB, the silicon surface is less accumulated and eventually becomes charge-free at flatband, beyond which the surface undergoes depletion. From deep accumulation to strong

Fig. 2. (a) Accumulation model. (b) Depletion model.

model is similar to the accumulation model with additional depletion capacitance Cd at the accumulation-layer-to-S/D interface. By performing network transformation on the models, equivalent series resistance R, and capacitance C, can be derived and Q can then be computed as l/(wR,C,).
111. EXPERIMENTAL RESULTS AND DISCUSSION

A varactor shown in Fig. 3 was fabricated in a standard 0.5-pm CMOS process with effective channel length of 1.95 pm. ,511 was measured using an HP8720B Network Analyzer and Cascade Microtech coplanar ground-signalground probes. R, and Cs are extracted and plotted in Fig. 4 and 5 , respectively. The measured C, exhibits a norma1 high-frequency C-V characteristic and remains relatively independent of frequency up to 3 GHz beyond which the parasitic series inductance L , causes C, to appear increasing with frequency. The effective series capacitance Cs,eff can be described by C,/(l - w2L,C,). According to this expression, C s , edeviates ~ noticeably from C, at high frequencies under accumulation condition as observed in

depletion, the capacitance varies from a maximum to a

minimum value. The region of interest where capacitance changes involves both accumulation and depletion operations. The models under these operating conditions are shown in Fig. 2. In accumulation, the overall capacitance is mainly the series combination of the oxide capacitance CO,and semiconductor capacitance Csi. Loss is represented by a combination of gate resistance R, , accumulation-layer resistance R,,,, S/D resistance Rd, and well resistance R,. In depletion, the silicon surface consists of fixed donor charges only and lacks conducting majority carriers. The depletion

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N (no of gate fingers) = 1 4

Fig. 3. Layout of the varactor tested

1998 Symposium on VLSl Circuits Digest of Technical Papers

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0-7803-4766-8/98/$10.00 0 1998 IEEE

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Fig. 6. Measured and Modeled Q

Fig. 4. Measured and Modeled effective series capacitance Cs,efi

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Fig. 5. Measured an83 Modeled series resistance R,

pled through the well has less effect. The optimization is conducted for a nominal capacitance of 1p F with f 30%tuning capability at 1 GHz. Fig. 7 shows the resulting optimal Q, W, L, and N as a function of maximum allowed area. As a larger area is allocated, Q can be increased to a maximum of 200, beyond which further area increase yields no improvement. This limit is achieved when L reaches a minimum governed by process technology. The result is consistent with the fact that Q in accumulation is largely determined by R,,, which is proportional to L and inversely proportional to W and N. This plot serves as a design tool for high-quality varactors.

Fig. 4. The series resistance R , in accumulation increases as V, is swept from deep accumulation towards flatband. This is due to an increase in accumulation-layer resistance R,,, as majority carriers are extracted out through the n+ regions. Below flatband, surface dopants are depleted leaving behind fixed donor charges. In depletion, loss is dominated by the well resistance R,. R, decreases below flatband because the depletion capacitance Csi decreases, which reduces the effect of R,. The measured R, shows a slight frequency dependene which is unnoticeable in the model. This minor discrepancy can be attributed to the distributed nature of the well parasitic$,which is not adequately modeled by a single lumped RC element. Measured and modeled varactor Q are shown in Fig. 6. In general, the modeled and measured results show excellent agreement. In accumulation, R,,, dominates the loss behavior. In depletion, the loss mechanism is dependent on the distributed well parasitics. Q reaches a minimum value around the flatband voltage where Cs variation is large and R, is near maximum. This indicates a direct trade-off between Q and sensitivity, which can be specified as a constraint in device optimization.

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Fig. 7. Optimal Q, W, L, N vs allowed device area

V. CONCLUSIONS

A novel IC varactor is presented along with a physical model which has been verified with experimental data. Through optimization, design parameters for achieving Q as high as 200 have been determined.

ACKNOWLEDGMENTS
The authors would like to thank Rockwell International for fabricating the test devices.

Iv. DEVICE OPTIMIZATION

Based on the derived model, optimization can be performed to determine the design parameters for achieving maximum Q in a given area. The device parameters, effective width (W), effective length (L) and number of gate fingers (N) are as defined in Fig. 3. The device is chosen to operate in accumulation mode where substrate noise cou-

REFERENCES
[l] J.N. Burghartz, M. Soyuer, K.A. Jenkins, Integrated RF and

Microwave Components in BiCMOS Technology, IEEE h n s actions on Electron Devices, vol. 43, no. 9, Sept 1996. [2] R.H. Kingston, S. F. Neustadter, Calculation of the Space Charge, Electric Field, and Free Carrier Concentration at the Surface of a Semiconductor, Journal of Applied Physics, vol. 26, no. 6, June 1955.

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