Al-Balqa'a Applied University
Al-Huson College
Experiment #: 11 11 11 11
Experiment Subject: Transistor Voltage Divider
Biasing.
Date of Experiment: 7/8/2007 - (11:30-2:30)
Sunday & Thursday
Student Name: Mohmmed Sami Ibrahim Issa
Student No.: 30519127076 30519127076 30519127076 30519127076
Specialization: Communication & Software
Engineering.
Supervisor: Dr.Amjad Al-Hendi
Eng.Ahmad Btaenh
ive Object
To verify the voltages and currents in a transistor voltage divider
bias circuit and to construct its dc load line.
INTRODUCTORY THEORY
The transistor voltage divider bias circuit is one of the transistor
biasing schemes which is commonly used because it stabilizes
the Q point, which means that the Q point is independent of the
value of dc, since the base current is made small compared with
the currents through the two base ("voltage-divider") resistors
EQUIPMENT REQUIRED
2-1-k resistors, 1/4W
1-4.7-k resistor, 1/4W
1-10-k resistor, 1/4W
1-10- k potentiometer
2N3904 NPN silicon transistor
0-15 V dc power supply
VOM or DMM (preferred)
Breadboarding socket
EXPERIMENTAL PROCEDURE EXPERIMENTAL PROCEDURE EXPERIMENTAL PROCEDURE EXPERIMENTAL PROCEDURE
1. Connect the circuit shown below in fig.1, note that the
following relationship must be verified in the voltage
divider transistor bias circuit, and then switch the dc power
supply on.
R1|| R2< RE
Figure 1
2. Using the VOM or DMM, measure VB, VC, VE and VCE
and then measure the quiescent collector current, then
record your results in the table No.1.
N.B: The blue colored values are the experimental values we
got through the experiment.
3. Using the value of VBE =0.7 V typically, calculate all the
expected values of the quiescent dc base voltage VB, emitter
voltage VE, collector voltage VC, and collector-emitter
voltage VCE for the given transistor voltage divider circuit
shown in figure 1, and then record these calculated values in
the table No.1 and compare your calculated results to the
measured ones.
VB =VCCR2/ (R1+R2) =15V4.7k/ (10k+4.7k) 4.8V
VE =VB-VBE=4.8-0.7=4.1V
IE= VE/ RE=4.1V/1k=4.1mA IC
VC =VCC-ICRC=15-(4.1mA1k) =10.9V
VCE =VCC-IC(RC+RE) =VC-VE=10.9-4.1=6.8V
Table No.1
Parameter Measured Value Expected Value
VB 4.83V 4.8V
VC 11.02V 10.9V
VE 4.12V 4.1V
VCEQ 6.89V 6.8V
ICQ 4.16mA 4.1mA
4.Using the equations shown below, calculate VCE(off) &
IC(sat)= and record your results in table No.2, the draw the dc
load line of the transistor voltage divider bias circuit and then
plot the Q point you got on the graph, note that the Q point
must locates at the dc load line.
VCE(off) =VCC=15V
IC(sat)= VCC/ (RC+RE)=15V/(1k+1k)=7.5mA
5. Turn off the dc power supply, and connect a 10k
potentiometer instead of R1 and R2, then turn the dc power
supply on.
6. Vary the potentiometer until you get the highest value of
VCE which represents VCE(off) and then measure the value of
IC which represents IC(off) then record your result in the
table No.2, then vary the potentiometer until you get the
highest value of IC which represents the value of IC(sat) then
measure the value of VCE which represents VCE(sat) and
record your result in the table No.2.
7. Vary the potentiometer to get five points on the
experimental dc load line and record them in the table
No.3, then plot your experimental load line using the
points you have in the table No.3.
Table No.2
Condition IC VCE IC VCE
Saturation 7.65mA 0.01V 7.5mA 0.00V
Cutoff 0.01mA 14.85V 0.00mA 15V
Table No.3
VCE IC
13.5V 0.7mA
12.4V 1.27mA
11.5V 1.73mA
4.75V 5.2mA
2.5V 6.36mA
CONCLUSION
1. In the emitter biased transistor circuit, the base of the
transistor is grounded, and the emitter voltage is negative
to forward bias the base-emitter junction.
2. In the emitter biased transistor circuit, there is two
conditions to be taken into considerations:
(a) RE>>RB
(b) VEE>>VBE
3. The value of of the transistor increases by increasing the
temperature of the transistor, which causes increasing the
value of ICQ and decreasing the value of VCEQ.
