Experiment No.

Study of Framing in Time Division Multiplexing

 256 KHz

TIMING
COUNTER AND CLOCK
SYNC. 2.048 MHz.

8 KHz
MARKER 1
F2
M F1
CH1 U
L
MARKER 2 T LINE
I CODING
P
L
CH 2 TO E
CH 32 X
E
R

FIBER OPTIC
TRANSMITTER
AND
RECEIVER SYSTEM

CH 2 D
TO E
CH 32 U
L RECEIVED DATA
T
LINE
I
DECODING
P
L
E MARKER
X
RECEIVED
E
CLOCK
R
TIMING
AND
SYNC.

BLOCK DIAGRAM FOR FRAMING IN TIME DIVISION MULTIPLEXING

 JUMPER SETTING DIAGRAM FOR EXPERIMENT NO.7

Emitter of Q2 (2N2907)
1 2 Audio 1 to Codec 1 I/P 1
Cathode of SFH 756V
3 4 Ext-Analog to Codec 1 I/P 2
Collector of Q1 (2N3904)
3
JP1
4 Cathode of SFH 450V

JP8

1 2 Audio 2 to Codec 2 I/P +5V

1
3 4 Ext-Analog to Codec 2 I/P SFH 756V Anode
2

JP2 +9V
3

JP10

1 2 Audio 1 to Audio 1

Audio 2 to Audio 1

Audio 1 to Audio 2

7 8 Audio 2 to Audio 2

JP3

2.048 MHz 1 2

256 KHz

EXT-TTL

Manchester Coded Data 7

8 Digital Buffer I/P for LED
SFH 756V

JP4

1 Manchester Coded Data Received

From Photodetector
2 Manchester Decoder Circuit I/P

3 Manchester Coded Data (Directly)

JP5
 SWITCH SETTING DIAGRAM FOR EXPERIMENT NO. 7

Switch Settings for Marker

SW1 SW2 8 7 6 5 4 3 2 1

ON ON L
1 2 3 4 5 6 7 8

1 2 3 4 5 6 7 8
SW3 ON

M L
8 7 6 5 4 3 2 1

SW4 ON

Switch Settings For Audio Channels in Time Zone

M L M L M L M L

4 3 2 1 SW6 ON SW8 ON
4 3 2 1

ON SW5 ON SW7 1 2 3 4 1 2 3 4
Audio 1 Tx setting Audio 2 Tx setting Audio 1 Rx setting Audio 2 Rx setting

Switch Settings For Manchester Coder

4 3 2 1
SW9-2 SW9-1 Data for coding Clock for coding

0 0 TDM data 2.048 MHz

ON SW9
0 1 128 KHz freqn. 256 KHz.

1 0 64 KHz. freqn. 256 KHz.

1 1 32 KHz freqn 256 KHz.

 EXPERIMENT NO. 7
NAME
Study of Framing in Time Division Multiplexing.

OBJECTIVE
The objective of this experiment is to study the technique of generation of FRAME in time
division multiplexing.

THEORY
This is an advanced experiment on Time Division Multiplexing. This experiment examines
the method of synchronous multiplexing. A FRAME plays a vital role in synchronous time
division multiplexing, which repeats itself after every T seconds. The frame has ‘n’ bits &
frame rate is 1/T frames per sec. The total data rate is n/T bits per sec. A synchronous
signal can occupy one or more bits in every frame. A signal occupying one bit per frame will
have a data rate of 1/T bits per sec. & a signal occupying ‘m’ bits per frame will have a data
rate of m/T bits per sec.

CIRCUIT DESCRIPTION:
In TDM of number of channels, data from one channel is transmitted first then data from
second channel, third channel so on till last channel occurs. After last channel again the
whole sequence is repeated from the beginning. Thus we observe a set of channels
repeating it self again and again. This set of channels form, what is called a FRAME. In our
case frame is of 32 channels.

Now the repetition rate of frame depends on channel sampling frequency. Since we are
transmitting audio signals on these channels, we should sample channel at least twice the
highest frequency component in audio signal, which is 4 KHz. This determines frame
frequency of 8 KHz. Within this period of 125 micro sec. we transmit 32 channels hence,
each channel ON period comes about 125/32 micro sec. This corresponds to the frequency
of 256 KHz. Lastly, since we transmit 8 bits of data per channel, data rate can be derived as
3.90625 / 8 = 0.48828125 & 1 / 0.48828125=2.048 MHz.

The different frequencies required for the generation of a frame are obtained from the clock
generation circuit. The synchronization between these three frequencies is achieved using a
stable crystal clock and the divider circuitry of a counter. The rising edge of frame frequency
8 KHz. is synchronized with the Marker generation block. A parallel to serial shift register
generates the marker and it always appears in the second channel of a frame. Channels 3
to 6(CH2 to CH5) in frame receive data from 4 keys (K1-K4). The digitized data from
CODEC I and from CODEC II appears in remaining time slots as determined by switch
settings.
Thus the timing and synchronization block takes care of generating a fixed frame pattern
every time.

EQUIPMENTS
Experimenter Kit 3
20 MHz dual Trace Oscilloscope
1 meter Fiber Cable
PROCEDURE
1. Set the optical digital link at 660 nm between LED SFH756V & detector SFH551V as
explained in earlier experiments.

2. The jumper and switch setting are done as shown in the jumper/switch block
diagram.
3. Observe Frame Frequency at TP3 and Slot frequency at TP2 simultaneously on the
CRO. Draw the waveforms. You should get 32 periods of slot frequency within one
period of frame frequency. Similarly observe Data Clock at TP1 and compare it with
the slot frequency at TP2.
4. Observe the multiplexed data at TP10. This clearly indicates the frame pattern as
explained above. Compare it with the frame frequency at TP3.
5. Observe the transmitted clock at TP1 and received clock at TP15. The duty cycles of
the two are not the same but the clocks are synchronized except for a slight
transmission delay in the received clock.