PCS405 VLSI DESIGN AND EMBEDDED SYSTEMS

UNIT 1 COMPONENTS OF VLSI

VLSI Very Large Scale Integration
IC Integrated Circuits
ICs/Chips Contains electronic components

Levels of Integration: (ICs are categorized according to number of gates in single package)

SSI (Small Scale Integration)
o Less than 10 gate
o Logic gate ICs
MSI (Medium Scale Integration)
o 10 to 1000 gates
o Decoders, adder and multiplexers
LSI (Large Scale Integration)
o Thousands of gates (>1000 gates and <100000 gates)
o Processors, memory chips and PLDs
VLSI (Very Large Scale Integration)
o Hundred thousands of gates (>100000 gates)
o Memory arrays and complex micro computer chips

Why we design ICs:
Electronic systems perform variety f tasks in daily life
Creates new applications
Example: ABS (Antilock Braking System), Fuel Injection, Consumer Electronics, ATM
(Automated Teller Machine), Medical electronic systems (ECG, EEG etc.,)

Key advantages of ICs over discrete components:
Size (circuits are smaller)
Speed (Communication within chip is faster)
Power consumption (logic operations consume less power due to smaller size)

System level advantages:
Smaller physical size
Lower power consumption
Reduced cost (due to reduction in number of components and mass production)

IC Manufacturing:

i) Technology

A manufacturing line can make any circuit by changing few tools called masks (for different
technology)
Patten on wafer to create wire and transistor
Series of identical hips are patterned onto the wafer
Some space reserved for test
Process is efficient because of producing many identical chips on single wafer


A Wafer divided into chips


Example: (Inverter circuit)

Transistor circuit Layout sketch (Stick diagram)

Creating layouts is a time-consuming process
Size of the layout decides the cost of the manufacturing process
Photolithography is used to transfer the layout from mask to the wafer
Fabrication steps requires high temperatures, small amounts of toxic chemicals and
extremely clean environments
After the process the wafer is divided into chips
Tiny wires or direct connections made to package pins
Package body protects the chip

ii) Economics (Moores law)

In the 1960s Gordon Moore predicted that the number of transistors that could be
manufactured on a chip would grow exponentially. His prediction, now known as Moores Law,
was remarkably prescient. Moores ultimate prediction was that transistor count would double
every two years, an estimate that has held up remarkably well
Transistor count on a chip would double every 18 months



The squares show various logic circuits, primarily central processing units (CPUs) and
digital signal processors (DSPs), while the black dots show random-access memories, primarily
dynamic RAMs or DRAMs. At any given time, memory chips have more transistors per unit area
than logic chips, but both have obeyed Moores Law.

Logic families: (Classification of ICs based on circuit technology)

Different IC fabrication technologies available (Type of transistor used is different)
Different types of circuit design for memory and Boolean functions
Different speed and power characteristics
Some logic families are
o RTL Resister Transistor Logic
o DTL Diode Transistor Logic
o TTL Transistor Transistor Logic
o ECL Emitter Coupled Logic
o MOS Metal Oxide Semiconductor (nMOS / pMOS)
o CMOS Complementary Metal Oxide Semiconductor (Both nMOS and pMOS)
NAND or NOR will be the basic gate for all logic families
Parameters / characteristics
o Fan-in (Number of inputs to gate)
o Fan-out (Number of standard loads connected)
o Power dissipation (Amount of power needed by the gate)
o Propagation delay (Average transition delay time for the signal to propagate from
input to output)
o Noise margin (Maximum noise voltage allowable)
o SPP (Speed Power Product) product of power dissipation and propagation delay


CMOS Technology:

i) CMOS circuit techniques

(a) (b) (c)
Inverter circuit

In the above circuit the speed and power consumption decreases from left to right
No steady-state power consumption for CMOS rather than bipolar and nMOS

ii) Power consumption
Huge chips due to less power consumption
More the power consumption, much of the power is dissipated as heat which limits the
number of transistors in a chip
Limiting number of transistors in a chip increases the physical size of the system
High power circuit increases power supply and cooling requirements
Low power design
o Reduce power by slowing down computations
o Reduce power by avoiding unnecessary work

iii) Design for testability
Manufacturing defects will be there with the ICS
To find out the defects, all the chips should be tested in the test sequence
Stuck at 1 and stuck at 0 are the common fault
Some fault is not covered by fault model
Testability should be improved

IC design techniques:

IC design is hard because
o Multiple levels of abstraction
o Multiple and conflicting costs (think of area, speed process of balancing
conflicting constraints)
o Short design time (especially for ASICs)

i) Hierarchical design
Hierarchical design is commonly used in programming: a procedure is written not as a
huge list of primitive statements but as calls to simpler procedures. Each procedure breaks
down the task into smaller operations until each step is refined into a procedure simple
enough to be written directly. This technique is commonly known as divide and conquer
(the procedures complexity is conquered by recursively breaking it down into manageable
pieces).

Chip designers divide and conquer by breaking the chip into a hierarchy of components. As
shown in above figure, a component consists of a body and a number of pins - this full adder has
pins a, b, cin, cout, and sum. If we consider this full adder the definition of a type, we can make
many instances of this type. Repeating commonly used components is very useful, for example, in
building an n-bit adder from n full adders. We typically give each component instance a name.
Since all components of the same type have the same pins, we refer to the pins on a particular
component by giving the component instance name and pin name together; separating the instance
and pin names by a dot is common practice. If we have two full adders, add1 and add2, we can refer
to add1.sum and add2.sum as distinct terminals (where a terminal is a component-pin pair).

ii) Design abstraction

Multiple levels of design abstraction to manage the design process and to ensure that they
meet the major design goals (logic optimization, delay etc.,)

The simplest example of a design abstraction is the logic gate. A logic gate is a
simplification of the nonlinear circuit used to build the gate: the logic gate accepts binary Boolean
values. Some design tasks, such as accurate delay calculation, are hard or impossible when cast in
terms of logic gates. However, other design tasks, such as logic optimization, are too cumbersome
to be done on the circuit. We choose the design abstraction that is best suited to the design task.

Specification
o The customer specifies what the chip should do, how fast it should run, etc. A
specification is almost always incomplete - it is a set of requirements, not a design.
Behavior
o The behavioral description is much more precise than the specification.
Specifications are usually written in English, while behavior is generally modeled as
some sort of executable program.
Register-transfer
o The systems time behavior is fully-specified - we know the allowed input and
output values on every clock cycle - but the logic isnt specified as gates. The system
is specified as Boolean functions stored in abstract memory elements. Only the
vaguest delay and area estimates can be made from the Boolean logic functions.
Logic
o The system is designed in terms of Boolean logic gates, latches, and flip-flops. We
know a lot about the structure of the system but still cannot make extremely accurate
delay calculations.
Circuit - The system is implemented as transistors.
Layout - The final design for fabrication. Parasitic resistance and capacitance can be
extracted from the layout to add to the circuit description for more accurate simulation.

A hierarchy of design abstractions for integrated circuits

iii) Computed Aided Design (CAD)

The only realistic way to design chips given performance and design time constraints is
to automate the design process, using computer-aided design (CAD) tools which automate parts
of the design process. Using computers to automate design, when done correctly, actually helps
us solve all three problems: dealing with multiple levels of abstraction is easier when you are
not absorbed in the details of a particular design step; computer programs, because they are
more methodical, can do a better job of analyzing cost trade-offs; and, when given a well-
defined task, computers can work much more quickly than humans.

Design entry
Computer-aided design tools can be categorized by the design task they handle. The
simplest of CAD tool handles design entry. Design entry tools capture a design in machine-
readable form for use by other programs, and they often allow easier modification of a
design, but they dont do any real design work.
Analysis and verification
Analysis and verification tools are more powerful. The Spice circuit simulator, for
example, solves the differential equations which govern how the circuit responds to an input
waveform over time.
Synthesis
Synthesis tools actually create a design at a lower level of abstraction from a higher level
description. Some layout synthesis programs can synthesize a layout from a circuit.
Hierarchical design and design abstractions are important of CAD tools.
Fabrication process:


Components are formed by a combination of
o Doping (adding impurities to create p+ or n+ regions
o Adding and cutting away
o Adding wire is made of polysilicon or metal
Figure of merit of the process is the size or channel length
o 0.5m CMOS process means channel length is 0.5m or

Fabrication steps:
Feature are patterned on the wafer by a photolithographic process
The wafer is covered with photoresist (light or photo sensitive material)
And exposed to light (UV) with proper pattern (mask)
The transistors are fabricated within regions called tubs or wells
N-type transistor is build in a p
Tub formation
o Start with p-doped wafer and add n
o Start with n-doped wafer and add p
o Start with undoped wafer or substrate and add both n and p tubs or wells
Twin tub is the most commonly used process because of its better electrical characteristics

Cross section of IC
Components are formed by a combination of
Doping (adding impurities to create p+ or n+ regions
Adding and cutting away insulating glass (SiO
2
) on top of the substrate
Adding wire is made of polysilicon or metal
Figure of merit of the process is the size or channel length
0.5m CMOS process means channel length is 0.5m or =0.25 m.
patterned on the wafer by a photolithographic process
The wafer is covered with photoresist (light or photo sensitive material)
And exposed to light (UV) with proper pattern (mask)
The transistors are fabricated within regions called tubs or wells
transistor is build in a p-tub and N-type transistor is build in a n-tub
doped wafer and add n-tubs
doped wafer and add p-tubs
Start with undoped wafer or substrate and add both n and p tubs or wells
most commonly used process because of its better electrical characteristics


) on top of the substrate
=0.25 m.

Start with undoped wafer or substrate and add both n and p tubs or wells
most commonly used process because of its better electrical characteristics



Steps in processing a wafer

Put tubs into wafer at appropriate places
Form an oxide covering wafer
o Think oxide over entire wafer
o Remove field oxide over transistor area and thin oxide is grown
Polysilicon wiring are laid
Diffusion wires laid to create self-aligned transistors (source / drain regions)
Oxide layer is deposited to insulate poly and metal wires
Holds made on field oxide to take metal connections (Aluminum is used)
Add metal 2 and metal 3 by additional oxidation, cut and deposition sequence
Finally covered with passivation layer of SiO
2
to protect the chip from chemical
contamination

Delay:

Majority of chip designs are limited more by speed than by area


Output voltage (V
out
) is pulled down (due to input is equal to 1)
V
out
is pulled up when input is 0
When V
out
is equal to 0, p type transistor is off (out of circuit)
When V
out
is equal to 1, n type transistor is off (out of circuit)

Transistor starts in saturation region, then moves to linear region
The logic 0 to logic 1 transistion will be or 1/3 of the speed of the logic 1 to logic 0
transition ( if size of pull-up and pull-down transistors are equal)
To make both transition time equal, the pull up transistor must be two or three times wider
than pull down transistor
Due to body effect, as source voltage increases threshold voltage increases

This effect can be modeled by a capacitor between source to the substrate ground and to
eliminate the body effects drive the capacitor to 0V as soon as possible
If we connect the early arriving signals to the transistors nearest to the power supply and late
arriving signals to the gate output, the early arriving signal will discharge the body effect
capacitance


Power consumption:

More the speed the power consumption increases
The power consumption comes at the cost of heat dissipated out of chip
Static CMOS gates are efficient in power consumption

No steady state power consumption in CMOS
Because after the capacitor is fully charged or discharged only one transistor (either pull up
or pull down) is on
But there is a slight leakage current (10
-12
A) through channel of an off transistor
Leakage current and power is important in very lower power devices

The current through the capacitor and the voltage across it are
L P
C R
t
P
SS DD
CL
e
R
V V
t i

= ) (
] 1 )[ ( ) (
L P
C R
t
SS DD CL
e V V t V

=
The energy required to charge the capacitor is


dt t V t i E
CL CL C

= ) ( ) (
2
) (
2
1
SS DD L
V V C =
The above equation only depends on C
L
and not on R
P
. The current through and voltage
across the pull up resistor are
) ( ) ( t i t i
CL P
=
L P
C R
t
P
Ve t V

= ) (
The energy required to charge the capacitor is


dt t V t i E
p p R

= ) ( ) (
2
) (
2
1
SS DD L
V V C =
Once again the value of Rp (pull-up resistance) drops from energy formula
The energy consumed in discharging the capacitor can be calculated in same way and is

2
) (
2
1
SS DD L
V V C =
The total charging and discharging cycle consumes
2
) (
SS DD L
V V C
Therefore, the power consumed by the circuit depends on frequency of output changes
The clock frequency is f=1/t. so the total power consumption is
2
) (
SS DD L
V V fC
Therefore, power consumption is depends on clock frequency because must power is
consumed while the outputs are changing
Speed power product (power-delay product)
o Ignore leakage current and consider speed and power for single inverter transisiton
o SP/SPP = 1/f *P = CV
2

o This result suggests an important method for power consumption reduction is by
reducing the power supply voltage
Voltage scaling
o The power consumption is reduced by reducing the power supply voltage and adding
parallel logic gates
o In this method, the power consumption shrinks quickly than the circuit delay so
voltage scaling is a powerful technique

Yield:

chips of number Total
wafer on chips good of Number
Y =
Depends on
o Technology
o Chip area
o Layout
Seeds model
o
AD
e Y

= Where A Chip area, D Defect density
o This model is used for large chips and yields less than 30%
Murphys model
o
2
1
(

=

AD
e
Y
AD

o This model is used for small chips and yields greater than 30%
Recent generalized model
o
i
C
N
i j
ij i j
P D A Y

=

|
|

\
|
+ =
1
1
Where i i
th
type of defect
j j
th
module
P
ij
Probability of i
th
defect to cause a fault in j
th
area
C
i
Constant relating to the density of i
th
type of defect
Yield decreases dramatically as the area of chip is increased

Yield enhancements
Space out wires to reduce risk of short circuits and to reduce capacitance
At least two vias for every connection to avoid open circuits
Use wider-than-min transistors
Avoid non rectangular shapes ( angle, circles)