20 W Benchmark Converters for Simulation and

Control Comparisons
Topology
Input voltage
Output voltage
Output power
Richard Muyshondt
University of Illinois
Department of Electrical
& Computer Engineering
1406 W. Green St.
Urbana, Illinois 61801
USA
Phone: +I-217-333-1742
Fax: +1-217-333-1162
E-mail: muyshond 8 uiuc.edu
Non-isolated Buck Converter
12 V nominal; an unregulated
source with 20% ripple at 100 Hz
or 120 Ht .
5 V nominal, with ripple and
regulation to maintain output inside
a +. 1 % window.
20 W nominal, with correct
Absfracf - Although various control techniques have
been proposed for dc-dc converters, direct
comparisons between these techniques have been
diffcult. In the past, special test cases have been
used t o emphasize the strengths of a new control
technique and show the weaknesses of conventional
approaches. It can be debated whether these test
cases are realistic. This paper proposes a suite of
benchmark converters that are examples of good
conventional designs. The benchmark designs are
based on the extensively studied methods of
averaging and linearization. The benchmarks are
proposed as reference circuits for comparisons of
simulators and control methods.
- -
Switching freq.
I. Introduction
operation over a 0 to 20 W range.
100 lcHz and 200 kHz designs are
Various control techniques have been proposed for
dc-dc converters. Each has its strengths and weaknesses,
but direct comparisons havebeen difficult. In much of the
literature, special test cases are used to emphasize
weaknesses of conventional approaches whilehighlighting
new capabilities. There is a need for benchmark
converters that can be accepted as examples of good
conventional designs. These can then serve as a basis for
comparison withalternative control methods.
This paper proposes a suite of non-isolated dc-dc
converter benchmarks for compqison purposes. 1 The
designs are complete enough to support both simulation
and experimental studies. The conventional design
methods of averaging and linearization will be used to
model the converters and design the feedback network.
Section I1 proposes benchmark specifications for buck,
boost. and buck-boost topologies. In Section 111,
conventional designs of these three topologies are
presented. The conventional buck design will be
Regulation
. I
0-7803-4856-7-8/98/$10.00 0 1998 IEEE *
.
compensated feedback.
Integral gain is used to ensure ideal
Philip T. Krein
University of Illinois
Department of Electrical
& Computer Engineering
1406 W. Green St.
Urbana, Illinois 61801
USA
Phone: +I-217-333-1742
Fax: +I-217-333-1 162
E-mail: krein@ece.uiuc.edu
described in somedetail whiletheboost and buck-boost
designs will be summarized. Detailed simulation studies
of all of theconverter designs will bepresented in Section
N. and a discussion of experimental results will be
presented in Section V. Concluding remarks are given in
Section VII.
11. Benchmark Specifications
A benchmark converter for simulation and control
should be realistic. easy to reproduce and safe. Most
important, it should represent consensus about thefactors
that constitute "good conventional" design. I n an attempt
to direct the benchmarks toward consensus, Table 1 ,
Table 2. and Table 3 show the specifications for three
converter topologies.
I presented.
Control I Voltage mode control with
I [ steady-state output. I
20 1
Table 2 - Specifications for Boost Converter
Control
I output-inside a +1% window.
I 20 W nominal, with correct
compensated feedback and
duty ratio limit.
I Output power I operation over a o to 20 w I
r
Topology
Input voltage
Output voltage
Output power
range.
100 kHz and 200 kHz
designs are presented.
Voltage modec.ontrol with
Switching freq.
Non-isolated Buck-Boost
Converter
48 V nominal; 40 V to 56 V
possible voltage range
12 V nominal, with ripple and
regulation to maintain output
inside a *I % window.
20 W nominal, with correct
operation over a 0 to 20 W
Switching freq.
Integral gain is used to ensure
ideal steady-state output.
Regulation
range.
100 Wz and 200 kHz designs
Voltage mode control with
are presented.
Control compensated feedback and
duty ratio limit.
Integral gain is used to ensure
ideal steady-state output.
Regulation
III. Conventional Benchmark Design
Conventional design of a converter is separated into
two parts - the power stage design and the controller
design. Since the design approach for the different
converter topologies is fundamentally similar. this section
will show only the details of the buck converter design.
Key differences between the buck and the boost and buck-
boost topologies will then be explored, and modifications
of the design approach for the boost and buck-boos!
converters will bediscussed.
A. Buck Power Stage Design
Conventional average analysis in continuous conduction
mode[ 1-51 yields thedc transfer function
?he power soge model is shown in Figure 1.
V,,, =D(V,, - i LRds i- Vd) - Vd
(1)
whereD is the duty ratio of thetransistor and other values
are is shown in Figure 1. For an input range of 12 V f
10%. theduty ratio will fall between 0.39 and 0.57.
The inductor is selected to maintain continuous
conduction modedown to 20% of rated load in the 100
kHz switching case, and down to 10% rated load in the
200 kHz case. The objective is an inductor small enough
to support fast dynamic control, but large enough to
prevent excessive flux variation and magnetic loss. The
proposed selection is consistent with typical practices
whenferrite materials are in use. Once again, the analysis
is conventional, and an inductor equal to 46 pH will work
at either switching frequency. A 50 pH part will be used
for availability.
Figure 1 - Simple Buck Converter Representation
The capacitor handles the main part of theripple, and
must keep ripple l ow enough to meet thespecifications.
Generalizing from[3, p. 1071. the output voltage ripple
with low ESR is
/.\ .n
where T is the switching period. For the 100 kHz
switching case, AiL is 1.6A. Taken the ESR from a loss
tangent on the order of 25%. plus about l or n for the
wireresistance, a capacitance of 35 pF should meet the
requirements at both frequencies. TO keep FSR values
low and avoid self-resonance issues, two parallel 22 pF
tantalumcapacitors will be used, with a small 0.1 pF
ceramic added as well.
The benchmark switching components are a 300
MOSFET (such as MTpI2PIO) and a IO A Schortky
diode (such as MBR1045).
202
B. Buck Feedback Design -- Small-Sigrial Transfer
Furiction
me feedback loop design follows conventional
practice as in [6] and [7], and is summarized here. The
converter model of Figure 1 is averaged and linearized
around an arbitrary operating point (in continuous mode)
to yield the results shown on Table 4.
Table 4 - Control-to-Output, Input-to-Output, and
Output Voltage-to-Current Transfer Functions for
Linearized Buck Converter
+~ ( DR, - R, . R ~ ) + R,
D
R
R + R r
R, =-
For comparison, it is useful to consider theformof the
control-to-output transfer function, G(s), when theRc, &,
and Vd values are small. This gives
(3)
VC Vin
L
R
G( s ) =- =
s2LC+s-+l
Although small-signal results apply only at a specific
operating point, the arbitrary forms in the table support
inferences about a widedesign space. Wemight refer to
the application of Table 4 over thefull operating range as
a quasi-small-signal approach. This reflects the
conventional practice in dc-dc conversion. Designs based
on this method should be robust enough to handle all
allowed conditions. The justification for extension to no-
load and discontinuous-mode cases isgiven below.
The response of (3) is shown in Figure2 for values L
=50 vH, R =1.25 Q, C =44.1 F, and Vin =12 V. The
second traces show the effect of &ht loading (i.e., R =50
Q). The transfer function has two poles. The load, R,
affects the real values of the poles. and the system
beconies moreoscillatory as theload becomes lighter. In
thelight load limit, this continuous-mode model yields an
LC oscillator damped only by the ESR and other stray
elements. The effect of discontinuous mode can be
inferred fromrecent results 181 that reveal a split in poles
when discontinuous modeis entered. Onepoleremains
fixed, whilethesecond moves higher in frequency. This
implies that poles inferred by taking thelimit R w + oo in
(3) will give a conservative estimate of stability and
frequency response issues for control design. The no-load
circuit, therefore, serves as a worst case. If a stable
controller can be designed for it, theconverter of Figure 1
should be stable over theentire load rangeeven though
discontinuous modewill occur at light loading.
I 0' I0' I 0' to'
F n g Ur r Y ( d S d
Figure 2 - Frequency Response of Buck Converter
Control-to-Output Transfer Function G(s) under Normal
Load (solid line) and Light Load (dashed line)
The control-to-output function should also include the
PWM sawtooth amplitude, sincethis can affect duty ratio.
Given that a nominal amplitude Vramp corresponds to
D=l, G(s) should benormalized, and written as
Vin
(4)
C. Buck Feedback Design -- Feedback Loop
The light-load transfer function reflects oscillation.
since there is positive gain when the phase changes to
-1800. The basic objective of the feedback loop is to
enforce a gain below 0 dB when thephasereaches -1800.
203
This should be done at thehighest possible frequency and
with significant extra margin for headroom. In the design
here, theproposed objective is to maintain positive gain
up to 10% of the switching frequency, and to provide
phase margin of at least 600 at this crossover frequency.
Based on suggested compcnsation networks in [6],[7].
the feedback circuit in Figure 3 is proposed. This in effect
combines lead cornpensation with proportional-integral
feedback control but performs this function with a single
amplifier. The circuit transfer function H(s) adds 3 poles
and 2 zeroes to the systemopen-loop transfer function
G(s)H(s). A Bode plot for H(s) is provided in Figure 3.
Analytical expressions for the various values are given in
[6), and summdzed in Table 2. The resonant frequency
of the LC pair is 3.56 kHz, and the nominal dc gain of the
converter is Go =lU5. At 10 kHz, the gain of G(s) has a
value of 0.3, or about -10 dB. To produce a pain of 1 at
10 kHz, the gain of H(s) should beU0.3 at this frequency.
RL (W) I 10
C (uF) 1 44.1
to' IO' to' IO* I0'
F i a ~ o r y ( r adhc l
Figure 3 -Feedback Circuit and Its Ideal Frequency
Response, H(s)
A. , - -
Let the corner freguencies fi and fz be set to match the
LC resonance frequency. This provides cancellation of
10
44.1
the LC polepair. The AVI value is found by extrapolating
a gain of 10/0.3 at 10 kHt to the gain value at ft and f2
based on a slope of 20 dBldecade. Its valueis 1.2, The
values of f3and f4are chosen so that the zeros at fi and fi
will be able to compensate for the two poles of the
converter. The values selected for 100 kHz switching are
f3=200 Wiz and f4=SO kHz. The value of A v~ is found
along the lines of Avl. and has a value of 60.
Table 6 summarizes component values and margin
resulu for both I00 kHz and 200 kHz switching. Standard
component values are given, The open-loop frequency
response of theconverter withand without thefeedback
circuit for the 100 kHz case is shown in Figure 4. The
complete circuit for 100 Wt switching with added gate
drive is shown in Figure 5. Note Figure 5 contains a
6.3V zener diode at the output. This diode is not used in
thesimulations, but serves to clamp the output voltage in
the hardwareimplementation of theconverter. The zener
diodes across CI help avoid overshoot caused by the
integrator.
Table 6 - Component Values for Design Results and
Feedback Circuit of Buck Converter at Switching
R (a)
& (mn)
Frequencies of 100 kHz and 200 kHz
1 f =100 I f =200 1
1.25 1.25
300 300
v d (v)
Vramp (VI
0.7 0.7
5 5
Rp (n)
Gain Margin (dB)
Phase Margin (degrees)
lo0 100
66.0 31.4
67.5 69.1
CrossoverFrequency I ,, I
(kHz)
Audio Susceptibility(dB)
at 12OHz
Full Load Efficiency
I
-98.9 -93.,
84.5% 85.5%
204
16 14 lo'
-Ww
Figure 4 - Open loop Frequency Response of the
Converter, G(s) (dashed line), and Converter with
Feedback Circuit, G(s)H(s) (solid line)
lOOkHz 1
Figure 5 - Complete Buck Converter Circuit for I 00
kHz Switching
D. Boost arid Buck-Boost Coriventiorwl Berichmark
Designs
As discussed previously, the boost and buck-boost
design approaches are similar to thebuck topology design
approach. However, a few notable differences exist. The
first difference deals with the LC component selection
process for the power stage. In both cases. theselection
criteria for the inductance assured that theRHP zero of
thecontrol to output transfer functions of theconverters
(discussed below) was set to a high frequency. For both
topologies, an inductance value that would have a 25%
flux variation at 20 W was chosen. The capacitance
values were chosen to rneet ripple requirements. Extra
emphasis was given to ESR values for these topologies
since they typically suffer fromESR voltage jumps at the
output. In both cases, the ESR voltage jump criteria
determined thevalueof thecapacitance to be used in the
final design. Table 8 and Table 9 contain thefinal L and
C values used in thepower stage.
As suggested above, another difference in thedesign
process lay in thefact that both theboost and buck-boost
have a right half plane (RHP) zero in their control to
output transfer functions (see Table 7). As in thecase of a
left half plane (LHP) zero, the RHP zero increases the
gain as thefrequency is increased. However, unlikethe
LHP zero, the phase of theRHP zero drops by 90". In
both cases, the RHP zero is directly proportional to the
duty ratio and inversely proportional to theinductor value.
Care was taken in thepower stage component selection
process to assure that the RHP zero was located at higher
frequencies to nunimize its effects at l ow frequencies (i.e.,
the RHP zero of the boost is at 11.5 kHz and theRHP
zero of the buck boost is at 40 kHz).
A final difference in thedesigns is an enforcement of
a duty ratio linut for theboost and buck-boost topologies.
Since theenergy transfer is not direct for both topologies,
a minimal timemust be madeavailable for theinductor to
transfer its energy to the load. For example, a voltage
below the nominal value would cause the controller to
force thetransistor to its 'on' state whereit would remain
until the output voltage exceeds its nominal value.
However, in this state, theoutput voltage will decrease
since theinductor cannot transfer its energy to the output.
Thus, thetransistor would be in its 'on' state indefinitely.
This is thelarge signal effect that gives rise to theW
zero. Enforcement of a duty ratio limit avoids this large
signal instability.
Table 7 - Control to Output Transfer Functions for
B(
Converter
Boost
Buck-
Boost
;t and Buck-Boost Converters
G(s)
f
205
Table 8 - Component Values at Switching Frequencies
Gain Margin (dB)
Phase Margin (degrees)
Crossover Frequency
(kHZ)
Audio Susceptibility (dB)
at 120Hz
Full-Load Efficiency
of 100 kHz and 200 kHz for Boost Converter
4.1 2.7
54.2 50.5
3. I 4.5
-2 I .2 -15.5
81% 79%
Figure 6 - Complete Boost Converter Circuit for
1OOkHzSwitching
and zeros for thecompensation network were chosen in a
similar manner as for thebuck converter. The component
values for the compensation network as well is the gain
and phase margins for the open loop transfer function,
G(s)H(s), are given in Table 8 and Table 9. Figure 6 and
Figure 7 show the complete circuit representations for the
boost and buck-boost benchmark converters. Note that as
in the buck converter, zener diodes have been added at the
output of theconverter. In this case, 15V zeners were
used for inverter clamping. Again, the zeners were not
used in the simulations but are added since they were used
to improve the integrator response in the hardware
implementation of theconverters.
Table 9- Component Values at Switching Frequencies
of 100 kHz and 200 kHz Buck-Boost Converter
I f=100 I f =200
I 72
Audio buscepta
at 120t.- I I
~ Full-Load Efficiency 1 88% I 87%
The compensation network shown on Figure 3 was
also used for theboost and buck-boost designs. The poles
206
I
Figure 7 -Complete Buck-Boost Converter Circuit for
100 kHz Switching
IV. Simulations Results
Figure 8 shows time response when small signal
perturbations are imposed on thebuck converter, starting
froma 19.8 W load and 12 V input. In the figure, the
disturbance at 0.6 ms is a 1% increase in the load (i.e.,
19.8W to 20W). The disturbance at 0.85 ms is a 1%
decrease in theinput voltage. Since there is integral gain,
the figure shows a return to exactly 5 V output after
sufficient time. The dynamic specifications are met under
these disturbances.
Figure 9 demonstrates several large signal
disturbance cases, each well outside thedomain of small
signal analysis. The converter is allowed to reach steady
state with a 2.5 (10 W) load. At time t =0.6 ms, the
output is increased to 20 W. At time t =1.2 ms, theline
input is decreased to 9.6 V. The controller is stable as it
responds to each of these disturbances, as suggested in
Figure 4. Even open-circuit simulation cases show
stable operation in the face of oscillatory open-loop
converter behavior. The converter also recovers from
temporary short-circuit and loss of line conditions
(simulations not shown).
Notice that there is no separate ripple filter i n the
control loop. The bandwidth limitation is sufficient to
avoid aliasing effects of ripple. The results in Figure 9
show the robustness of the quasi-small-signal methods,
or at least reflect a certain low sensitivity of the buck
converter. A voltage-mode control offers a good
reference deign.
. . . .
,,W" ................................................... -.--.-.- ............ ..-.. ...................
.yu 0 - ..o- ..A 0 - ,.,U
8-
.","I.,,
Figure 8 - 100 kHz Closed-Loop Buck Converter
Response to a Series Small-Signal Transients
,.w ................................................................................................
. .
i 1- s ; m Y.c)~.c . nv 1. *.w I. C~IIC- a.". '
. . . : .
Figure 8 - 100 kHz Closed-Loop Buck Converter
Response to a Series Small-Signal Transients
,.w ................................................................................................
. .
: tm s . ,er Y.c)~.c . nv 1. *.w I. C~IIC- a.". '
'"1 v
, ......................... ..........._.............-............._..............r.....I ......
0 - a * *.U ,b. 1.- I W l b . 1.
7.-
. w.3, I,
Figure 9 - LOO k Hz Closed-loop Buck Converter
Response to a Series Large-Signal Transients
Simulations to test the performance of theboost and
buck-boost were also performed. Figure 10 shows the
performance of fie boost converter under small signal
perturbations. At 2.5 ms theload isincreased from19.8
W to 20 W. At 4 ms, the input source is decreased by
1 o/c from 3.6 V to 3.564V. Again. i n all cases, theoutput
voltagereturns to thedesired voltage of 12 V.
,,.w .............................. .-.._.-.- ......... ......-......... ............................... I
8 . b 1.- ..L I . L 1.- ..,I
*-
."I-,
Figure 10 - 100 kHz Closed-Loop Boost Converter
Response to a Series Small-Signal Transients
207
Figure 11 shows how the boost converter performs
under various large signal disturbances. Initially. the
input source is set to 3.6 V and theload is 10W. At 2 ms,
the load increases 20 W. At 4.0 ms. the input source
voltage decreases to 3.0 V. From Figure 1 1, one can see
that theconverter always recovers from each of the large
signal disturbances after some time. Extreme load and
input source cases were also simulated but are not
included in this paper. For temporary short-circuit. open-
circuit, and loss of linesimulation cases as well as start-
up, the boost converter recovers from the extreme
perturbations, and its output voltagereturns to 12 V each
time.
" ................ ....................................................................................
. . * .
.... : I r ' . N. Y1, - ". . . : . I.* .,.. l .CWkr ..6...u" . . : . . . . :
i : / : : / :
m.w...* ............ .._ ............................................................................
1.- I L . 4 . L . I - .s" .b. a -
.-
. ",..I,
Figure 1 1 - 100 lcHz Closed-Loop Boost Converter
Response to a Series Large-Signal Transients
The buck-boost converter transient response was
similar to the boost response. Figure 12 shows the
performance of the buck-boost converter under small
signal perturbations. At 1.35 ms theload changes 19.8 W
to 20 W. At 2 ms, the line voltage is decreased from 48 V
to 47.52 V. As in the boost converter, theoutput voltage
returns to the desired voltageof 12 V for all small signal
disturbances.
i
".*,.I ...,.- ...... ."T ...... ~ .... ..... '....., .. ~-.~..~ ..,.. t":..:.T"2-_ ..... ...................
. . . . . . . . . 1' . ....
. I* I- I-.- @.-. ". a. .T.S* .
. / . .
. .
i . , .
,,.-!...: . :
Il. u. i. . i .i L ; i i : &.........I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: .
.......... .......... .......... ........... ........... .......... .......... . .
I.)- 8 . m 1 . m 1.- 18- I Y I.- 1.011.ur
..-
. - M I
Figure 12 - 100 kHz Closid-Loop Buck-Boost
Converter Response to a Series Small-Signal Transients
Figure I3 shows how the buck-boost converter
performs under large signal disturbances. Initially, the
buck-boost converter's input source is set to 48 V, and it
has a IO W load. At 1.0ms, the load increases to 20 W.
At 2.5 ms. theinput source voltage decreases to 40 V.
One can see from Figure 13 that the converter always
recovers fromeach of the input source variations and that
theoutput voltage returns to its nominal value. The buck-
boost benchmark converter was also simulated with short
circuit, open circuit, and loss of line conditions (not
shown). In each case, theoutput voltage recovered from
the extreme disturbances when nominal conditions were
restored.
...............................................................................................
, .
: :m 8- w- +* I.--& .& ,. m I& I..... :
. .
. .
,,.,+ . . . . . . . . . . . . : . . . . : . . . . . . . .
. .
. .
I . I .
. . . . . . : . . . . . . : . . . . i . . . . . . . . . . . .
U,...-: ........... i ........... ; ..........-.... ...... i ........... ; ........... i..-.-- ..... i ..........
..- t r 2.Q. 2.- la" I - .- ,I
I-
. +r.Wnl
Figure 13 - 100 kHz Closed-Loop Buck-Boost
Converter Response to a Series Large-Signal Transients
Appendix A at the end of this paper contains the
PSpice netlists for the 100 kHz converters. The netlists
can also be downloaded from
httpy/energy.ece.uiuc.edu/-benchmarks/index.html.
V. Experimental Results
The 100 kHz converters shown in Figure 5, Figure 6.
and Figure 7 were implemented in hardware. The
component values of the benchmarks were matched as
closeas possible. The MTPl2PlO were used for the p
channel MOSFETs in the buck and buck boost, and the
MTP50N06 was use for the nthannel MOSFET in the
boost. All npn BJTs were implemented with 2N2222A
transistors, and all pnp BJTs were implemented with
2N2907A transistors. Theoperational amplifiers used in
the hardware were MC34074. The diodes were
implemented with MBR1045 in the buck and boost while
the buck boost used an MUR830. 1N4730 zener diodes
were used to limit the duty ratios in the boost and buck
boost. Finally, a MC34152 gate driver was used to drive
the MTPSONO6 in the boost converter.
208
The hardware results presented here are for large
signal disturbances and are shown in Figure 14 to Figure
19. The hardware results validate performance of the
converter benchmarks in this paper.
Figure 14 and Figure 15 show the response of the
buck converter hardware to a 1OW to 20W load change
and a 12V to 9.6V input source change, respectively.
Figure 16 and Figure 17 show theresponse of theboost
converter hardware to a 9W to 20W load change and a
3.6V to 2.9V input source change, respectively. Figure18
and Figure 19 show the response of the buck-boost
converter hardware to a 9 W to 20W load change anda 48
to 40V input source change, respectively.
100 kHz Busk Raspor. lo a I OW lo 20W Load Change
I 1
0.6 0 7 0.8 0.0 1 1.1 1 2
lime (ms)
Figure 14 -100 kHz Buck Hardware Implementation
Response to a 10%' to 20W Load Change
s.11
i
0.2 0.3 0.4 0.5 0.6 0.7 0.8
r ma (ma)
Figure 15 -100 kHz Buck Hardware Implementation
Response to a 12V to 9. 6~ Input Source Change
2 4 4 10 12 14 16 18 M
Tma (mi)
Figure 16 - 100 kHz Boost Hardware Implementation
Response to a 9W to 20W Load Change
lalknz Bmrl R.rpos0 lo a 3 6V lo 2 9V k4 Soma C b n w
12
-
11.5
0
r
>
3
-D 11
d
10 5
1 0 1 ' . . * ' . ' . ' I
Figure 17 -100 W z Boost Hardware Implementation
Response to a 3.6V to 3. 0~ Input Source Change
2 4 6 8 10 12 14 16 18 20
Tm. (ms)
100 kH2 Buck B o al R.s-a 10 a 9W Io MW Load CMnw
( OS t
101 J
Figure 18 - 100 kHz Buck-Boost Hardware
Implementation Response to a 9W to 20W Load Change
1 1 2 1.4 1.6 1 .8 2
rm. (ms)
209
1- . I
0.2 0.4 0.6 0.8 I 1.2 1.4
rm (rm)
Figure 19 - IO0 kHt Buck-Boost Hardware
Implementation Response to a 48V to 40v Input Source
Change
VI Control Comparisons
The above benchmarks are proposed as reference
circuits for comparisons of simulators and control
methods. As an example of a control comparison,
Figure 20 and Figure 21 show the transient performance
of a boundary controlled boost converter that uses
integral feedback [9]. The power stage of the converter
in these simulations is the same as thepower stage for
the 100 kHz boost benchmark. The control stage uses a
boundary slope of ki d . 8 . an integral gain of 25000.
and a switching frequency limit of 100kHt.
Figure 20 shows the small signal performance of the
boundary controlled boost converter. First, the boost
converter is allowed to reach steady state under nominal
operating conditions. At t =1.2111s. theload is increased
1% to 20W. At t e 4ms. the input source of the
converter is decreased by 1% to 3.564V. In both cases
the converter is not significantly affected by the small
signal disturbance. FromFigure 10, however, it can be
Seen that the boost benchmark is slightly affected by the
small signal disturbances.
I
? I e S 8 7
1- I-I
Figure 20 - Integral Feedback Boundary Controlled
Boost Converter Response to Small Signal Transients
Used for Comparison with the Benchmark in Figure 10
Figure21 shows the large signal performance of the
boundary controlled boost converter. The boost
converter is allowed to reach steady state with a 1OW
load and a 3.6V input source. At t =1.2ms, the load is
increased to 20W. At t =4ms. the input source of the
converter is decreased to 3.0V. The converter recovers
fromboth of the large signal disturbances. Figure 21
and Figure 1 1 (boost benchmark) are plotted on similar
scales for easy comparison. Figure 21 shows that the
boundary controlled converter exhibits an over-damped
response, smaller transient peaks, and faster recovery
speed than the benchmark converter. The faster
response of the boundary controlled converter is
partially explained by the inclusion of feed-forward in
the boundary control algorithm. The faster response is
particularly evident in the response of the boundary
controller to the input source pertutbation.
I I
w I
Figure 21 - Integral Feedback Boundary Controlled
Boost Converter Response to Large Signal Transients
Used for Comparison with the Benchmark in Figure 11
2 3 4 c
T- (n*)
210
VII. Conclusions
A possible suite of benchmark designs for dc-dc
converters was presented. All designs used conventional
voltage-mode control and werestable even into an open
circuit. The converters handle small transients while
maintaining tight performance, and recover fromextreme
cases such as loss of line or load. Experimental validation
of theconverters was performed and confirmed that the
converters are stable.
VIII. Acknowledgements
This paper is based in part onthePh.D. thesis of R.
Muyshondt, submitted to the University of Illinois.
Primary support was provided under contract DOE SNL
AS 0627 by Sandia National Laboratory, Albuquerque,
NM. P. Krein is grateful for support as a Fulbright
Scholar through thejoint U.S.-United KingdomFulbright
Commission.
IX. References
[ I ] R. D. Middlebrook andS. Cuk, A general unified
approach to modeling switching converter power
stages, IEEE Trans. Aerospace Electronic
Systems, vol. AES-9. no.3, pp, 376-385. May 1973.
12) G.W. Wester, R.. D. Middlebrook, Low frequency
characterization of dc-dc converters, IEEE Trans.
Power Electronics, vol. 3, no. 4, pp. 489498.
October 1988
[3) P. T. Krein, Elements of Power Electronics, New
York: Oxford University Press, 1998.
[4] R. D. Middlebrook. Small-signal modeling of pulse-
width modulated switched-mode power converters.
Proc. IEEE, Vol. 76, No. 4. April 1988.
frequency response theory for piecewiseconstant
two-switched-network dc-to-dc converter systems,
Proc. IEEE, 1986, pp. 186-200.
[6] H. D. Venable, S. R. Foster, Practical techniques for
analyzing, measuring, and stabilizing feedback
control loops in switching regulators and
converters, Proc. Powercon 7, pp.
[7] R.B. Ridley, B.H. Cho. F. C. Lee, Analysis and
interpretation of loop gains of multilooptontrolled
switching regulators. IEEE Power Electronics
Specialists Conference Record, 1976. pp. 18-34.
[8] J. Sun, D. Mitchell, M. Gruel, P. Krein, R. Bass,
Modeling of pwmconverters in discontinuous
mode - a reexamination, IEEE Power Electronics
Specialists Conference Record, 1998, pp.
[ 5] B. Y Lau. R. D. Middlebrook. Small-signal
[9] M. Greuel, R. A. hluyshondt, P. T. Krein. Design
approaches to Boundary Controllers, IEEE Power
Electronics Specialists Conference Record, 1997.
pp. 672-678.
Appendix A
This appendix contains the netlist files for the three
100 kHz benchmark topologies under nominal input and
loading conditions. The netlist were simulated with
MicroSimPSpiceA/D @ version 8.0. Text files of these
netlists can be downloaded from
http://energy.ece.uiuc.edu/-benchmarks/index.html.
A. Buck Converter Netlist
R-RL 2 1 .01
E-HS2-LIMIT4 8 0 VALUE (LIMIT(V(7).0,5))
R-HS2-Ro 8 14 .01
E-HS2-EI 70 15 16 IO00
R-R2 3 14 12k
D-D2 0 4 Dbreak
.MODEL Dbreak D Is= 1 On Cjo=. I pF Rs=.Ol
C-Cout 17 5 44.luF IC=4.95
V-Vd 4 2.7
c-c3 6 16 4700pFIC=O
R-Rc 50 .02
L-L 1 I 17 50uH IC=3.9
R-R 1 18 16 10k
R-R3 186 200
V-Vin 200 12v
R-R27 170 1.25
s-s2 202 I 1 os2
RS-S2 1 1 0 IG
.MODEL S2 VSWITCH Roff=lOe7 Ron=.3 Voff=O
+Von=.5
R-Rr 210 I k
V-Vr 21ODCOACO
+PULSE 0 5 0 9. 9~ .05u .05u I OU
E-HS4-LIMIT4 100 VALUE (LIMlT(V(9),0,5))
R-HS4-Ro 10 1 I .01
E-HS4-EI 9 0 14 21 loo0
R-Rcont 140 lOOk
V-Vref 15 0 2.5
R-R36 190 Ik
R,R35 17 19 I k
E-HSS-LIMIT4 13 0 VALUE (LIMIT(V( 12).0.5))
R-HSS-Ro 13 18.O1
E-HS5-E I 120 19 18 IO00
c-c2 16 14 27pF IC=.42
c-c 1 16 3 3900pF IC=.42
21 1
B. Boost Converter Netlist
R,RL 14 1 .01
D-D6 15 2 Dbreak
.MODEL Dbreak D Is=lOn Cjo=.lpF Rs=.Ol
V-Vd 2 160.7V
s,s7 I50 130S7
RS37 13 0 1G
.MODEL S7 VS WITCH Roff=1 Oe7 Ron=.028 Voff=O
Von=.5
R,R32 160 7.2
R-Rc 30 .012
R- k 170 lk
V-Vr 17 0 DC 0 AC 0
+PULSE 0 4 0 9. 9~ .05u . O h 1Ou
c,c3 4 1832n IC=O
R-R4 I 200 lk
R-R40 1620 3k
E-HS12-LIMIT4 7 0 VALUE (LIMIT(V(6).0,5))
R-HS12,Ro 721 .01
E-HS12-El 602021 lo00
R-R 1 21 18 10k
R,R3 421 100
V-Vref 19 0 3V
D-DlO 0 22 DbreakZ
.MODEL DbreakZ D Is=lOn Cjo=. 1pF Rs=.Ol Bv=3.9
R-Rcont 220 l00k
E-HSll-LIMIT4 9 0 VALUE (LIMIT(V(l),OS))
R-HS11-Ro 9 10 .01
E-HS11-El 8 0 19 18 IO00
R-R2 510 lo00
R-R42 22 10 I k
L-L1 115 9uHIC=4.3
C-Cout 16 3 200uF IC=I 1.95
c-c2 18 10 lOOOpF IC=.02
c-Cl 18 5 320nF IC=.02
V-Vin 14 0 DC 0 AC 0
+PULSE 3.6 3.0 2ms 0 0 6m 8m
E-HSS-LIMIT4 12 0 VALUE {LIMI'T(V( 1 1),0,5))
R-HSS-Ro 12 13 .01
E-HS8-E 1 11 022 17 lo00
.
C. Buck-Boost Converter Netlist
v-Vd 1 20.7
D,D7 17 1 Dbreak
.MODEL Dbreak D Is= 1On Cjo=. 1 pF Rs=.O I
R-RL
L,L3
L Resr
C-cout
E-HS4-LIMIT4
R-HS4-Ro
E-HS4-E 1
c,c3
- .
30 .01
2 3 92uH IC=2
40 .017
17 4 5 7 ~ F IC=-12
9 0 VALUE (LIMIT(V(8).0,5))
9 10 -01
80 1920 loo0
5 20 16nF I C 4
R,R2 6 10 1200
V-Vref 190 3V
c-c 1
c,c2 20 10 13OOpF IC=12
R-R40 22 10 lk
R-Rc 220 lOOk
D-W 0 22 DbreakZ
.MODEL DbreakZ D Is= 1 On Cjo=. 1 pF Rs=.O 1 Bv=3.9
R- k 180 lk
V-Vr 18 0 DC 0 AC 0
+PULSE 0 4 0 9.911.0511 .Oh 1Ou
S-S 15 232 130S15
RS-S 15 130 IG
.MODEL SI5 VSWITCH Roff=lOe7 Ron=0.300
+Voff=O Von=.5
E-HSS-LIMIT4 12 0 VALUE [ LIMIT(V( 1 I),O,S))
R-HSS-Ro 12 13 .01
E-HS5-E 1 11 022 18lo00
v-v39 23 048
R-R43 70 lk
R-R42 177 3k
R-R44 721 lOOk
R-R 1 1620 10k
R-R3 5 16 133
E-HS6-LIMIT4 15 0 VALUE {LIMIT(V( 14),0,5))
R-HS6-Ro 15 16 .01
E-HS6-E 1 140021 1O00
R,R45 21 16 lOOk
R-R36 170 7.2
20 6 130nF IC=12
212