Stuck-At Fault:
A Fault Model for the next
Millennium?
Stuck-At Fault
I tell you, I get no respect!
-Rodney Dangerfield, Comedian
Janak H. Patel
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
The news of my death are highly exaggerated
-Mark Twain, Author
2005 Janak H. Patel
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Stuck-At Fault a Defect Model?
Stuck-At Fault as a Logic Fault
z Stuck-at Fault is a Functional Fault on a Boolean
(Logic) Function Implementation
z It is not a Physical Defect Model
Stuck-at 1 does not mean line is shorted to VDD
Stuck-at 0 does not mean line is grounded!
z It is an abstract fault model
A logic stuck-at 1 means when the line is applied a
logic 0, it produces a logical error
A logic error means 0 becomes 1 or vice versa
You can call it Abstract
Logical
Boolean
Functional
Symbolic
or Behavioral ... Fault Model
But dont call it a Defect Model!
Propagate Error To
Primary Output Y
Fault Excitation
1
A
0
D
1
F
Gs-a-0
D
C
E
B
ERROR
1/0
ERROR
1/0
0
0
0
H
Test Vector A,B,C = 1,0,0 detects fault G s-a-0
Activates the fault s-a-0 on line G by applying a logic
value 1 in line G
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Unmodeled Defect Detection
Defect Sites
z Internal to a Logic Gate or Cell
Transistor Defects Stuck-On, Stuck-Open,
Leakage, Shorts between treminals
z External to a Gate or Cell
Interconnect Defects Shorts and Opens
Other Logic
ERROR
Defect
D
C
ERROR
Y ERROR
0
GI
Fault Modeling
Defects in Physical Cells
z Physical
Physical Cells such as NAND, NOR, XNOR, AOI,
OAI, MUX2, etc.
For primitive gates such as NOT, NAND and NOR,
stuck-at tests are derived for faults on the pins.
For complex cells such as XOR, XNOR, AOI, OAI,
and MUX2 etc, Stuck-at Tests are assumed to be
derived on faults on gate equivalent models.
How good are these test vectors for a variety of
defects?
z Do we need additional vectors?
z Do we need transistor level details?
z Electrical
B
A
VDD
GND
z Logical
Z is Stuck-At-0
A
B
10
Non-Logical Values
Non-Logical Values
open
B
A
Indeterminate Value - N
A
1
Floating Node - Z
0
open
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12
Defect Detection in a NAND Gate
Two-Input NAND Gate
z For a 2-input NAND gate, the complete stuck-at
test set is: AB = 01, 10 and 11
z With a defect in the NAND cell, the gate may
produce any combinations of 0, 1, N, Z
N is an indeterminate logic value (active, driven)
Z is a floating node with unknown charge (passive)
z Each of 4 possible input vectors can produce any
of the 4 possible output values
256 possible defective behaviors for 2-input NAND
Infinitely
A
F
many delay and current behaviors
AB
a/0
F5
F6
F7
F8
00
b/0 a/1 b/1
1
F9
01
F256
10
11
z Is the stuck-at test set 01, 10 and 11 sufficient?
Fault Dictionary
13
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Defect Characterization
Vector 00 and 2-input NAND
z Inductive Contamination Analysis (ICA)
J. Khare, W. Malay and N. Tiday, VLSI Test Symp.
1996, pp. 407-413
Inductive Fault Analysis (IFA) is inadequate for three
dimensional defects in multi-layer cells
Experiment on 2-input NAND cell with 1000
particle contamination simulations. Assumed 84
major process steps, 2-metal C-MOS.
Reported 22 different fault behaviors in the paper
z Stuck-at test set (01,10,11) was sufficient for all
behaviors (my interpretation not theirs)
Pseudo Theorem:
In a 2-input NAND CMOS cell, there does not exist a
real physical defect that requires test vector 00 for
its exposure.
Proof:
If such a defect existed, it would make the gate
more functional than a NAND gate.
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Two-Input NAND Gate
Stuck-at tests for other Cells
z It can be shown that for all simple gates and
complex gates with fan-out free logic, stuck-at
test for pin faults is sufficient to expose any
defect inside the Cell
Simple Gates, NAND, NOR, NOT
Complex fan-out free Gates, AOI, OAI
A
F
AB
AB
a/0 b/0 a/1 b/1 F5
F6
F7
F8
F9
00
01
10
11
16
Even
functions such as: [(A+B)(C+D)+E]INVERT
z Pin fault stuck-at tests are not adequate for
complex gates with internal fanout-reconvergence
XOR, XNOR, MUX
Fault Dictionary
17
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Multiplexer Expansion
z Some of the defects within a cell produce
indeterminate logic N or floating node Z values for
some of the stuck-at vectors.
If a clean logic error (0-to-1, or 1-to-0) is possible,
a stuck-at test vector will expose it.
That means N and Z values cannot be avoided by
using test vectors other than stuck-at vectors.
If a clean logic error is not possible, Stuck-at
vectors are sufficient to expose the defect by
changing a correct logic value to either N or Z.
2-to-1
1 MUX
Y
Testing for Pin Faults
on A,B,C and Y will not
guarantee detection of
internal faults on
D,E,F,G and H.
C
G
A
F
D
C
What about N and Z values?
Y
E
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Defects External to a Gate
Shorts
z Opens
All opens external to a gate are detected by a
stuck-at fault test set
z Shorts
Input-to-Input Shorts on the same Gate
Input-to-Output Shorts on the same Gate
Output-to-Output Shorts on different Gates
Input to Input Short
Input to Output Short
Output to Output Short
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Input to Output Short
Input-to-Output Bridging Faults
z Validation of Stuck-at Fault Test Set Coverage
Circuits with Complex Gates
All Bridging Faults on the Input and Output on
the same Gate
Fault Simulation with E-PROOFS
z In a simple CMOS gate, if the short causes an
Error then Input value is forced upon the output Vierhaus, Meyer and Glaser, ITC-93
z This is also true for complex CMOS gates such as
And-Or-Invert (AOI) and Or-And-Invert (OAI) Cusey, M.S. Thesis, Illinois 1993
z Test Vectors for Input and Output Stuck-at Faults
cover Input-to-Output Shorts
Experiments Confirm this
0
0
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Total
Circuit Vectors Faults
% Faults Detected
0k
1k
2k
C432
C499
C880
100%
100%
94%
100
190
128
371
274
336
100%
100%
90%
43%
97%
70%
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Logic Model for a Short
A
B
C
D
Shorts and Stuck-at Tests
A
B
C
D
FAULT-FREE
G,H = 0,1
FAULTY
FAULT MODEL
G,H = 0,0 or H s-a-0 when G=0
G,H = 1,1
G s-a-1 when H=1
G,H = 1,0
G,H = 0,0 or G s-a-0 when H=0
G,H = 1,1
H s-a-1 when G=1
1 Test for G stuck-at 0
z Assume H dominates G with the Bridge present
z Test for G stuck-at 0 has no control over node H
z Probability that H has the correct logic value to excite
the Bridge is 0.5
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Probability of Detection
Repeated Detections
z The four stuck-at faults on nodes G and H require
a minimum of two test vectors
z Each test vector has a probability of Bridge
Excitation of 1/2
Probability that two test vectors miss the excitation
of the bridge is 1/4
Lower bound on expected bridge coverage is 75%
For most stuck-at test sets, a node gets tested
many more times than 2
z Example - ISCAS89 fullscan circuit S38417
99 test vectors, 31,015 faults detected
Number of
Repetitions
1
2
3
4
5
6
7
8
9
>10
Number of
Faults
3,411
1,710
1,262
1,043
861
925
821
834
808
19,340
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Probability of Bridge Detection
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Bridge Coverage with SSF Test Set
z Assume the stuck-at test set detects each node n
times
Probability of Bridge being detected is (1 - 1/2n)
z For example, let us say each stuck-at fault gets
detected 5 times.
That means each node gets detected 10 times.
The probability of Bridge detection is 99.9%
z Caveat: The Bridge must cause a Detectable error.
High Resistance Bridges do not affect the logic
value, and hence are undetectable by a static logic
test.
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Simulation of extracted bridges with Stuck-at Test
Sets using very accurate electrical level simulator
(EPROOFS, Greenstein, Patel, ICCAD 1992)
shows a very high coverage in ISCAS circuits.
Output to Output Bridges have comparable
coverage to a stuck-at fault coverage
Input to Input Bridges have lower coverage
because many of them are logically redundant
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SSF Test Set and Bridging Faults
Stuck-at
Vectors
Circuit
Large Custom Blocks
z Two major classes
Fully Complementary CMOS networks
All Others One-Sided networks.
Output to Output Bridges
0k
1k
2k
C499
C880
C1908
184
128
138
99.8%
96.9
98.8
77.5%
46.0
71.6
1.8%
3.9
1.8
C499
C880
C1908
184
128
138
Input to Input Bridges
91.5% 84.1% 0.0%
52.7
43.9
0.0
87.9
56.6
0.0
VDD
VDD
p
network
In
precharge
network
Out
n
network
(source: J. Cusey and J. Patel, ITC 1997, pp 838-847)
Gnd
Out
In
switch
network
Gnd
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Modeling Switch Networks
a
b
d
Fault Coverage Metrics
c
e
z A Stuck-at faults on Transistor terminals?
Not a very meaningful measure because Logic 1
and 0 do not always occur on all terminals, N and
Z values abound!
Gives
Express the network as AND-OR or OR-AND Network
C. E. Shannon, A symbolic analysis of relay and switching networks
Trans. AIEE, 1938.
Complementary transistors cannot be
independently controlled, results in many
untestable faults.
Gives
AND-OR: Each series path corresponds to an AND
unnecessarily pessimistic coverage
unnecessarily pessimistic coverage
z Gate level logic stuck-at coverage is already hard!
Dont make it any harder!
abc + abeh + adgec + adgh + fdbc + fdbeh + fgec + fgh + iec + ih
OR-AND: Each cut-set corresponds to an OR
(a+f+i)(a+d+g+i)...
Generate a stuck-at test set on either network
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Final Thoughts
z Logic Stuck-at Fault
Good for defects within a cell
Any
lower level model is too complex and inaccurate
Good for defects outside of a cell
Easy to model custom blocks for an ATG
Coverage metrics are well-defined
Automation is well-understood
Bridges
easy to cover without explicit targeting
Things should be made as simple as possible,
but not any simpler Albert Einstein
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