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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 2, MAY 2009
A Manufacturing Cost Model for 3-D Monolithic
Memory Integrated Circuits
Andrew J. Walker, Member, IEEE
AbstractImminent lateral scaling issues with NAND Flash are
forcing manufacturers to consider 3-D process integration to keep
single chip memory capacities rising while keeping costs down. In
this way, several layers of memory cells are stacked on top of a silicon substrate using a single series of process steps with no material bonding used. This paper presents a general and practical cost
model showing the advantages of 3-D process integration together
with the main parameters determining the total cost. This model
suggests that a mini revolution will soon be upon us consisting of
multiprogrammable stacked nonvolatile memory cells in a monolithic chip.
Index Terms3-D, memory, nonvolatile (NV), yield.
I. INTRODUCTION
HREE-DIMENSIONAL (3-D) stacking of circuits [1] is
being promoted as a way to increase CMOS performance,
reduce form factor, combine different materials and functions
all at reasonable cost and usually in this descending order of
importance. While this may be true for fast CMOS circuits,
the most important consideration for NAND Flash is cost. Up
until now, the way to increase capacity in a single package has
been to stack several NAND chips where each chip consists of
a single physical layer of Flash cells built into a silicon wafer
substrate. Successful scaling of lateral dimensions has allowed
the capacity per NAND chip to double almost every year with
the minimum feature size being the real half pitch in the technology.
NAND Flash scaling problems have been reported recently
with monolithic 3-D process integration being proposed as a
solution [2] to continue the decreasing cost per bit with increasing single chip capacities. To avoid confusion with other
3-D stacking approaches, the NAND Flash monolithic approach
consists of stacking several layers of memory cells on top of a
silicon substrate using a single series of process steps with no
material bonding required.
The cost analysis of such a monolithic 3-D approach is not intuitively obvious except for the simple-minded observation that,
for a certain memory capacity, cost is being added in the process
to decrease the die size and so increase the number of die per
wafer. In this way, monolithic 3-D integration can be seen in historical perspective where traditionally the way to decrease cost
per bit or transistor has been to laterally shrink and add process
complexity to solve the resultant process and device problems
[3]. Up until now, lateral scaling has been very successful in
the quest for decreasing cost per bit or transistor. Impending
physical limits to lateral scaling change the economics and result in monolithic 3-D integration becoming the least expensive
path to decreasing bit and transistor costs. The added process
complexity associated with 3-D replaces that arising from lateral scaling. The importance is to know the cost leverage.
Given the high probability that such monolithic 3-D integration will serve the NAND Flash market [4] it is the intention of
this paper to put the cost analysis on a firm footing.
This paper is organized as follows: Section II deals with yield
due to monolithic 3-D stacking; Section III presents a discussion on the process cost increase and die cost reduction from
increased die per wafer; examples in the use of the cost model
are given in Section IV; Section V contains a discussion of the
findings and Section VI concludes the paper.
II. YIELD
The effect on defect-limited-yield of adding process complexity is a well-trodden path in silicon manufacturing. For our
discussion here, Srednis general mathematical description will
form the basis for the analysis [5] with the same variable change
as used by Rung [6]. Thus we have:
(1)
where
is the defect-limited-yield,
is the defect density,
is the effective critical area in which the defects define the
yield, and is a parameter. With this equation choice for Y,
we do not limit ourselves to one particular non-composite yield
model since, as noted by both Sredni and Rung, this equation
, we have the Seedscovers most well-known models: for
, Dingwalls expression [9];
Price expression [7], [8]; for
, a close approximation to Murphys
expression
for
[10]; and for
, the Poisson expression. This general
equation for yield will help to show that the conclusions of the
cost model are independent of any particular yield model.
can be reasonably
In a high density 2-D Flash memory,
associated with the memory array area since this is the region
of the chip using the most aggressive design rules and so most
prone to spot defects. When we consider a 3-D Flash chip conlayers of devices, we can write the total yield of
sisting of
such a 3-D approach as
Manuscript received July 09, 2008; revised November 26, 2008. Current version published May 06, 2009.
The author is with the Schiltron Corporation, Mountain View, CA 94040 USA
(e-mail: andy@schiltron.com).
Digital Object Identifier 10.1109/TSM.2009.2017643
0894-6507/$25.00 2009 IEEE
(2)
WALKER: MANUFACTURING COST MODEL FOR 3-D MONOLITHIC MEMORY INTEGRATED CIRCUITS
269
Fig. 1. Ratio of 3-D yield to 2-D yield for different defect densities. The 2-D case has a fixed critical effective area at 2 cm which is then divided up into the 3-D
device layers. The yield parameter
is fixed at 1. Note the strong effect of defect densities on 3-D yield.
where all the symbols have the same meanings as above but for
each physical memory layer.
A practical simplification of (2) can be made with the reasonable assumptions that each memory layer in the 3-D stack
adds spot defects at the same rate as any other layer and that
these defects tend to affect the memory layer they are on and
not those layers above and below them. The first assumption can
be defended by the identical physical nature of each memory
layer and its associated processing steps. A slight adjustment
would be necessary perhaps if the first memory layer is in the
silicon bulk versus those monolithic memory approaches where
all layers are built above the silicon bulk [11] since the processing steps would be slightly different between the first layer
and all the rest. The second assumption is reasonable when the
individual memory layers are isolated from each other using a
dielectric that is thicker than the minimum feature size in each
memory layer (see for instance Jung). It is then envisaged that
spot defects are far likelier to cause problems in the layer they
are on than interfere with other layers.
With these assumptions, (2) becomes:
(3)
with the symbols having their definitions above.
It is instructive to compare the 3-D and 2-D yields for memory
chips that have the same total number of cells. Fig. 1 shows the
ratio of 3-D to 2-D yields as a function of the number of device
layers stacked in the 3-D case with defect density as a parameter.
This example used a fixed effective critical area of 2 cm (equivalent to 32 Gbit using 50 nm minimum feature size and 2 bits per
cell). The key is that this total effective area is distributed over
device layers in the 3-D case. Therefore, the
in (3) is the
. Fig. 1 shows that monolithic 3-D in2-D area divided by
tegration has very little impact on yield compared to 2-D when
the defect densities per device layer are on the order of those
already obtainable in advanced processes [12]. A further result
from this yield analysis is shown in Fig. 2. Here, the ratio of 3-D
to 2-D yields is shown as a function of increasing values of the
parameter with defect density as a parameter. Again, the ratio
of the yields is almost independent of the yield model chosen
when the defect densities per device layer are on the order of
those already obtainable in advanced processes. These are extremely important results for 3-D memory integration and will
be used later in the full cost model comparison with 2-D.
III. PROCESS AND DIE COST
When device layers are stacked in 3-D, the total process becomes more complex and expensive. We can calculate the wafer
cost of adding device layers with the following:
(4)
(5)
where
and
are the process costs of the wafer for 2-D
and 3-D respectively;
is the base wafer cost with all the support circuitry but without memory cells (assumed to be very
is the
similar in both the 2-D and 3-D approaches);
cost of a critical mask photolithography step and its associated
process steps in 2-D but then replicated in 3-D; is the rate of
increase in wafer cost between process generations [13] to account for the possibility that the 3-D approach can use older generations of technology (values between 1.5 and 2 were used by
Nakatsuka, but for NAND Flash may actually be increasing
due to the use of double patterning technology and any migration to more advanced wavelength lithography); is the number
of technology generations between the 2-D and 3-D approaches
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 2, MAY 2009
Fig. 2. The ratio of 3-D to 2-D yields as a function of
in the yield (3) with defect density as a parameter.
at 2 cm .
(0 if using the same node, 1 if 2-D is at 32 nm and 3-D uses
and
are the total number of
42 nm); and
critical masking steps needed in 2-D and 3-D respectively.
The total number of dice per wafer in both 2-D and 3-D can
be approximated by
(6)
where is the wafer diameter and
the 3-D case can be expressed as
is die area. The latter in
has been fixed at 5 and the effective critical area
for the number of 3-D device layers above the substrate needed
to achieve the minimum die size:
(9)
with all symbols defined before. It should be clear that the minimum die size given by (8) is not achievable if the first layer of
memory cells is placed in the substrate as is the case in the Jung
reference. In this case, (7) would have to be recast as follows:
(7)
is the total number of cells in the chip;
is the
where
is the area of a single memory
number of device layers;
is the array efficiency of the chip with a
cell on each layer;
single layer of cells defined as the memory array area as seen
from above divided by the total chip area and in %; MLC is a
variable for multilevel cell (1 for single bit per cell; 2 for 2 bits
per cell and so on).
It will be apparent that die size cannot continue shrinking
with added 3-D device layers since the CMOS driving circuitry
remains in the substrate. Indeed, the minimum die size along
with the number of added device layers needed to reach it can
be calculated. Imagine that all memory cells in a 2-D version
of a chip could be elevated above the substrate in 3-D fashion.
Then the minimum die size is given as the area originally taken
up by this peripheral substrate circuitry. This area is given as:
(8)
where all symbols have been defined before. Now, setting (7)
, we reach the following equation
equal to (8) and solving for
(10)
which shows (8) as an asymptotic limit at large
. This of
course would be at the expense of increased wafer cost given
in (5). The general point is that it is always better to elevate all
memory cells above the wafer substrate and keep the latter for
control circuitry to be able to minimize the die size at minimum
added process cost. We shall make this comparison more concrete below.
It is perhaps better in the interests of clarity to reformulate (7),
(8) and (10) in terms of the original 2-D die size. The results are:
(11)
when no memory cells are placed in the silicon substrate and
with a minimum at:
(12)
WALKER: MANUFACTURING COST MODEL FOR 3-D MONOLITHIC MEMORY INTEGRATED CIRCUITS
271
Fig. 3. Ratio of 3-D to 2-D die size as a function of the number of 3-D device layers for the cases where all memory cells are above the substrate and where the
first layer of memory cells are in the substrate.
The equivalent of (11) when the first layer of memory cells is
placed in the substrate is:
(13)
which clearly has no minimum but asymptotically approaches
(12) with increasing 3-D device layers as has been stated above.
Fig. 3 shows the ratio of 3-D to 2-D die sizes as a function of
the number of device layers stacked in 3-D for the two cases
where the first layer of memory cells is either above the substrate
or in the substrate. Clearly, putting all memory cells above the
substrate allows us to reach the minimum die size at lower added
process complexity.
We shall now revisit the yield equations given by (2) and
(3) with the realization that there is indeed a minimum die size
achievable with 3-D memory stacking. The key here is that the
has a
number of 3-D dice per wafer has a maximum since
minimum. However, the yield in a memory is defined by the ef, which is approximated by the memory
fective critical area,
per layer
array area. In 3-D for a fixed capacity memory,
increases even beyond the minimum
continues to shrink as
die size. Therefore, for a fixed capacity single chip memory
from a purely yield perspective, it pays to continue adding 3-D
memory layers. The cost of this will be taken up by the process
complexity and resultant wafer cost as given by (5).
IV. COST EXAMPLES
The general equation for the comparison of cost between the
3-D and 2-D approaches to achieve a memory of fixed capacity
can be given as
(14)
and
are the good die costs for 3-D and 2-D
where
respectively and where all other parameters have been defined
above.
In the first example, we shall look at the case of a 64 Gbit
Flash memory using a minimum feature size of 32 nm in both
2-D and 3-D. The defect density (per layer in the 3-D case) is
set at 0.1/cm . Other relevant parameters are: cell size in both
where is the minimum feature size; in
cases given as
yield model is 1; 300 mm wafer diameter; MLC is 2 for both
in 2-D is 75%; 2-D uses 4 critical lithography
2-D and 3-D;
is $2800 and
masks while 3-D uses 4 per device layer added;
is $200, similar to standard foundry numbers. Fig. 4
shows the cost comparison for this case.
The second example uses the inputs as in the first example
but changes the 3-D MLC to 1 which would model the initial
inability to do MLC in 3-D. Fig. 4 again captures this result.
The third example uses the approach where the 3-D version
of the chip would use older technology. In this case, a 64 Gbit
Flash memory is made in 2-D using the inputs as in the first
example. The 3-D version uses 42-nm technology at about one
generation behind 32 nm. The is set at 2. Fig. 4 shows the cost
comparison.
The fourth example is the same as the third except for a defect
density of 0.02 cm for the 42 nm technology versus 0.1/cm
for the 32-nm technology reflecting a more mature technology
node.
The fifth example is the same as the fourth except that the 3-D
version has MLC set at 1. Fig. 4 shows the result.
As NAND Flash manufacturers pursue lateral scaling, everything is being done to avoid a transition to the more expensive Extreme Ultra Violet (EUV) lithography. The measures
being taken include double patterning technology and immersion 193-nm lithography. Nevertheless, if the NAND cells can
indeed be laterally scaled, a transition point will be reached. The
cost model can take this into account through increasing as
used and defined in (5). Fig. 5 shows the example of the cost
advantage of 3-D stacking the older more mature (by that time)
technology at 32 nm versus the 2-D approach using 25 nm that
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 2, MAY 2009
Fig. 4. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) for various scenarios.
cm ;
;
for both; 2-D uses four critical masks; 3-D uses four critical masks
The 2-D AE0 was set at 75%. Example 1: 32 nm for both;
;
. Example 2: as example 1, but with
per device layer added;
for 3-D. Example 3: as example 1, but 3-D uses 42 nm
. Example 4: as example 3, but with
cm for 3-D. Example 5 as example 4, but with
for 3-D.
with
Z=2
C = $2800 C
D = 0:1
= $200
D = 0:02
= 1 MLC = 2
MLC = 1
MLC = 1
Fig. 5. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) with as a
cm ,
. The same base
and
parameter. 2-D uses advanced 25-nm half-pitch while 3-D uses more mature 32-nm half-pitch.
wafer and adder costs were used as in Fig. 4.
D = 0:1
would perhaps use EUV. For this example, a 64 Gbit was used
with all other parameters as given in the first example above.
Here we can see the increasing advantage of using 3-D even on
older technologies as the cost of the more advanced 2-D technology increases.
If we can use an older more mature technology in 3-D while
the 2-D approach is at the most advanced node, we may expect
that defect densities on the more mature technology would be
MLC = 2
AE = 75%
lower. This also has an impact on the relative costs as can be
seen in Fig. 6 where the 2-D approach is at a minimum half
pitch of 25 nm and 3-D is at 32 nm. The has been fixed at 3.
The defect density for 2-D has been set at 0.1/cm while the 3-D
defect densities vary to show the effect. All other parameters are
as in the first example above.
The ability to use older more mature technologies to compete
on cost allows us to take advantage of their lower defect densi-
WALKER: MANUFACTURING COST MODEL FOR 3-D MONOLITHIC MEMORY INTEGRATED CIRCUITS
273
Fig. 6. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) with the 3-D
as a parameter. 2-D uses advanced 25-nm half-pitch while 3-D uses more mature 32-nm half-pitch. 2-D
cm ,
,
and is fixed
at 3. The same base wafer and adder costs were used as in Fig. 4.
D = 0:1
MLC = 2 AE = 75%
Fig. 7. Ratio of 3-D to 2-D die costs as a function of the number of 3-D device layers added for a fixed capacity memory (64 Gbit in this case) with the 3-D
cm while all 3-D
cm to
technology half-pitch as a parameter indicating the use of older more mature technologies for 3-D. The 2-D
reflect their process maturity. is fixed at 3 to reflect the much more expensive 2-D node. MLC is 2 for all except the one case shown.
. The same
base wafer and adder costs were used as in Fig. 4.
ties. Fig. 7 shows the cost advantages of this strategy. In these
cases, the 2-D approach is at a minimum half pitch of 25 nm
and 3-D is fabricated at various older nodes. The defect density for 2-D is set at 0.1/cm while the 3-D defect density is
fixed at 0.01/cm to reflect the maturity of the older technologies. Fig. 7 shows the advantages of such an approach. Also included is the case where the 32 nm 3-D approach uses a single
to show that even this can be cheaper
level cell
than the advanced node with MLC at 2 if the defect conditions
are right.
The final example considers the case when 2-D lateral scaling
has reached its limit for NAND Flash. To provide solid-state
products with ever-increasing memory capacities to compete in
D = 0:1
D = 0:01
AE = 75%
the computer hard drive market, several possibilities are then
open to us: first, several 2-D dice stacked in a single package;
second, several 3-D dice stacked in a single package; third, one
monolithic 3-D die in a package. In this example, the following
assumptions have been made: 32 nm is the final lateral min; 64 Gbit
imum half-pitch, F; a single cell area is given as
is the final single 2-D die capacity; 2-D and 3-D approaches
consist of 2 bits per cell; 2-D array efficiency is 75%; 3-D has
no memory cells in the substrate; each new 3-D device layer
adds four critical lithography steps; the base wafer cost without
critical memory layers in 2-D and 3-D is $2800; each new critical lithography step and its associated process steps costs $200;
the 3-D die size reaches a minimum after four device layers
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 2, MAY 2009
Fig. 8. Ratio of 3-D cost to 2-D cost to achieve given capacity as a function of the capacity with defect density as a parameter. 32 nm half-pitch is assumed to be
the last laterally scaled node. 64 Gbit is then the final 2-D single chip. 3-D approaches consist of: either building single die with four device layers all above the
substrate and then chip-stacking these to achieve the capacity; or stacking device layers (above the substrate) monolithically on a single substrate to achieve the
, AE
, 3-D device layer consists of 4 critical lithography steps. The same base wafer and adder costs were used as in Fig. 4.
capacity.
MLC = 2
= 75%
have been added (therefore, the effective critical area in (3) is
fixed and does not shrink with increasing monolithic capacities
keeps on rising).
whereas
Fig. 8 shows the ratio of 3-D capacity cost to 2-D capacity
cost as a function of the single package memory capacity (no
costs have been added to the multichip cost originating from
the actual physical stacking and bonding). The two 3-D approaches are: first, make single chip 64 Gbit using four device
layers reaching the minimum die size and physically stack these
in a package similar to the 2-D multichip stacking; second, add
3-D device layers monolithically until the required capacity is
reached with the minimum die size having been reached after
four device layers. The variable parameter in Fig. 8 is the defect density per device layer (being equal to the defect density
in 2-D). Clearly, 3-D in whatever form provides a less expensive option to 2-D die stacking. Also, the defect density per device layer is the key to achieving low cost. The values for this
parameter are within the reach of existing memory production
facilities.
V. DISCUSSION
Monolithic 3-D integration has been touted since the early
1980s as the solution to impending CMOS lateral scaling limits
[14]. CMOS has however been successfully scaled since then.
The problems are now more severe in NAND Flash scaling
leading to new calls for monolithic 3-D integration specifically
for high density Flash. The resulting increase in process complexity and wafer cost can be seen in historical perspective as
being part of the same trend as coming from lateral scaling. Now
however, 3-D monolithic integration is gaining in impetus due
to the impending lateral scaling limits specific to NAND Flash.
Figs. 1 and 2 show monolithic 3-D die yield can be competitive provided defect densities are kept on their current trends
for 2-D. Fig. 4 shows that various degrees of freedom are made
available through 3-D integration to achieve low cost solutions.
Apart from the use of the most advanced tooling, older depreciated fabrication facilities could also be used to achieve
lower cost than 2-D approaches. This provides possibilities for
useful fab filling to manufacturers with spare capacity and
older tooling and could extend the life of such facilities. Fig. 4
also shows the appearance of an optimum number of 3-D device
layers the position of which depends on the compactness of the
substrate control circuitry.
The possibility of using older more mature technologies to
serve the high density Flash market is apparent from Figs. 57
where fabrication facility depreciation and lower defect densities could even allow single level cell in 3-D to be cheaper than
multi-level cells in 2-D at the advanced node.
An interesting example of the possibilities of 3-D monolithic
integration is that of the cost of increasing capacity solutions
specifically to be able to provide solid-state computer drives
at reasonable cost compared to magnetic hard drives. Fig. 8
showed the 3-D cost advantages over stacked 2-D dice. At the
time of writing, solid-state Flash-based drives are gaining a
foothold in the computer hard drive market but at significant
cost disadvantage. To be able to take sizable market share, the
Flash-based solution needs to drop in price. Clearly, several
lower cost scenarios become possible provided defect densities
are kept in control.
VI. CONCLUSION
The advent of lateral scaling limitations combined with
the ever-increasing market demand for high density NAND
WALKER: MANUFACTURING COST MODEL FOR 3-D MONOLITHIC MEMORY INTEGRATED CIRCUITS
Flash have given added impetus to monolithic 3-D integration.
This paper has presented a simple and practical cost model to
show the advantages of such an approach. Several degrees of
freedom are possible in achieving lower cost high density Flash
memory than the 2-D approach allows. The main points are the
following.
3-D monolithic stacking can achieve lower cost at both the
same technology node as and at older nodes than 2-D.
The optimum approach is to place all memory cells above
the substrate.
There is then a minimum in die size at a given number of
added device layers.
Monolithic stacking is the best path to lower bit cost as we
approach the limits to 2-D scaling.
We are not far from the situation where high density nonvolatile memory products consist of single chips each with four
or more active device layers in a monolithic stack. As in all
such mini revolutions in silicon technology, the cost drives the
change.
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Andrew J. Walker (M90) was born in Sialkot,
Pakistan, in December 1962. He received the B.Sc.
(Hons) degree in physics from Dundee University,
Scotland, in 1985 and the Ph.D. degree from the
Technical University of Eindhoven, The Netherlands, in 1994.
He was with Philips Research Laboratory, Eindhoven from 1985 to 1994 where he worked on
MOS transistor and nonvolatile memory physics
and technology. Between 1994 and 1998, he worked
primarily on ESD at Cypress Semiconductor, San
Jose, CA. After a one year stint at Artisan Components, Sunnyvale, CA, and
four years at Matrix Semiconductor, Santa Clara, CA, he became an ESD
consultant. He founded Schiltron Corporation to investigate new monolithic
3-D Flash technologies.
