Digital Electronics Lab Manual
DIGITAL ELECTRONICS LAB
EC-106(C-09)
Department of
DIPLOMA IN ELECTRONICS & COMMUNICATION ENGINEERING
Devineni Venkata Ramana & Dr.Hima Sekhar
MIC College of Technology
KANCHIKACHERLA
2014-15
Name : ________________________________
Regd. No. : _____________________________
Class : ________________________________
Year : _________________________________
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Digital Electronics Lab Manual
LIST OF EXPERIMENTS
DIGITAL ELECTRONICS LAB
EXP. NO.
PAGE
NO.
INDEX
Verify the truth tables of AND,OR,NOT,NAND,NOR and Exclusive
OR(Using ICs)
Develop NOT,OR and AND operations using universal gates
Construct Half adder and verify its truth table
Construct Full adder and verify its truth table
Construct and verify the truth tables of NAND and NOR latches
Verify the truth tables of RS,DT,and JK and MASTER-SLAVE JK flip-flops
Verify the function of counter (ICs like 7490,7493,74160)
Verify the function of shift register(ICs like 7495,74194 etc)
Verify the truth table of digial comparator using IC 7485
10
Construct and Verify the working of R-2R D\A converter.
11
Construct and Verify the working of Multiplexer(Using IC 74153)
12
Verify the working of Demltiplexers
13
Study the read and write operation of IC 7489
14
Design and simulate half adder,full adder circuits using workbench software
etc,,
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Digital Electronics Lab Manual
STUDENT NAME:
BRANCH:
S.NO
REG NO:
YEAR:
EXPERIMENT NAME
DATE
Verify the truth tables of
AND,OR,NOT,NAND,NOR and Exclusive
OR(Using ICs)
Develop NOT,OR and AND operations using
universal gates
Construct Half adder and verify its truth table
Construct Full adder and verify its truth table
Construct and verify the truth tables of NAND
and NOR latches
Verify the truth tables of RS,DT,and JK and
MASTER-SLAVE JK flip-flops.
7
8
STAFF
SIGNAT
URE
REMARKS/
GRAD
E
Verify the function of counter (ICs like
7490,7493,74160)
Verify the function of shift register(ICs like
7495,74194 etc)
Verify the truth table of digial comparator
using IC 7485
10
Construct and Verify the working of R-2R D\A
converter.
11
Construct and Verify the working of
Multiplexer(Using IC 74153)
12
Verify the working of Demltiplexers
13
Study the read and write operation of IC 7489
14
Design and simulate half adder,full adder
circuits using workbench software etc,.
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Digital Electronics Lab Manual
EXP NO: 1
DATE:
1.VERIFY THE TRUTH TABLES OF AND,OR,NOT,NAND,NOR AND
EXCLUSIVE OR (USING ICS)
AIM:
To study the operations and verify the truth tables of Logic Gates AND, OR, NOT,NAND,NOR
and Exclusive OR gates using ICs.
APPARATUS REQUIRED:
COMPONENTS:
1. IC 7408,7432 ,7404,7402 and 7486
EQUIPMENT:
1. IC Trainer Kit
2. Connecting wires, Patch chords
Theory:
AND Gate:
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs
are high. A dot (.) is used to show the AND operation i.e. A.B. The logic symbol and its
expression of AND Gate is shown in Fig. The IC 74LS08 is a two-input AND Gate IC it consists
of 4-AND gates. The IC has 14 pins as shown in Fig. The truth table of AND Gate is as shown in
table.
VCC = + 5V
14
13
12
11
13
10
12
11
C
8
10
B
6
GND
1
74LS08
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AND GATE
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Digital Electronics Lab Manual
OR Gate:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its
inputs are high. A plus (+) is used to show the OR operation. The logic symbol and its
expression of OR Gate are shown in Fig. The IC 74LS32 is a two in put OR Gate IC it consists
of 4-OR gates. The IC has 14 pins as shown in Fig. The truth table of OR Gate is as shown in
table.
OR - Gate Symbol
NOT Gate:
When in put variable A is low the output of a NOT gate is High. The logic symbol of
NOT Gate is shown in Fig .The IC 74LS04 is a single in put NOT Gate IC and it consists of 6NOT gates. The IC has 14 pins constructed in Dual in Line package(DIP) as shown in Fig. The
truth table of NOT Gate is as shown in Fig.
IC 74LS 04 NOT GATE
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NOT - Gate Symbol
VCC = + 5V
14
13
12
11
10
GND
1
74LS04 NOT GATE
NAND Gate:
The outputs of all NAND gates are high if any of the inputs are low. The logic
symbol of NAND Gate is shown in Fig .The IC 74 LS00 is a two input NAND Gate IC. It
consists 4 NAND gates built in. The truth table of NAND Gate is as shown in Table.
NOR Gate:
The outputs of all NOR gates are low if any of the inputs are high. The logic symbol
of NOR Gate is shown in Fig. The IC 74 LS02 is two in-put NOR Gate IC it consists of 4 NOR
gates. The truth table of NOR Gate is as shown
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EXOR Gate:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not
both, of its two inputs are high. . The logic symbol of EXOR Gate is shown in Fig .The IC
74LS04 is a single in put EXOR Gate IC and it consists of 4- EXOR gates. The truth table of
EXOR Gate is as shown in Table.
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PROCEDURE:
1.
Construct the circuit on breadboard for each Gate as shown in figures by inserting the
appropriate IC.
2.
Check the combinations of various inputs as shown in truth tables for each Gate.
3.
If the input is low connect input to Ground, which indicates logic 0.
4.
If input is high or logic 1 then connect the input to the power supply.
5.
When output is high the LED will glow which indicates output as high, if the LED is not
glowing then the output is low.
OBSERVATIONS:
Truth Table for NOT Gate
A
X=
0
1
Truth Table for NAND Gate
A
0
0
1
1
B
0
1
0
1
X=
RESULT:
Successfully checked and verified the operation of Basic Logic Gates through the truth
table.
Signature of Staff Member
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Digital Electronics Lab Manual
EXP NO: 2
DATE:
2.REALIZATION OF BASIC GATES USING UNIVERSAL GATES
AIM: To realize the Basic gates AND- OR NOT using universal gates (NAND and
NOR )Gates using ICs.
APPARATUS REQUIRED:
COMPONENTS:
1.IC 7400 AND 7402
EQUIPMENT:
1.Power supply
2.IC Trainer Kit
3.Connecting Wires/Patch Chords
Realize OR gate using NAND Gate:
Realize AND gate using NAND Gate:
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Realize AND gate using NOR Gate:
Realize AND gate using NOR Gate:
PROCEDURE:
1. Construct the circuit on breadboard for each Gate as shown in figures by inserting the
appropriate IC.
2. Check the combinations of various inputs as shown in truth tables for each Gate.
3. If the input is low connect input to Ground, which indicates logic 0.
4. If input is high or logic 1 then connect the input to the power supply.
5. When output is high the LED will glow which indicates output as high, if the LED is not
glowing then the output is low.
OBSERVATIONS:
Truth Table for NOR Gate
Truth Table for NAND Gate
A
0
0
1
1
RESULT:
B
0
1
0
1
A
0
0
1
1
X = A*B
B
0
1
0
1
X = A+B
Successfully realized Boolean expressions using AND-OR-NOT Gates, NAND and NOR
gates and verified the operation through the truth tables.
Signature of Staff Member
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EXP NO: 3
DATE:
REALISATION OF HALF ADDER
AIM:
To construct and check the truth tables for Half-Adder.
APPARATUS REQUIRED:
COMPONENTS:
1.
2.
3.
4.
IC 7408
IC 7486
LED - 2 nos
330 resistor-2 nos
EQUIPMENT:
1. Power supply
2. Bread Board.
3. Connecting wires
THEORY:
HALF ADDER:
LOGIC SYMBOL:
A
S = AB+ AB
HA
C = AB
The combinations for the sum and carry are written by the formula are given as.
S = AB+ AB
C = AB
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
Connect the logic circuit diagram of Half adder on bread board as shown in figures.
Give power supply to pin no. 14 of each IC.
Ground the pin no 7 of each IC.
Connect LEDs as an out put for sum, carry, difference and barrow.
Connect a 330 resistor in series with each LED.
Check the truth table for all combinations.
When output is high the LED will glow, indicates logic 1.
When output is low the LED will not glow, indicates logic 0
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CIRCUIT DIAGRAM:
TRUTH TABLE
A
0
0
1
1
B
0
1
0
1
S C C
PROCEDURE:
1 Connect the logic circuit diagram of Half adder on bread board as shown in figures.
2 Give power supply to pin no. 14 of each IC.
3 Ground the pin no 7 of each IC.
4 Connect LEDs as an out put for sum, carry, difference and barrow.
5 Connect a 330 resistor in series with each LED.
6 Check the truth table for all combinations.
7 When output is high the LED will glow, indicates logic 1.
8 When output is low the LED will not glow, indicates logic 0
RESULT:
Successfully constructed the Half-adder circuit using ICs and verified truth table.
Signature of Staff Member
EXP NO: 4
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DATE:
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Digital Electronics Lab Manual
REALISATION OF FULL ADDER
AIM:
To construct and check the truth tables for Full-Adder.
APPARATUS REQUIRED:
COMPONENTS:
5.
6.
7.
8.
IC 7408
IC 7486
LED - 2 nos
330 resistor-2 nos
EQUIPMENT:
4. Power supply
5. Bread Board.
6. Connecting wires
THEORY:
The Full Adder circuit is used to add three binary digits. The two outputs are sum- S and
carry-C. The three inputs are input A, input B and carry input C. The outputs are sum S and
carry out X. The construction of Full adder using two EX-OR Gates, two AND Gates and one
OR Gate is as shown in fig-3. The IC numbers are 7486, 7408 and 7432.
LOGIC SYMBOL:
The combinations for the sum and carry are written by the formulae are given as.
S = ABC + ABC+ ABC + ABC
X = AB + BC + AC
Sum- S
A
B
Full-Adder
Carry -X
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Full Adder Using Two Half Adders
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PROCEDURE:
1 Connect the logic circuit diagram of Full adder on bread board as shown in figures.
2 Give power supply to pin no. 14 of each IC.
3 Ground the pin no 7 of each IC.
4 Connect LEDs as an out put for sum, carry, difference and barrow.
5 Connect a 330 resistor in series with each LED.
6 Check the truth table for all combinations.
7 When output is high the LED will glow, indicates logic 1.
8 When output is low the LED will not glow, indicates logic 0
TRUTH TABLE FOR FULLADDER
A B C
Sum Carry
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
RESULT:
Successfully constructed the Full-adder circuit using ICs and verified truth table.
Signature of Staff Member
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DATE:
EXP NO: 5
NAND AND NOR LATCHES
AIM:
To construct and verify the truth tables of Logic Gates NAND and NOR latches.
APPARATUS REQUIRED:
COMPONENTS:
2. IC 7400,7402
EQUIPMENT:
3. IC Trainer Kit
4. Connecting wires,Patch chords
LOGIC CIRCUITS:
1.NAND LATCH:
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TRUTH TABLE:
INPUTS
R
0
0
1
1
S
0
1
0
1
OUTPUTS
NOT Q
OUTPUTS
NOT Q
2.NOR LATCH:
TRUTH TABLE:
INPUTS
R
0
0
1
1
S
0
1
0
1
PROCEDURE:
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1. Place the ICs on Trainer kit.
2. Connect vcc and ground pins of ICs at +5v and ground pins of IC Trainer kit respectively
3. Connections are made as per the logic circuit.
4. Connect the input to the input switches and the outputs to the output LEDS provided in
the IC Trainer kit.
5. Apply clock pulse wherever necessary.
6. Apply various combinations of inputs according to the truth table and observe the
condition of LEDS.
7. Hence , verify the truth table.
RESULTS:
Signature of Staff Member
EXP NO: 6
DATE:
FLIP FLOPS : RS, JK,T,D, MASTER SLAVE FF
AIM: To Study about Flip Flops and its applications.
APPARATUS REQUIRED:
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COMPONENTS:
1.
2.
3.
4.
5.
6.
IC 7400
IC 7410
IC 7476
IC 7474
LED 2 no.s
Single lead probes.
EQUIPMENT:
1. Flipflop trainer kit
2. Connecting wires/patch chords.
THEORY:
A flip-flop has two stable states. One of the stable states is known as SET or LOGIC 1 where
as the other stable is called RESET, CLEAR or LOGIC 0. It stores a binary digit either 0 or 1.
Types of flip-flops:
1) SR flip flop
2) JK flip flop
3) D flip- flop
4) T flip-flop
S-R Flip-flop
. When S=1 and R=0 after applying of clock pulse Q=1 and = 0,this state is know as set
condition. When S=0 and R=1 when clock pulse is high Q=0 and = 1,this is reset condition.
For the combination S=0 and R=0 the outputs will be the previous outputs only. The combination
S=1 and R=1 are not applied because the outputs will be toggling mode i.e. Outputs are not
stable.
S
Q
CLK
FF
Q
FIG 2. CLOCKED S-R FLIP-FLOP
JK Flip-flop
The construction of JK flip-flop using NAND gates is shown in fig-.
When clock is applied if J=1 and K=0 then the outputs Q=1 and =0 this condition is called as
SET. If J=0 and K=1 then the outputs Q=0 and =1 this is called as reset condition. The truth
table for the J-K flip flop is shown below. The JK flip flop can also be constructed by using an IC
74LS76. The Pin Description for IC 7476 are shown below:
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J
Q
CLK
FF
Q
FIG 5 .J-K FLIP-FLOP
D Flip-flop
The Logic symbol of D flip-flop is shown in fig 9. When clock is applied if D=1 then the
outputs Q=1 and =0. If D=0 then the outputs Q=0 and =1. The truth table for the D flip
flop is shown below. The D flip flop IC number is 74LS76. The Pin Description for IC 7476 are
shown below:
D
Q
CLK
FF
Q
FIG 9. D- FLIP-FLOP
T Flip-flop
WORK PROCEDURE:
1. Connections are made as per the logic symbols
2. Connect the logic input to input switches and logic outputs to o/p switches provided on the
FlipFlop Trainer kit
3. Apply clock iput to the pulser of trainer kit.
4. Set the synchronous inputs Reset/Clear and set/preset to logic 1 throughout the experiment
for all the flipflops
5. Switch on the trainer kit
6. Apply various combination of
inputs
TRUTH TABLE FOR
according to the truth tables and
observe
the
condition of LEDs
JK MASTER SLAVE FLIP FLOP
7. Hence verify the truth tables for
all flipflops.
J
K
Q
n+1
OBSERVATIONS:
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0
200
1
1
0
1
0
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Digital Electronics Lab Manual
TRUTH TABLE FOR
SR FLIP FLOP
S
Qn+1
TRUTH TABLE FOR
T FLIP FLOP
TRUTH TABLE FOR
D FLIP FLOP
D
Qn+1
Qn+1
RESULT:
Successfully constructed various flip-flops and verified their truth tables.
Signature of Staff Member
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EXP NO: 7
DATE:
COUNTERS
AIM:
To construct and check the Decade counter, Ripple counter and binary counters using
and IC 7493.
IC 7490
APPARATUS REQUIRED:
COMPONENTS:
1.
2.
3.
4.
5.
IC 7490
IC 7493
Resistors - 330 -- 8 nos.
LEDs -- 4 nos
Single lead probes.
EQUIPMENT:
1. Power supply
2. Bread Board.
IC 7490/ 7493 PIN DIAGRAM:
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PRINCIPLE:
7490 decade (0-9) ripple counter &7493 4-bit (0-15) ripple counter
These are ripple counters. The Counter outputs respond to a clock pulse. The count advances as
the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock
label. This is the usual clock behaviour of ripple counters and it means a counter output can
directly drive the clock input of the next counter in a chain.
The counter is in two sections: clock A-Q3 and clock B- Q2-Q1-Q0. For normal use connect QA
to clock B to link the two sections, and connect the external clock signal to clock A. For normal
operation at least one reset 0 input should be low, making both high resets the counter to zero
(0000, Q3-Q0 low). The 7490 has a pair of reset 9 inputs on pins 6 and 7, these reset the counter
to nine (1001) so at least one of them must be low for counting to occur. Counting to less than
the maximum (9 or 15) can be achieved by connecting the appropriate output(s) to the two reset0
inputs. If only one reset input is required the two inputs can be connected together. For example:
to count 0 to 8 connect Q3 (1) and Q0 (8) to the reset inputs.
IC 74LS 90 is used to count up to 9, ie.0 to 9 or 10 numbers. By applying input pulses
manually the output will be a number in the form of glowing LEDs. The sequence of counting is
as shown in table -.
Decade Counting
Clk Present State
I/P Q3Q2Q1Q0
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Next State
Q3Q2Q1Q0
Decimal
Number
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1
0 1 1
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 0
1 0 0 1
10 1 0 0 1
0 0 0 0
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7490
Digital Electronics Lab Manual
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PROCEDURE:
1. Setup the circuit as shown in fig-.
2. Now apply input signals at point A input manually (trigger pulses) and note sequence of
counting and check the outputs as given in the table.
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PRECAUTIONS:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Always use a straight lead probe to insert into the breadboard.
Apply proper grounding for ICs.
Check the starting pin number for each IC indicated with a dot as starting pin.
Use IC remover to remove IC from breadboard to avoid damage of pins of IC.
Dont touch the pins of ICs while power on.
Dont bend the pins of ICs.
Insert the components into the breadboard firmly.
Loose contact may result in error at output.
Give 1 level Voltage (+5V for TTL) or 0 level voltage to the inputs of the IC.
RESULT:
Successfully constructed the decade counter and observed the waveform and checked its
counting sequences such as Even- Odd, Even and Odd.
Signature of Staff Member
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EXP NO: 8
DATE:
SHIFT REGISTER(IC 7495,74194)
AIM:To study shift register using IC 7495 in all its modes i.e. SIPO/SISO, PISO/PIPO.
APPARATUS REQUIRED: IC 7495, etc.
Shift register trainer kit,
Connecting wires,patch cords
Serial In Parallel Out(SIPO):1. Connections are made as per circuit diagram.
2. Apply the data at serial i/p
3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift to
QB and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the
shift register.
Serial In Serial Out(SISO):1. Connections are made as per circuit diagram.
2. Load the shift register with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data d0 appears at QD.
4. Apply another clock pulse; the second data d1 appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data d3 to appear at
QD. Thus the data applied serially at the input comes out serially at QD
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Parallel In Serial Out (PISO):1. Connections are made as per circuit diagram.
2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at
A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the
Data coming out serially at QD
Parallel In Parallel Out (PIPO):1. Connections are made as per circuit diagram.
2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD
respectively.
Circuit diagram :-
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PISO:-
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RESULT:-
Signature of Staff Member
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EXP NO: 9
DATE:
DIGITAL COMPARATORS(IC 7485)
AIM:
i) To construct a Comparator using IC-7485 and to compare 2 BCD numbers in terms of
their Magnitude.
APPARATUS REQUIRED:
COMPONENTS:
1. IC-7485
EQUIPMENT:
1. IC Trainer Kit
2. IC7485
3. Connecting wires/Patch chords
.
THEORY:
The comparison of two numbers is an operator that determine one number is greater than,
less than (or) equal to the other number. A magnitude comparator is a combinational circuit that
compares two numbers A and B and determine their relative magnitude. The outcome of the
comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B.
A = A3 A2 A1 A0
and
B = B 3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit designated by the
symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits
starting from most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
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The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
x3 x2 x1 x0
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Functional table of IC 7485
PROCEDURE:
1. Connections are made as per the circuit diagram
2. Apply comparing inputs nad cascading inputs as per the truth table
3. Observe the corresponding inputs
4. Hence,verify the truth table.
RESULTS:
Signature of Staff Member
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DATE:
EXP NO: 10
R-2R DIGITAL to ANALOG - CONVERTER
AIM: To Study a 4 bit R-2R ladder type Digital to Analog converter circuit.
APPARATUS REQUIRED:
Components:
1. 8-BIT DIGITAL TO ANALOG TRAINER KIT
Equipments:
1. C.R.O.
2. CRO PROBES.
3. Power supply.
PRINCIPLE:
The purpose of Digital to Analog Converter is to convert a binary number or word to
a proportional analog current or voltage. An 8-bit DAC takes 8-bit data as input and generates a
proportional voltage signal as the output. The output range can be 0 to 2.56V. There are two
methods of DAC
1. Binary Weighted Resistor method
2. R-2R Ladder Network method
R-2R LADDER METHOD
It uses only two types of resistors (R & 2R) only. It removes the disadvantages of binary
DAC method. The circuit is as shown in figure. The input to the circuit is applied through digital
switches (0 & 1). If switch is in zero position the input is zero otherwise one. This network is
linear its operation can be analyzed as the output voltage from each source is independent of
other sources. The sum of all sources gives the output voltage and current.
CIRCUIT DIAGRAM:
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3R
Vo
1
2R
2R
2R
2R
2R
LSB
M SB
Thus the input of DAC is proportional to the sum of the weights represented by the
switches that are connected to a reference voltage V. When three input bits are used, only 2 3(or 8)
different analogue voltages can be signaled by the circuit; if the number of bits is increased to 4,
this becomes 24 (or 16) different voltages and so on. The full scale FS is the full-scale output of
the DAC and it is the maximum output voltage it can deliver to a load. The FS is given for an nbit DAC
FS = 2n 1/(2n X FSR)
FSR - Full-scale range is the value, which is divided into 2 n parts to determine the least
significant bit. For example the FSR of a DAC is 10 V. If the DAC is a 3 bit circuit, then
Least significant bit LSB = 10/23 = 1.25 V
Most significant bit MSB = 10/2 = 5 V
FS = 10 1.25 = 8.75 V.
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PROCEDURE:
1. Switch on the experimental board.
2. Connect he clock generator to the clock input terminals.
3. Apply the digital inputs to the terminals as shown.
4. Apply LSB to MSB terminals for Binary weighted method.
5. Apply the LSB to LSB and MSB to MSB terminals on kit.
6. Apply the count enable switch by pushing the switch.
7. Connect the CRO probes to CRO terminal.
8. Observe the waveform on screen of CRO.
9. Note down the voltage level for every input digit position.
OBSEVATIONS
DIGITAL INPUTS
D0(MSB) D1 D2
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D4
D5
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D6
D7(LSB)
ANALOG OUTPUT
OBSERVED CALCULATED
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PRECAUTIONS:
10. Always use a straight lead probe to insert into the breadboard.
11. Apply proper grounding for ICs.
12. Check the starting pin number for each IC indicated with a dot as starting pin.
13. Use IC remover to remove IC from breadboard to avoid damage of pins.
14. Dont touch the pins of ICs while power on.
15. Dont bend the pins of ICs.
16. Insert the components into the breadboard firmly.
17. Loose contact may result in error at output.
18. Give 1 level Voltage (+5v for TTL) or 0 level voltage to the inputs of the IC.
RESULT:
Successfully checked the analog output voltage for the given input digital combinations.
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DATE:
EXP NO: 11
MULTIPLEXERS - DATA SELECTOR
AIM:
To construct and check the Multiplexer using IC 74153 .
APPARATUS REQUIRED:
COMPONENTS:
1.
2.
3.
4.
IC 74153
Resistors - 330 -- 8 nos.
LEDs --8 nos
Single lead probes.
EQUIPMENT:
1. Power supply
2. Bread Board.
THEORY: Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are 2 n
input line and n selection lines whose bit combination determine which input is selected.
BLOCK DIAGRAM
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2n input line
andent any 2-variable ft is Y = A.B + A.B.ailable for multiplexers are 2:1, 4:1, 8:1 and 16:1. The
diff
Standard multiplexer ICs
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Procedure: - (IC 74153)
1. The Pin [16] is connected to + Vcc.
2. Pin [8] is connected to ground.
3. The inputs are applied either to A input or B input.
4. If MUX A has to be initialized, Ea is made low and if MUX B
has to be initialized, Eb is made low.
5. Based on the selection lines one of the inputs will be selected at the
output and thus verify the truth table
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RESULT:
Signature of Staff Member
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EXP NO: 12
DATE:
DEMULTIPLEXER USING 74139
AIM: - To verify the truth table of demultiplexer .
APPARATUS REQUIRED: IC 74139
THEORY
A demultiplexer is a combinational logic circuit with an input line, 2n output lines and n
select lines. It routes the information present on the input line to any of the output lines. The
output line that gets the information present on the input line is decided by the bit status of the
selection lines.
Procedure: - (IC 74139)
1. The inputs are applied to either a input or b input
2. The demux is activated by making Ea low and Eb low.
3. Verify the truth table .
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PRECAUTIONS:
1. Always use a straight lead probe to insert into the breadboard.
2. Apply proper grounding for ICs.
3. Check the starting pin number for each IC indicated with a dot as starting pin.
4. Use IC remover to remove IC from breadboard to avoid damage of pins of IC.
5. Dont touch the pins of ICs while power on.
6. Dont bend the pins of ICs.
7. Insert the components into the breadboard firmly.
8. Loose contact may result in error at output.
9. Give 1 level Voltage (+5V for TTL) or 0 level voltage to the inputs of the IC.
RESULT:
Successfully constructed the Demultiplexer Circuit and verified the Function Table.
Signature of Staff Member
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EXP NO: 13
DATE:
RANDOM ACESS MEMORY(RAM)(IC 7489)
AIM: To conduct an experiment to store a set of data in a RAM using IC 7489 starting from
location to location and retrieve the same data.
Apparatus Required: IC 7489, etc.
Procedure: 1.
Circuits connections are made to the appropriate pins of IC 7489
2.
First you have to write the data and then read the data, for writing data make WE to low
and ME input to low
3.
For a 4-bit data select any address input from A0 to A9. for ex, select A3 to A0 and
connect the data inputs/ outputs i.e., I/O4 I/O1
4.
Write a 4-bit data of your choice in each of the required address inputs or memory
locations
5.
By doing the above steps 2, 3 and 4 the data will be stored in the memory location
6.
For reading data
a. make WE to high and ME input to low
b. disconnect the data inputs I/O4 I/O1 from input lines and connect them to
output lines to read the data
c. and then give the address inputs of the data you have stored and observe the
outputs through I/O4 I/O1.
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RESULT:
Signature of Staff Member
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DATE:
EXP NO: 14
SIMULATION OF HALF ADDER,FULL ADDER
AIM:
To design and simulate half adder and full adder circuits using electronic workbench software.
APPARATUS REQUIRED:
Computer System,VHDL software.
SIMULATION PROGRAM:
1.HALF-ADDER:
Library IEEE;
Use IEEE.STD-LOGIC-1164.all;
Entity.h-adder is
Port(a:in STD_LOGIC;
B:in STD-LOGIC;
Sum:out STD-Logic;
Carry:out STD-Logic);
End h-adder;
Architecture half-adder-arch of h-adder is
Begin
Sum <= a xor b;
Carry<= a and b;
End half-adder-arch;
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FULL-ADDER:
Library IEEE;
Use IEEE.STD-LOGIC-1164.all;
Entity.
full-adder is
Port(a:in STD_LOGIC;
b:in STD-LOGIC;
c:in STD-LOGIC;
Sum:out STD-Logic;
Carry:out STD-Logic);
End Full-adder;
Architecture full-adder-arch of h-adder is
Begin
Sum <= a xor b xor c;
Carry<= (((a xor b) and c) or (a and b));
End full-adder-arch;
RESULTS:
Signature of Staff Member
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