Comm14 Version (I) Microprocessor

Project Regulations:
Number of students per group: 4 or 7 (not less and not more)
Format of the report: there are no strict guidelines for the report, but it should have not
more than 5 pages, you should deliver a CD that contains all project files with the report
Examination procedure: projects will be graded based upon the delivered report and
an oral discussion that must be attended by all team members.
Grading: The project will be graded out of 100.

Project Description:
-In this project, you should design a general purpose processor using VHDL targeting
FPGA platform. The general purpose processor has the following instruction set:
Instruction

Opcode

In A
Out A
HLT
NOP

11011011
11010011
01110110
00000000

MOV R1,R2

01DDDSSS

MVI R,d8

00DDD110
d8
00Rp0001
d16l
d16h
00111010
a16l
a16h
00110010
a16l
a16h

LXI Rp,d16
LDA [a16]
STA [a16]

ADC R
ADD R
ADI d8
SBB R
SUB R

10001SSS
10000SSS
11000110
d8
10011SSS
10010SSS

Operation
Comments
IN/OUT Instructions
A Data
Input data to accumulator
Data A
Output data from accumulator
Halt
The processor is stopped
No operation
Data Transfer Instructions
R1 R2
Source register R2 is moved or copied to
destination register R1
R d8
move immediate byte to register
Rl d16l
Rh d16h

load register pair Rp with immediate word

d16

A M[a16]

content of the memory location pointed to

by immediate operand value a16 is moved to
register A
M[a16] A
The content of accumulator A is stored in
main memory location whose address is a16
(immediate word)
Arithmetic instructions
A A + R + Cy
Add register R to A with carry
AA+R
Add register R to A
A A + d8
Add A to immediate value d8
A A - R - Cy
AAR
1

subtract register R from A with borrow

subtract register R from A

SUI d8
INR R
INX Rp
DEC R
DEX Rp
ANA R
ANI d8

11010110
d8
00111SSS
00Rp0011
00110SSS
00Rp1011

A A d8

Subtract immediate value d8 from A

RR+1
Increment R
Rp Rp + 1
Increment Rp
RR1
Decrement R
Rp Rp + 1
Decrement Rp
Logic instructions
AA&R
AND Accumulator with R
A A & d8
AND Accumulator with immediate value d8

ORA R
ORI d8
XRA R
CMA
RLC

10100SSS
11000110
d8
10110SSS
11110110
10101SSS
00101111
00000111

RRC

00001111

Rotate A Right
Circular

RAL

00010111

Rotate
Accumulator A
Left

RAR

00011111

Rotate
Accumulator A
Right

CMP R

10111SSS

AR

CPI d8

11111110
d8

A d8

AA|R
A A | d8
AA^R
~A
Rotate A Left
Circular

OR Accumulator with R
OR Accumulator with immediate value d8
XOR Accumulator with R
Complement Accumulator
Each binary bit of the accumulator is rotated
left by one position. Bit D7 is placed in the
position of D0 as well as in the Carry flag.
CY is modified according to bit D7.
Each binary bit of the accumulator is rotated
right by one position. Bit D0 is placed in the
position of D7 as well as in the Carry flag.
CY is modified according to bit D0.
Each binary bit of the accumulator is rotated
left by one position through the Carry flag.
Bit D7 is placed in the Carry flag, and the
Carry flag is placed in the least significant
position D0. CY is modified according to bit
D7.
Each binary bit of the accumulator is rotated
right by one position through the Carry flag.
Bit D0 is placed in the Carry flag, and the
Carry flag is placed in the most significant
position D7. CY is modified according to bit
D0.
Compare:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero
flags are reset
Compare:
if (A) < (d8): carry flag is set
if (A) = (d8): zero flag is set
if (A) > (d8): carry and zero flags are
reset

JMP a16

Branching instructions
PC a

11000011
a16l
a16h
11011010
a16l
a16h
11010010
a16l
a16h
11110010
a16l
a16h
11001010
a16l
a16h
11000010
a16l
a16h
11001101
a16l
a16h
11001001

JC a16
JNC a16
JP a16
JZ a16
JNZ a16
CALL a
RET

Unconditional jump

If Cy = 1:
PC a

Jump on carry

If Cy = 0:
PC a

Jump on No carry

If S = 0:
PC a

Jump on plus

If Z = 0:
PC a

Jump on zero

If Z = 1:
PC a

Jump on No zero

SP PC
PC a

Unconditional Call

PC SP + 1

Return

Registers (See table 1)

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store
operations.
Flag is an 8-bit register containing 4 1-bit flags:

Sign - set if the most significant bit of the result is set.

Zero - set if the result is zero.
Parity - set if the parity (the number of set bits in the result) is even.
Carry - set if there was a carry during addition, or borrow during subtraction/comparison.

D7
S

D6

D5

D4

D3

D2
P

D1

D0
CY

General registers:
8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a
pair the C register contains low-order byte. Some instructions may use BC register as a
data pointer.
8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a
pair the E register contains low-order byte. Some instructions may use DE register as a
data pointer.
8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a
pair the L register contains low-order byte. HL register usually contains a data pointer
used to reference memory addresses.

Stack pointer is a 16 bit register. This register is always incremented/decremented by 2.

Program counter is a 16-bit register.
Table1: Microprocessor Comm14 Registers
7
0 7
0
B

SPH
PCH

SPL

(program counter)

15

PCL

increment/decrement register

Table 2: Register Bits

DDD or SSS bits:

register names:

000

001

010

011

100

101

110

M[HL]

111

A
4

Table 3: Register Pairs for Opcode

Rp bits:

register pairs (rh, rl):

00

B, C

01

D, E

10

H, L

11

SP

Memory
Program, data and stack memories occupy the same memory space. The total addressable
memory size is 64 KB.
Program memory - program can be located anywhere in memory. Jump, branch and call
instructions use 16-bit addresses, i.e. they can be used to jump/branch anywhere within 64 KB.
All jump/branch instructions use absolute addressing.
Data memory - the data can be placed anywhere as the Comm14 processor always uses 16-bit
addresses.
Stack memory is limited only by the size of memory. Stack grows downward.

Requirements:
First:
Design the Data path and verify its functionality for random inputs for the different
operations. Show clearly in your reports the internal design and the main steps of design
verification.
Second:
Design the control unit using any method you want.
(Hint: the easiest and feasible method is FSM)
Third:
Design the whole CPU unit by connecting the components in one top entity.
Fourth:
To verify the correctness of your design, you will test it for some test programs detailed
below. This will be done in two steps:
5

Convert the program to the machine code of Comm14 and write the code in the memory
as detailed later and simulate the program on your processor.

Test Programs:
Solved Example: Addition of two 8-bit numbers.
Solution:
MVI

C,00

LDA

4200

MOV B,A

LABEL1:

LDA

4201

ADD

JNC

LABEL1

INR

STA

4202

MOV A,C
STA

4203

HLT

Sample Output:

Input: 15H(4200)
27H(4201)
Output:3CH(4202)
00H(4203)

Test Program: 1.

Assume that you have an array, and the target is to get

the index as well as the value of its maximum value.
Hint: Using C you can perform this task as follows:
C code Example:
Int x[5]={7,14,20,27,6}; // create an array of integers and initialize it
Int index, max_value; // index and value of the maximum
6

Index = 0; // initialize the index variable to the first location in the array
Max_value = x[index]; // max is assumed to be the first value in the array
For(int i=1; i<5;i++)
{
If (max_value < x[i]) // the maximum is less than the current element
{ // update the index and the max_value to the current element
Index = i;
Max_value = x[i];
}
}
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2. HEX to ASCII Conversion.

3. BCD to HEX Conversion.

Best Regards,