HDL Coder Workshop

10th February 2016, Trondheim

Why are we here today?

Learn more about HDL Coder

The why, how, and what

Get some hands on experience

Its more fun than just looking

Give you the possibility to talk with MathWorks representatives

Share your thoughts, give us feedback We are here for you!

What to do?

Agenda
09:00

1. Introduction to Model-Based Design

2. MATLAB to HDL workflow
3. MATLAB HDL Verification

4. Simulink to HDL workflow

16:00

5. Simulink HDL Verification

Who is Who?

Before we start

c:\class\coursefiles\hdl03
(and the handouts on your desk)

Things to remember .

Enable collaboration by integrating workflows with Model-Based Design

Reduce development time with Automatic HDL Code generation

Reduce verification time with HDL/FPGA Co-simulation

Agenda
09:00

1. Introduction to Model-Based Design

2. MATLAB to HDL workflow
3. MATLAB HDL Verification

4. Simulink to HDL workflow

16:00

5. Simulink HDL Verification

Introduction to Model-Based Design

Integrated HDL Workflow

Introduction to Model-Based Design

Integrated HDL Workflow

10

Who is involved in the design?

11

Introduction to Model-Based Design

System Designer

FPGA Designer

Algorithm Design

System Test Bench

RTL Design

Verification

Fixed-Point

Environment Models

IP Interfaces

Behavioral Simulation

Timing / Control Logic

Analog Models

HW Architecture

Functional Simulation

Architecture Exploration

Digital Models

Static Timing Analysis

Algorithms / IP

Algorithms / IP

Timing Simulation

Implement Design
FPGA Requirements
Hardware Specification
Test Stimulus

Back Annotation

Synthesis
Map
Place & Route

FPGA Hardware

12

Introduction to Model-Based Design

System Designer

FPGA Designer

Algorithm Design

System Test Bench

RTL Design

Verification

Fixed-Point

Environment Models

IP Interfaces

Behavioral Simulation

Timing / Control Logic

Analog Models

HW Architecture

Functional Simulation

Architecture Exploration

Digital Models

Static Timing Analysis

Algorithms / IP

Algorithms / IP

Timing Simulation

Implement Design
FPGA Requirements
Hardware Specification
Test Stimulus

Back Annotation

Synthesis
Map
Place & Route

FPGA Hardware

13

MATLAB and Simulink

Algorithm and System Design
Model Refinement for Hardware

Automatic HDL
Code Generation

HDL Co-Simulation

Behavioral Simulation

Back Annotation

Implement Design
Synthesis
Map
Place & Route

Verification
Functional Simulation
Static Timing Analysis
Timing Simulation

FPGA Hardware
FPGA-in-the-Loop
14

MATLAB and Simulink

Algorithm and System Design
Model Refinement for Hardware

Automatic HDL
Code Generation

HDL Co-Simulation

Model-Based Design
Behavioral Simulation

Back Annotation

Implement Design
Synthesis
Map
Place & Route

Verification
Functional Simulation
Static Timing Analysis
Timing Simulation

FPGA Hardware
FPGA-in-the-Loop
15

Example

16

From model to implementation

Integrated HDL Workflow Video Mosaick

17

From model to implementation

Integrated HDL Workflow Video Mosaick

18

From model to implementation

Integrated HDL Workflow Video Mosaick

Microcontroller

19

From model to implementation

Integrated HDL Workflow Video Mosaick

FPGA
Corner
Detection

Microcontroller

20

From model to implementation

Integrated HDL Workflow Corner Detection

21

From model to implementation

Integrated HDL Workflow Corner Detection

22

From model to implementation

Integrated HDL Workflow Corner Detection

Test Bench

23

From model to implementation

Integrated HDL Workflow Corner Detection

Test Bench

24

From model to implementation

Integrated HDL Workflow FIR Filter

FPGA in the loop

Simulation

Behavioral
Simulation

Stand Alone
Prototype

25

Algorithms to HDL?

26

Algorithm to HDL Workflows

1.
2.

MATLAB to HDL
Simulink to HDL
(with MATLAB and Stateflow)

1
3.

Hybrid workflow
3

VHDL & Verilog

VHDL & Verilog

27

Agenda
09:00

1. Introduction to Model-Based Design

2. MATLAB to HDL workflow
3. MATLAB HDL Verification

4. Simulink to HDL workflow

16:00

5. Simulink HDL Verification

28

MATLAB at a glance
Exercise

The leading environment

for technical computing

Interactive development environment

Technical computing language
Data analysis and visualization
Algorithm development

29

Exercise

30

MATLAB at a glance | Exercise

Getting Started
(1) Navigate to folder
01_MATLAB_intro

(3) When you create a variable it

will appear in the MATLAB
workspace

(2) Type the following commands in the

MATLAB command window

(4) Use domain specific visualization

methods

31

MATLAB to HDL
The big challenges

MATLAB

HDL

Floating point
Procedural
Matrices

Algorithm Land

Architecture Land

Fixed-Point

Concurrent + optimized
Block RAMs

Untimed

Timed with rates

Loops

Streaming, Unrolling

Functions
System objects

Hardware-efficient
implementations
32

MATLAB to HDL
Workflow
MATLAB Algorithm and System Design
Model Refinement for Hardware
Iterative
Refinement
using
Fixed-Point Advisor

Conversion to Fixed Point

and Fixed-Point Verification

HDL Code Generation

Refinement and
Design Exploration

HDL Simulation
Implement Design
Synthesis
Map
Place & Route

33

How do I get good

results on my FPGA?

34

MATLAB to HDL
How do I get good results on my FPGA?

1. Author MATLAB for hardware

2. Leverage HDL Coder workflow

3. Use synthesis and implementation tools

35

MATLAB to HDL
How do I get good results on my FPGA?

1. Author MATLAB for hardware

2. Leverage HDL Coder workflow

3. Use synthesis and implementation tools

36

MATLAB to HDL | Author MATLAB for hardware (1/3)

Think Hardware! Separate Test Bench from Algorithm

Contains stimulus and visualization code

Contains algorithmic function targeted for
implementation in FPGA or ASIC

Test Bench

+
Hardware Algorithm

Example :
Hardware Algorithm

37

MATLAB to HDL | Author MATLAB for hardware (2/3)

MATLAB Authoring Best Practices

Use Persistence when modeling:

Behavioral registers (e.g. tap delay lines)

RAM or ROM

Constant arrays

State machines

Think like
hardware
!

38

MATLAB to HDL | Author MATLAB for hardware (3/3)

MATLAB Authoring Best Practices

Arrays can be represented as:

Wires

Flip-Flops

RAM

ROM

Think about how arrays are used in the design to get the best results
39

MATLAB to HDL
How do I get good results on my FPGA?

1. Author MATLAB for hardware

2. Leverage HDL Coder workflow

3. Use synthesis and implementation tools

40

MATLAB to HDL | Leverage HDL Coder Workflow (1/3)

Why use fixed-point?

Fixed-point designs are:

Smaller in silicon
Use less power
Give good performance

FPGAs contain fixed-point arithmetic

units optimized for performance

Careful control of word length allows

designers to balance resources and
sample rate against fixed-point
performance
41

MATLAB to HDL | Leverage HDL Coder Workflow (2/3)

Fixed-point conversion

Automated workflow to convert floating point MATLAB to fixed-point

MATLAB

42

Exercise

43

MATLAB to HDL | Exercise

Fixed-point conversion (1/7)

Automated workflow to convert floating point MATLAB to fixed-point

MATLAB

44

MATLAB to HDL | Exercise

Fixed-point conversion (2/7)

(1) Navigate to folder 02_MATLAB_2hdl

(2) Type in MATLAB

command window

(5) Click here to start Workflow

Advisor

(3) Select fir.m

(4) Select fir_tb.m

45

MATLAB to HDL | Exercise

Fixed-point conversion (3/7)

(1) click Run

Input types are defined based on configured test

benches

46

MATLAB to HDL | Exercise

Fixed-point conversion (4/7)

Select options:
(1) Log histogram data
(2) Show code coverage

Based on Simulation min/max range fixed-point

types are proposed

(3) Click on the green play button to

start simulation

(2) Select Propose word lengths

and default fraction length 8

Use the logged histogram data to further refine

the proposed types

47

MATLAB to HDL | Exercise

Fixed-point conversion (5/7)

The coverage analysis is visually shown in the MATLAB code, this is a

good quality measure of your test bench
48

MATLAB to HDL | Exercise

Fixed-point conversion (6/7)

(1) Click on the validate types to generate fixedpoint MATLAB code

This step Automatically generates fixed-point MATLAB code

49

MATLAB to HDL | Exercise

Fixed-point conversion (7/7)
(3) Repeat all steps with a default fraction length of 10, how
much is the difference now?

(2) Click on the green play button to run a

simulation

(1) Enable Log inputs and outputs for comparison

plots

This step runs a simulation to test the numerical

accuracy, please note also the graphical difference plot
50

MATLAB to HDL | Leverage HDL Coder Workflow (3/3)

HDL Coder

Automatically generate optimized HDL code from MATLAB

51

Exercise

52

MATLAB to HDL | Exercise

HDL Coder (1/6)

Please note the different workflows:

1. Generic ASIC/FPGA
2. FPGA Turnkey
3. IP Core Generation (Zynq)

(1) Choose Generic ASIC/FPGA

(2) No synthesis tool specified

53

MATLAB to HDL | Exercise

HDL Coder (2/6)

(1) Set all options as shown in these GUIs

54

MATLAB to HDL | Exercise

HDL Coder (3/6)

(1) Please note the options to integrate

with Simulink and System Generator
55

MATLAB to HDL | Exercise

HDL Coder (4/6)

(1) Click on Run to

generate HDL code

(2) Click on this link to see the resource

utilization report

56

MATLAB to HDL | Exercise

HDL Coder (5/6)

(1) Click on this link to open one of the

generated HDL files

57

MATLAB to HDL | Exercise

HDL Coder (6/6)

(2) Look at the resource

utilization report to see the
result

(1) Enable Stream loops to save

resources and click Run
58

Agenda
09:00

1. Introduction to Model-Based Design

2. MATLAB to HDL workflow
3. MATLAB HDL Verification

4. Simulink to HDL workflow

16:00

5. Simulink HDL Verification

59

MATLAB to HDL | Leverage HDL Coder Workflow (4/3)

HDL Verification
MATLAB Test bench

Stimulus

MATLAB Design
Targeted to Hardware

Reference
Results

Automatically Generated HDL Test Bench

Stimulus

HDL Design

Actual
Results
60

Exercise

61

MATLAB to HDL | Exercise

HDL Verification (1/2) | Stimuli driven simulation

(2) Check out the Test Bench

Options

(3) Click on the green Run button to

start verification

(1) Select the options as shown in

this GUI

62

MATLAB to HDL | Exercise

HDL Verification (2/2) | Stimuli driven simulation

(1) Click on this link to open the

simulation report

63

MATLAB to HDL | Leverage HDL Coder Workflow (5/3)

HDL Verification | Co-simulation

MATLAB Functions
Stimulus

Input
stimuli

Response

HDL
Entity

Output
response

Out

Re-use system level test bench

Combine analysis in HDL Simulator and MATLAB/Simulink

In

HDL Simulator

HDL Verifier
Connects HDL simulation with
the MATLAB environment!

64

MATLAB to HDL | Exercise

HDL Verification (1/2) | Co-Simulation

(2) Check out the Test Bench

Options

(1) Select the options as shown in

this GUI

(3) Click on the green Run button to

start verification
65

MATLAB to HDL | Exercise

HDL Verification (2/2) | Co-Simulation

Analyze output based on HDL

and MATLAB analysis

Proof absence of errors

66

MATLAB to HDL | Leverage HDL Coder Workflow (6/3)

HDL Verification | Co-simulation of Hand Written Code

Use the cosimWizard to integrate

hand-written HDL code for verification with MATLAB
and Simulink

67

Demo

68

MATLAB to HDL | Leverage HDL Coder Workflow (7/3)

HDL Verification | FPGA-in-the-Loop

Re-use the MATLAB test bench

Accelerate Verification with FPGA Hardware
Stimulus

Input
stimuli

MATLAB Functions

Response

Output
response

HDL Verifier
Connects FPGA HW with the
MATLAB environment!

69

Demo

70

MATLAB to HDL | DEMO

HDL Verification | FPGA-in-the-Loop

(3) Click on the green Run

button to start

(1) Configure all options and

choose your FPGA board

(2) Download more FPGA

boards or add your own
71

MATLAB to HDL | DEMO

HDL Verification | FPGA-in-the-Loop

Analyze the FPGA

output based on
MATLAB analysis

Proof absence of errors,

through FPGA verification
72

MATLAB to HDL | Leverage HDL Coder Workflow (7/3)

HDL Verification | FPGA-in-the-Loop Wizard

Both MATLAB and Simulink based FPGA-inthe-loop

Use the filWizard to integrate

hand-written HDL code for
FPGA verification
Custom board support

73

MATLAB to HDL
How do I get good results on my FPGA?

1. Author MATLAB for hardware

2. Leverage HDL Coder workflow

3. Use Synthesis and Implementation Tools

74

MATLAB to HDL | Use Synthesis and Implementation Tools (1/1)

Automated Workflow for FPGA Implementation
Integration with Vivado, Xilinx ISE and Altera
Quartus II

Project creation
Synthesis
Place and Route
Reporting
Resource utilization
Timing analysis
Use loop streaming to reduce
resource utilization

Rapidly explore implementation options through quick iteration of trade-offs such as

sample rate and resource utilization

75

MATLAB to HDL | User Story

FLIR Accelerates Development of Thermal Imaging

Challenge
Accelerate the implementation of advanced thermal imaging filters and algorithms
on FPGA hardware

Solution
Use MATLAB to develop, simulate, and evaluate algorithms, and use HDL Coder
to implement the best algorithms on FPGAs

Results
Time from concept to field-testable prototype
reduced by 60%
Enhancements completed in hours, not weeks
Code reuse increased from zero to 30%

With MATLAB and HDL Coder we are much more

responsive to marketplace needs. We now embrace change,
because we can take a new idea to a real-time-capable
hardware prototype in just a few weeks.
There is more joy in engineering, so weve increased job
satisfaction as well as customer satisfaction.
Nicholas Hogasten, FLIR Systems

Link to user story

76

MATLAB to HDL
Summary

#1: Integrate separated workflows

Connect MATLAB algorithm developer with FPGA engineer
One language, better collaboration

#2: Automatic HDL code generation

Rapidly explore implementation options
Make the right trade-off choices

#3: HDL/FPGA Co-simulation

Combine MATLAB analysis methods with FPGA/HDL analysis
Use the best of both worlds
77

Agenda
09:00

1. Introduction to Model-Based Design

2. MATLAB to HDL workflow
3. MATLAB HDL Verification

4. Simulink to HDL workflow

16:00

5. Simulink HDL Verification

78

Algorithm to HDL Workflows

1.
2.

MATLAB to HDL
Simulink to HDL
(with MATLAB and Stateflow)

1
3.

Hybrid workflow
3

VHDL & Verilog

VHDL & Verilog

79

Simulink at a glance | Flexible Design Environment

Design and Simulation

Simulink, MATLAB and Stateflow

Integrate with MATLAB Filter Design
80

Simulink at a glance | Enable Collaboration with Simulink Projects

Version Control
Manage design-related files
efficiently within Simulink

Search, manage, and share related files in

a Simulink project
Access version control functionality
Peer review of changes using XML
comparison tools
Merge Simulink models from within XML
comparison report
View revision information
Impact Analysis
81

Exercise
(Getting Started)

82

Simulink at a glance | Exercise

Getting Started

83

Simulink at a glance | Exercise

Getting Started | Part 1 (1/2)

(3) Open
Simulink Library Browser
(1) Navigate to folder
06_Simulink_intro

(4) Open new

Simulink model

(2) Define model parameters in the

MATLAB workspace

84

Simulink at a glance | Exercise

Getting Started | Part 1 (2/2)
(5) Drag & drop the blocks from
library into model and connect
them:

(7) Define simulation

runtime (L/Fs)

(8) Hit Start button

Simulink/Sources
Simulink/Math Operations
Simulink/Sinks

(6) Double-click on blocks and parameterize

them:
Sine Wave:
Amplitude: 0.7; Frequency: 2*pi*50
Sine Wave1:
Frequency: 2*pi*120
Random Number:
Variance: 2; Sample Time: T

85

Simulink at a glance | Exercise

Getting Started | Part 2 (1/2)
(1) Drag & drop the blocks from library into model
and connect them:

Simulink/Discrete
Simulink/Math Operations
DSP System Toolbox/Transforms
DSP System Toolbox/Sinks

(7) Select
Scope Properties:
Input Domain: Frequency
Axis Properties:
Y-axis scaling: Magnitude
(5) Select
Output: Magnitude

(2) Define
Sample time: T
(3) Define
Output buffer size: L

(4) Tick
Scale result by FFT length

(6) Set
Gain: 2

86

Simulink at a glance | Exercise

Getting Started | Part 2 (2/2)
(9) Hit Start button

(8) Select in Display menu:

Signal & Ports:
Signal Dimensions
Port Data Types
Sample Time
Colors

87

Simulink to HDL
Model-Based Design for Implementation

1. Design and Simulation

2. Fixed-Point Conversion

3. HDL Creation

88

Simulink to HDL
Model-Based Design for Implementation

1. Design and Simulation

2. Fixed-Point Conversion

3. HDL Creation

89

Exercise
(Design and Simulation)

90

Simulink to MATLAB | Exercise

Design and Simulation (1/5)

(1) Navigate to folder

07_Simulink_Design_Simulation

(2) Load matlab.mat

(3) Launch
Filter Design & Analysis Tool

(4) Open model

my_equalizer.slx

91

Simulink to MATLAB | Exercise

Design and Simulation (2/5)

(1) Explore design hierarchies

(3) Left filter bank will be added

afterwards

(2) Filter_Hd4 will be generated in next step

using fdatool
92

Simulink to MATLAB | Exercise

Design and Simulation (3/5)
(1) Open session
fdatool.fda

(2) Open
Filter Manager

(3) Select Hd4_df2sos

(4) Examine filter

characteristics

93

Simulink to MATLAB | Exercise

Design and Simulation (4/5)

(2) Define block name,

e.g. Filter_Hd4

(4) Hit
Realize Model

(6) Compare block content with

content of other filters

(1) Select
Realize Model

(3) Select
Build model using basic
elements

(5) Move automatically generated

block in its intended position

94

Simulink to MATLAB | Exercise

Design and Simulation (5/5)

(1) Move one hierarchy level up

(Equalizer_Subsystem)

(2) Duplicate filter_bank_right

(4) Hit Start button

(3) Instantiate it at the intended

position and rename instance name,
e.g. filter_bank_left

95

Simulink to HDL
Model-Based Design for Implementation

1. Design and Simulation

2. Fixed-Point Conversion

3. HDL Creation

96

Simulink to HDL | Fixed-Point Conversion (1/2)

Fixed-Point Designer

Convert floating-point to optimized fixed-point models

Automatic tracking of signal range
for both Simulink blocks and MATLAB function block

Using simulation and/or static analysis

Word / Fraction lengths proposal

97

Simulink to HDL | Fixed-Point Conversion (2/2)

Fixed-Point Designer

Automatically compare simulation results,

e.g. Floating-Point vs. Fixed-Point

98

Exercise
(Fixed-Point Conversion)

99

Simulink to HDL | Exercise

Fixed-Point Conversion (1/12)

(1) Navigate to folder

08_Simulink_FixedPoint
(3) Update Diagram (Ctrl-D)
(2) Open model
my_equalizer_fixed_point.slx

(4) Examine Fixed-Point

data types

100

Simulink to HDL | Exercise

Fixed-Point Conversion (2/12)

(1) Descend in model

hierarchy to
filter_bank_right

(2) Right-click on output

signal of multiplier and
select Properties

(3) Select
Log signal data
101

Simulink to HDL | Exercise

Fixed-Point Conversion (3/12)

(1) Go one level up in the model

hierarchy to
Equalizer_Subsystem

(2) Right-click on
filter_bank_right
and select
Fixed-Point Tool

102

Simulink to HDL | Exercise

Fixed-Point Conversion (4/12)

(1) Select Model-wide no

override and full
instrumentation

(3) Start simulation

(4) Examine quantized dynamic

range of simulation results,
e.g. gain11

(2) Please note: Name for

simulation run,
NoOverride

103

Simulink to HDL | Exercise

Fixed-Point Conversion (5/12)

(1) Select gain11 in the Inspect

Signals tab

104

Simulink to HDL | Exercise

Fixed-Point Conversion (6/12)
(1) Select Range collection
using double override

(3) Start simulation

(4) Examine floating point

dynamic range of simulation
results,
e.g. gain11

(2) Please note: Name for

simulation run,
DoubleOverride

105

Simulink to HDL | Exercise

Fixed-Point Conversion (7/12)

(1) Compare original fixed-point

scaling with floating-point
reference
(Compare Signals tab)

(2) Difference due to limited

resolution in fraction part
(inherent to fixed-point scaling)

106

Simulink to HDL | Exercise

Fixed-Point Conversion (8/12)

(1) Click on Derive min/max

values for selected system

(2) Examine the Derived dynamic

range based on input specification
ranges

107

Simulink to HDL | Exercise

Fixed-Point Conversion (9/12)

(1) Configure autoscaling

properties

(3) Hit auto-scaling button

(2) Select fraction length based

autoscaling (Propose word lengths)
108

Simulink to HDL | Exercise

Fixed-Point Conversion (10/12)

(2) Select appropriate Column View

(1) Select DoubleOverride run for

auto-scaling reference

(3) Examine fixed-point

scaling proposal

(4) Apply new fixed-point

scaling

109

Simulink to HDL | Exercise

Fixed-Point Conversion (11/12)
(1) Select Model-wide no
override and full
instrumentation

(3) Start simulation

(4) Examine newly quantized

dynamic range of simulation
results, e.g. gain11

(2) Define identifier for

simulation run, e.g.
NoOverride final

110

Simulink to HDL | Exercise

Fixed-Point Conversion (12/12)

(1) Compare original fixedpoint scaling with optimized

fixed-point scaling

(2) No differences, i.e. same

precision with less area
consumption

111

Simulink to HDL
Model-Based Design for Implementation

1. Design and Simulation

2. Fixed-Point Conversion

3. HDL Creation

112

Simulink to HDL | HDL Creation (1/7)

Automatic HDL Code Generation

Automatically generate bit-true, cycleaccurate HDL code from Simulink, MATLAB

and Stateflow

Full bi-directional
traceability!!

113

Exercise
(Automatic HDL Code Generation)

114

Simulink to HDL | Exercise

Automatic Code Generation (1/4)

(1) Navigate to folder

09_Simulink_HDL

(2) Open model

my_equalizer_fixed_point.slx

115

Simulink to HDL | Exercise

Automatic Code Generation (2/4)

(2) Select
HDL Coder Properties

(1) Right-click on
Equalizer_Subsystem
116

Simulink to HDL | Exercise

Automatic Code Generation (3/4)

(1) Select Equalizer_Subsystem

(2) Select HDL of your choice

(VHDL / Verilog)

(3) Select the traceability and resource

utilization reports

(4) Hit
Run Compatibility Checker

(5) Hit
Generate

117

Simulink to HDL | Exercise

Automatic Code Generation (4/4)

(2) Follow the link to the

corresponding block in the
Simulink model

(1) Examine automatically

generated, generic RTL HDL code

(3) Right-Click and select HDL Code > Navigate to Code to follow link
from model to HDL code

118

What else is there?

119

Simulink to HDL | HDL Creation (2/7)

HDL Supported Blocks

~180 blocks supported

Core Simulink Blocks

Signal Processing Blocks

Basic and Array Arithmetic, Look-Up Tables, Signal Routing

(Mux/Demux, Delays, Selectors), Logic & Bit Operations, Dual
and single port RAMs, FIFOs, CORDICs, Busses

NCOs, FFTs, Digital Filters (FIR, IIR, Multi-rate, Adaptive, Multichannel), Rate Changes (Up &Down Sample), Statistics
(Min/Max)

Communications Blocks

Pseudo-random Sequence Generators, Modulators /

Demodulators, Interleavers / Deinterleavers, Viterbi Decoders,
Reed Solomon Encoders / Decoders,
CRC Generator / Detector
120

Simulink to HDL | HDL Creation (3/7)

MATLAB & Stateflow for HDL

MATLAB
Relevant subset of the MATLAB language for modeling and
generating HDL implementations
Useful MATLAB Function Block
Design Patterns for HDL

Stateflow
Modeling FSMs (Mealy, Moore)
Use different modeling paradigms (Graphical Methods,
State Transition
Tables, Truth Tables)

Integrate MATLAB

121

Simulink to HDL | HDL Creation (4/7)

Model Reference

Partition larger designs into smaller models

Incremental HDL code generation
Engineer 1

Engineer 2
122

Simulink to HDL | HDL Creation (5/7)

Integrating Legacy Code

Integrate legacy HDL code in

Simulink using black boxes

Configure the interface to legacy

HDL code

123

Simulink to HDL | HDL Creation (6/7)

Integrating System Generator Subsystems
HDL Coder provides an automated
workflow to integrate System
Generator

Take advantage of specific System

Generator functionality

124

Simulink to HDL | HDL Creation (7/7)

Integrate DSP Builder Advanced Blockset
Take advantage of specific Simulink
or DSP Builder functionality

HDL Coder provides an automated workflow to

integrate DSP Builder Advanced Blockset
components

125

Simulink to HDL
Model-Based Design for Implementation

1. Design and Simulation

2. Fixed-Point Conversion

3. HDL Creation

126

How do I get good

results on my FPGA?
(Optimization etc.)

127

Simulink to HDL
How do I get good results on my FPGA?

1. Modeling Best Practices

2. Speed Optimization

3. Area Optimization

128

Simulink to HDL | Modeling Best Practices (1/7)

Efficient Mapping to FPGA Resources

Pre-adder in Virtex-6 / Spartan-6

129

Simulink to HDL | Modeling Best Practices (2/7)

Efficient Mapping to FPGA Resources
Advanced HDL Synthesis Report (Selected Device : 6vsx315tff1156-1):
------------------------------------------------------------------Macro Statistics
# MACs
: 4
17x16-to-33-bit Mult with pre-adder
: 1
17x16-to-35-bit MAC with pre-adder
: 3
# Registers
: 224
Flip-Flops
: 224
Advanced HDL Synthesis Report (Selected Device : 5vsx50tff1136-1):
-----------------------------------------------------------------Macro Statistics
# MACs
: 2
17x16-to-34-bit MAC
: 2
# Multipliers
: 2
17x16-bit registered multiplier
: 2
# Adders/Subtractors
: 5
17-bit adder
: 4
35-bit adder
: 1
# Registers
: 195
Flip-Flops
: 195
130

Simulink to HDL | Modeling Best Practices (3/7)

Lookup Tables to ROM
Reset type set to none

Reset needs to be synchronous

Need a registered output, reset type set to none
It is good practice to structure your table such that the spacing between
breakpoints is a power of two
Input datatype determines how much memory will be allocated, 12 bits
2^12 = 4096
131

Simulink to HDL | Modeling Best Practices (4/7)

Lookup Tables to ROM

132

Simulink to HDL | Modeling Best Practices (5/7)

Block RAM Utilization

Dual/Single Port RAM

Integer Delay

FFTs

133

Simulink to HDL
How do I get good results on my FPGA?

1. Modeling Best Practices

2. Speed Optimization

3. Area Optimization

134

Simulink to HDL | Speed Optimization (1/2)

Finding the Critical Path

Finding the critical path in our model

Applying pipelining strategies to improve speed

135

Demo

136

Simulink to HDL | Demo

Finding the Critical Path (1/8)

(1) Navigate to folder

10_Simulink_SpeedOpt

(2) Open model

my_equalizer_sim_optimization.slx

137

Simulink to HDL | Demo

Finding the Critical Path (2/8)

(1) Open HDL Workflow Advisor

on subsystem EqualizerAlgorithm

138

Simulink to HDL | Demo

Finding the Critical Path (3/8)
(1) Select synthesis tool, e.g.
Xilinx ISE

(2) Select target FPGA device, e.g.

Virtex4

(3) Hit Run Task

139

Simulink to HDL | Demo

Finding the Critical Path (4/8)

(1) Model Preparation and HDL

Code Generation

140

Simulink to HDL | Demo

Finding the Critical Path (5/8)

(1) Trial synthesis using specified

synthesis tool

(2) Result: Static Timing Analysis

(STA) report

141

Simulink to HDL | Demo

Finding the Critical Path (6/8)

142

Simulink to HDL | Demo

Finding the Critical Path (7/8)

(1) Annotate critical timing path to

Simulink model

143

Simulink to HDL | Demo

Finding the Critical Path (8/8)
(1) Starting point of critical timing
path

(2) End point of critical timing

path

144

Simulink to HDL | Speed Optimization (2/2)

Strategies for Speed Improvement

Fixed-Point Conversion
Optimal Fixed-Point will save area and improve critical path

Architectural choices, e.g.

Linear, tree, cascade
Factored-Canonical-Signed-Digit (FCSD)
Newton-Raphson Approximation CORDIC

Pipelining
Input / Output pipeling
(Hierarchical) Distributed pipelining
Delay Balancing
145

Exercise
(Pipelining)

146

Simulink to HDL | Exercise

Speed Optimization | Pipelining (1/7)

(1) Navigate to folder

10_Simulink_SpeedOpt

(2) Open model

my_equalizer_sim_optimization.slx

(3) Navigate to subsystem

EqualizerAlgorithm/filter_subsystem/filter_bank_left

147

Simulink to HDL | Exercise

Speed Optimization | Pipelining (2/7)

(1) Right-Click on Sum of Elements Block and select

HDL Code > HDL Block Properties

(3) Move one hierarchy level up

(2) Specify OutputPipeline to 3

148

Simulink to HDL | Exercise

Speed Optimization | Pipelining (3/7)
(1) Right-Click on filter_bank_left Block and select
HDL Code > HDL Block Properties
(3) Open Code > HDL Code
and generate HDL code for
Equalizer Algorithm
(2) Turn DistributedPipelining on

149

Simulink to HDL | Exercise

Speed Optimization | Pipelining (4/7)

(1) Chose Distributed Pipelining report

(2) Open generated model

150

Simulink to HDL | Exercise

Speed Optimization | Pipelining (5/7)
(1) Navigate to filter_bank_left

(5) Close generated model

(2) The 3 output pipeline stages got

distributed

(4) Verify delay balancing also on upper

hierarchy levels

(3) Dependent paths got balanced

151

Simulink to HDL | Exercise

Speed Optimization | Pipelining (6/7)
(1) Open filter_bank_left
subsystem again

(4) Regenerate HDL code on

EqualizerAlgorithm level,
open Distributed Pipelining report,
open generated model
(2) Open HDL Block Properties of
multiplier block

(3) Specify ConstrainedOutputPipeline to 1

152

Simulink to HDL | Exercise

Speed Optimization | Pipelining (7/7)

(5) Close generated model

(3) Output pipeline of Sum block got adjusted

to match overall number of pipeline stages (3)

(2) Multiplier block got 1 output

delay

(1) Navigate to filter_bank_left

(4) Balanced delay got adjusted as constrained output pipeline is placed in

combined path
153

Simulink to HDL
How do I get good results on my FPGA?

1. Modeling Best Practices

2. Speed Optimization

3. Area Optimization

154

Simulink to HDL | Area Optimization (1/1)

Resource Folding Algorithms

Goal
Area reduction

Means
Time-multiplexed re-use of
resources

Algorithms
Resource Sharing

Re-use of identical operators

or atomic subsystems within
algorithm

Resource Streaming

Re-use of vectorized
operators or subsystems
155

Exercise
(Area Optimization)

156

Simulink to HDL | Exercise

Area Optimization | Streaming (1/8)

(1) Navigate to folder

11_Simulink_AreaOpt

(2) Open model

my_equalizer_sim_optimization.slx

(3) Navigate to subsystem

EqualizerAlgorithm/filter_subsystem/filter_bank_left

157

Simulink to HDL | Exercise

Area Optimization | Streaming (2/8)

(1) Note vectorized coefficients

(2) Note vectorized output

(4) Goal: Parallel filter channels shall be

implemented by single filter, but timemultiplexed (resource streaming)

(3) Scalar input signal is therefore processed by channel

filter (operators are parallelized)

158

Simulink to HDL | Exercise

Area Optimization | Streaming (3/8)

(1) Open HDL Block Properties of

subsystem Filter
(3) Regenerate HDL code on
EqualizerAlgorithm level

(2) Specify StreamingFactor of 10

159

Simulink to HDL | Exercise

Area Optimization | Streaming (4/8)

(1) Open Streaming and Sharing

report

(2) Open generated model

160

Simulink to HDL | Exercise

Area Optimization | Streaming (5/8)

(2) Examine filter architecture

(1) Navigate to EqualizerAlgorithm/filter_subsystem/filter_bank_left/Filter

161

Simulink to HDL | Exercise

Area Optimization | Streaming (6/8)
(2) Scalar input signals get aligned to
serialized sample rate

(1) Vectored input signals get

serialized and stored in shift registers
162

Simulink to HDL | Exercise

Area Optimization | Streaming (7/8)
(1) Intermediate results get stored in
shift registers to separate results of the
different filter channels

163

Simulink to HDL | Exercise

Area Optimization | Streaming (8/8)

(1) Output signal gets vectorized again

164

What else is there?

165

Simulink to HDL | Legacy Code Integration

Black Boxing Integration of an Audio Decoder

3rd party IP cores

Integrating legacy code
Handwritten HDL code
166

Simulink to HDL | Integration with Downstream Tools

EDA Scripts

Integrate with downstream implementations tools

Automatically create build scripts
Generate multicycle path constraint reports

167

What if you need both

DSP and FPGA?
168

System-on-Chip | HW/SW Co-Design

SoC Workflow

=
System

+
Hardware

Software

169

System-on-Chip | HW/SW Co-Design

SoC Example

170

System-on-Chip | HW/SW Co-Design

SoC Example

FPGA

171

System-on-Chip | HW/SW Co-Design

SoC Example

FPGA

ARM Cortex A9
172

System-on-Chip | HW/SW Co-Design

Targeting the ARM and the FPGA?

1. How to map algorithms to the FPGA on the Zynq?

2. How to map algorithms to the ARM on the Zynq?

173

System-on-Chip | HW/SW Co-Design

SoC Workflow

174

System-on-Chip | HW/SW Co-Design

Targeting the ARM and the FPGA?

Hardware generation
HDL Coder (VHDL and Verilog)
Software

Hardware

Embedded software generation

ARM
Processor

AXI Bus

Embedded Coder

HW IP Core

HW IP Core
ZYNQ

175

DEMO
(SoC Workflow - Zynq)

176

Customer developing Image Processing

application on Zynq platform

Challenge
Improve performance: from 50 Frames Per Second (fps) to >400 fps
Timeframe: complete project by end of 2015
Embedded software engineer heard about Zynq but never programmed FPGAs

Solution
Mathworks Model-Based Design approach for Zynq
Xilinx ZC702 development board

Results
Customer plans to release a new product to market in H1 of 2014;
a year ahead of schedule
Save costs replacing 3 processors and 3 cameras with one Zynq device
and one camera
Expects to sell > 100,000 units a year!

177

Agenda
09:00

1. Introduction to Model-Based Design

2. MATLAB to HDL workflow
3. MATLAB HDL Verification

4. Simulink to HDL workflow

16:00

5. Simulink HDL Verification

178

Simulink HDL Verification

Model-Based Design for Implementation

1. Requirement Traceability
2. Structural Testing

3. Regression Testing
4. Rapid Prototyping

179

Simulink HDL Verification | Requirement Traceability

Simulink Verification and Validation

Automatically generate bit-true, cycleaccurate HDL code from Simulink, MATLAB

and Stateflow

Full bi-directional
traceability!!

Requirements

180

Exercise
(Requirement Traceability)

181

Simulink HDL Verification | Exercise

Simulink Verification and Validation | Requirements Traceability (1/4)

(1) Navigate to folder

12_Simulink_requirements
(2) Open model
my_equalizer_requirements.slx
-andOpen MS Word document
Requirements_start.docx

182

Simulink HDL Verification | Exercise

Simulink Verification and Validation | Requirements Traceability (2/4)
(1) Select the requirements text in the
MS Word document

(2) RMB > Requirements > Add link to

Word selection
183

Simulink HDL Verification | Exercise

Simulink Verification and Validation | Requirements Traceability (3/4)

(1) Ctrl-LMB click to highlight the

linked block in Simulink

(2) RMB > Requirements >

1. Filter banks IIR SOS
to highlight the linked requirement

184

Simulink HDL Verification | Exercise

Simulink Verification and Validation | Requirements Traceability (4/4)

(1) Generate HDL code from the

Equalizer_Subsystem,
goto line 191 of Equalizer_Subsystem.vhd
in the traceability report

(2) Please note the hyperlinked

requirement in the report, click on this
link

185

Simulink HDL Verification

Model-Based Design for Implementation

1. Requirement Traceability
2. Structural Testing

3. Regression Testing
4. Rapid Prototyping

186

Simulink HDL Verification | Structural Testing

Simulink Verification and Validation | Test Coverage (Model)

Automatically collect and

report test coverage

Missed
coverage

100%
coverage
187

Simulink HDL Verification | Structural Testing

Design Verifier | Test Generation for 100% Test Coverage (Model)

Automatically generate tests to

reach coverage objectives

188

Exercise
(100% Coverage Testing)

189

Simulink HDL Verification | Exercise

Design Verifier | Achieving 100% Test Coverage (1/4)

(1) Navigate to folder

13_Simulink_coverage

(2) Hit the simulate button

190

Simulink HDL Verification | Exercise

Design Verifier | Achieving 100% Test Coverage (2/4)
(2) Open the effect_selection FSM
Please note the color coding indicating uncovered transitions,
click on a red colored transition to see why it is not covered

(1) Analyze the generated coverage report

How much coverage do we have?
191

Simulink HDL Verification | Exercise

Design Verifier | Achieving 100% Test Coverage (3/4)

(2) 77 test objectives are needed for 100% test coverage,

select Create harness model

(1) RMB > Design Verifier > Generate Tests for Subsystem
192

Simulink HDL Verification | Exercise

Design Verifier | Achieving 100% Test Coverage (4/4)
(2) Click here to simulate all stimuli
What is the test coverage now?

(1) Double click to open Signal Builder stimuli (if

not already open)
How many test cases are generated?

193

Simulink HDL Verification | Structural Testing

Design Verifier + HDL Verifier | Test Coverage (HDL Code)

Re-use system level test bench

Combine analysis in HDL Simulator and MATLAB/Simulink
Stimulus

Simulink Test Bench

Response

Input stimuli

Output
response

Input stimuli

Output
response

194

Exercise
(100% Code Coverage)

195

Simulink HDL Verification | Exercise

Design Verifier + HDL Verifier | Achieving 100% Test Coverage (1/2) - (HDL Code)
(2) Open and Analyze
gm_my_equalizer_coverage_harness_mq.tcl
-andTest_Unit_copied_from_EQ_Parameters0_compile.do

(1) Open the model gm_my_equalizer_harness_mq.slx

Please note: this model is automatically generated by
HDL Coder

196

Simulink HDL Verification | Exercise

Design Verifier + HDL Verifier | Achieving 100% Test Coverage (2/2) - (HDL Code)
(2) Run all test cases
Hint: open the Signal Builder GUI
(3) HDL Verifier block which connects
Simulink with
ModelSim/QuestaSim
(1) Double click here to start
ModelSim/QuestaSim

(4) How much HDL code

coverage did we get?

(5) Please note the Simulink

scopes, is there a difference?
197

Simulink HDL Verification

Model-Based Design for Implementation

1. Requirement Traceability
2. Structural Testing

3. Regression Testing
4. Rapid Prototyping

198

Simulink HDL Verification | Regression Testing

HDL Verifier | FPGA-in-the-Loop

Re-use system level test bench

Accelerate Verification with FPGA Hardware
Use application specific analysis methods

Stimulus

Input stimuli

Simulink Test Bench

Response

Output
response

199

DEMO
(FPGA-in-the-Loop)

200

Simulink HDL Verification | Demo

HDL Verifier | FPGA-in-the-Loop

Integration with FPGA

development boards
Add your own FPGA board (needs
Ethernet)

Automatic creation of FPGA-inthe-Loop verification models

201

Simulink HDL Verification

Model-Based Design for Implementation

1. Requirement Traceability
2. Structural Testing

3. Regression Testing
4. Rapid Prototyping

202

Simulink HDL Verification | Rapid Prototyping

FPGA Turnkey Workflow

Music in

Stand alone testing of algorithms on

FPGA hardware

Music out

Integrate with Altera / Xilinx

FPGA Development Boards

Automated workflow from model to

FPGA prototype

Demo
203

DEMO
(FPGA Turnkey)

204

Workshop
Summary

#1: Integrate separated workflows

One model, one language, better collaboration
Easily make algorithm trade-offs which impact performance

#2: Automatic HDL code generation

Rapidly explore implementation options
What-if analysis for Area / Speed / Power

#3: HDL/FPGA Co-simulation

Combine Simulink analysis methods with FPGA/HDL analysis
Use the best of both worlds flexible test bench creation
205

Other Resources: Tutorials

207

Other Resources: We are here to help you!

Accelerating return on investment
Process
Deployment /
Standardization
Advisory
Services

Jumpstart
Services

Pilot Programs

Team or Project Specific

Department / Corporate-wide Initiative

208

Other Resources: We are here to help you!

Accelerating return on investment
Developers of MATLAB & Simulink
$700M annual revenue from
125+ Countries

23,000+ Companies
7+ Major Industries

Headquarters in Natick, MA
World-wide footprint
2,400 total staff world-wide
World-wide technical and customer support

Technology focus
30% of revenue invested in R&D

Accelerate the pace of engineering and science

209

Other Resources: We are here to help you!

Accelerating return on investment

Web-based Resources
-

MathWorks home page

MATLAB Central

General Services
-

Technical Support
Training
Seminars
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Focused Services
-

Evaluations
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210

Wrap Up and Q & A

More information

Contact us for more information:

Per-Johan.Wiklund@mathworks.com
Jonas.Rutstrom@mathworks.com

211

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Please complete and return seminar survey forms

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212