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Design and Verification8

This document describes the design and verification of a nine port network router. The router uses Verilog and has one input port and eight output ports. It routes incoming packets to the appropriate output port based on the destination address in the packet header. The router design consists of register blocks, a finite state machine controller, and an output block containing four FIFOs to store and send data packets. The router supports synchronous serial data transfer of variable length packets up to 8192 bytes in a fully static synchronous design that is technology independent and fully synthesizable.

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0% found this document useful (0 votes)
72 views5 pages

Design and Verification8

This document describes the design and verification of a nine port network router. The router uses Verilog and has one input port and eight output ports. It routes incoming packets to the appropriate output port based on the destination address in the packet header. The router design consists of register blocks, a finite state machine controller, and an output block containing four FIFOs to store and send data packets. The router supports synchronous serial data transfer of variable length packets up to 8192 bytes in a fully static synchronous design that is technology independent and fully synthesizable.

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Sam
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International Journal of Engineering Research and General Science Volume 2, Issue 3, April-May 2014

ISSN 2091-2730

Design and Verification of Nine port Network Router


G. Sri Lakshmi1, A Ganga Mani2
1

Assistant Professor, Department of Electronics and Communication Engineering, Pragathi Engineering College, Andhra Pradesh,
India

Research Scholar (M.Tech), Embedded Systems, Department of Electronics and Communication Engineering, Pragathi Engineering
College, Andhra Pradesh, India
Email- srilakshmi1853@gmail.com

ABSTRACT - The focus of this Paper is the design of Network Router and verifies the functionality of the eight port router for
network on chip using verilog qualifies the Design for Synthesis and implementation. This Design consists of Registers, FSM and
FIFOs. This Router design contains Eight output ports and one input port, it is packet based Protocol. Router drives the incoming
packet which comes from the input port to output ports based on the address contained in the packet.. The router has an active low
synchronous input resetn which resets the router. Thus the idea is borrowed from large scale multiprocessors and wide area network
domain and envisions on chip routers based network. This helps to understand how router is controlling the signals from source to
destination based on the header adders.
KEYWORDS: FIFO, FSM, Network-On-Chip, Register blocks,Router Simulation,verification plan

INTRODUCTION
System on chip (SOC) is a complex interconnection of various functional elements. It creates communication bottleneck in the gigabit
communication due to its bus based architecture. Thus there was need of system that explicit modularity and parallelism, network on
chip possess many such attractive properties and solve the problem of communication bottleneck. It basically works on the idea of
interconnection of cores using on chip network. The communication on network on chip is carried out by means of router, so for
implementing better NOC, the router should be efficiently design. This router supports four parallel connections at the same time. It
uses store and forward type of flow control and FSM Controller deterministic routing which improves the performance of router. The
switching mechanism used here is packet switching which is generally used on network on chip. In packet switching the data the data
transfers in the form of packets between cooperating routers and independent routing decision is taken. The store and forward flow
mechanism is best because it does not reserve channels and thus does not lead to idle physical channels. The arbiter is of rotating
priority scheme so that every channel once get chance to transfer its data. In this router both input and output buffering is used so that
congestion can be avoided at both sides. A router is a device that forwards data packets across computer networks. Routers perform
the data "traffic direction" functions on the Internet. A router is a microprocessor- controlled device that is connected to two or more
data lines from different networks. When a data packet comes in on one of the lines .The router reads the address information in the
packet to determine its ultimate destination. Then, using information in its routing table, it directs the packet to the next network on its
journey.
WHY WOULD I NEED A ROUTER?
For most home users, they may want to set-up a LAN (local Area Network) or WLAN (wireless LAN) and connect all computers to
the Internet without having to pay a full broadband subscription service to their ISP for each computer on the network. In many
instances, an ISP will allow you to use a router and connect multiple computers to a single Internet connection and pay a nominal fee
for each additional computer sharing the connection. This is when home users will want to look at smaller routers, often called
broadband routers that enable two or more computers to share an Internet connection. Within a business or organization, you may
need to connect multiple computers to the Internet, but also want to connect multiple private networks not all routers are created equal
since their job will differ slightly from network to network. Additionally, you may look at a piece of hardware and not even realize it
is a router.
What defines a router is not its shape, color, size or manufacturer, but its job function of routing data packets between computers. A
cable modem, which routes data between your PC and your ISP can be considered as a router. In its most basic form, a router could
simply be one of two computers running the Windows 98 (or higher) operating system connected together using ICS (Internet
Connection Sharing). In this scenario, the computer that is connected to the Internet is acting as the router for the second computer to
obtain its Internet connection. Going a step up from ICS, we have a category of hardware routers that are used to perform the same
basic task as ICS, albeit with more features and functions often called broadband or Internet connection sharing routers, these routers
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International Journal of Engineering Research and General Science Volume 2, Issue 3, April-May 2014
ISSN 2091-2730

allow you to share one Internet connection with multiple computers. Broadband or ICS routers will look a bit different depending on
the manufacturer or brand, but wired routers are generally a small box-shaped hardware device with ports on the front or back into
which you will plug each computer along with a port to plug in your broadband modem. These connection ports allow the router to do
its job of routing the data packets between each of the computers and the data going to and from the Internet. These routers also
support NAT (network address translation), which allows all of your computers to share a single IP address on the Internet.
ROUTER DESIGN PRINCIPLES
Given the strict contest deadline and the short implementation window we adopted a set of design principles to spend the available
time as efficiently as possible. This document provides specifications for the Router is a packet based protocol. Router drives the
incoming packet which comes from the input port to output ports based on the address contained in the packet. The router is a
Network Router has a one input port from which the packet enters. It has Eight output ports where the packet is driven out. Packet
contains 3 parts. They are Header, data and frame check sequence. Packet width is 16 bits and the length of the packet can be between
1 byte to 8192 bytes. Packet header contains three fields DA and length. Destination address (DA) of the packet is of 16 bits. The
switch drives the packet to respective ports based on this destination address of the packets. Each output port has 16-bit unique port
address. If the destination address of the packet matches the port address, then switch drives the packet to the output port, Length of
the data is of 16 bits and from 0 to 8191. Length is measured in terms of bytes. Data should be in terms of bytes and can take anything.
Frame check sequence contains the security check of the packet. It is calculated over the header and data. The communication on
network on chip is carried out by means of router, so for implementing better NOC, the router should be efficiently design. This router
supports four parallel connections at the same time. It uses store and forward type of flow control and FSM Controller deterministic
routing which improves the performance of router. The switching mechanism used here is packet switching which is generally used on
network on chip. In packet switching the data the data transfers in the form of packets between co-operating routers and Independent
routing decision is taken. The store and forward flow mechanism is best because it does not reserve channels and thus does not lead to
idle physical channels. The arbiter is of rotating priority scheme so that every channel once get chance to transfer its data. In this
router both input and output buffering is used so that congestion can be avoided at both sides.
Features
Full duplex synchronous serial data transfer
Variable length of transfer word up to 8192 bytes.
HEADER is the first data transfer.
Rx and Tx on both rising or falling
Fully static synchronous design with one clock domain
Technology independent VERILOG
Fully synthesizable.
ROUTER is a Synchronous protocol. The clock signal is provided by the master to provide synchronization. The clock signal controls
when data can change and when it is valid for reading. Since ROUTER is synchronous, it has a clock pulse along with the data. RS232 and other asynchronous protocols do not use a clock pulse, but the data must be timed very accurately.

OPERATION
The Nine Port Router Design is done by using of the three blocks. The blocks are 16-Bit Register, Router Controller and output block.
The router controller is design by using FSM design and the output block consists of four FIFOs combined together. The FIFOs store
data packets and when you want to send data that time the data will read from the FIFOs. In this router design has Eight outputs i.e.
16-Bit size and one 16-bit data port. It is used to drive the data into router. we are using the global clock, reset signals, error signal and
suspended data signals are the outputs of the router. The FSM controller gives the error and SUSPENDED_DATA_IN signals. These
functions are discussed clearly in below FSM description. The ROUTER can operate with a single master device and with one or more
slave devices. If a single slave device is used, the RE (read enable) pin may be fixed to logic low if the slave permits it. Some slaves
require the falling edge (HIGHLOW transition) of the slave select to initiate an action such as the mobile operators, which starts
conversion on said transition. With multiple slave devices, an independent RE signal is required from the master for each slave device.

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International Journal of Engineering Research and General Science Volume 2, Issue 3, April-May 2014
ISSN 2091-2730

FIGURES

Figure 1: Block Diagram of Nine Port Router

Figure 2: Internal Structure of Nine Port Router

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International Journal of Engineering Research and General Science Volume 2, Issue 3, April-May 2014
ISSN 2091-2730

Figure 3: Simulation of FSM Controller

Figure 4: Simulation of Router


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International Journal of Engineering Research and General Science Volume 2, Issue 3, April-May 2014
ISSN 2091-2730

APPLICATIONS
When multiple routers are used in interconnected networks, the routers exchange information about destination addresses, using a
dynamic routing protocol. Each router builds up a table listing the preferred routes between any two systems on the interconnected
networks. A router has interfaces for different physical types of network connections, (such as copper cables, fiber optic, or wireless
transmission). It also contains firmware for different networking protocol standards. Each network interface uses this specialized
computer software to enable data packets to be forwarded from one protocol transmission system to another. Routers may also be used
to connect two or more logical groups of computer devices known as subnets, each with a different sub-network address. The subnet
addresses recorded in the router do not necessarily to map directly to the physical interface connections.
Eda Tools And Methodologies
HVL: System VERILOG.
HDL:VERILOG
Device :Sparatan 3e
EDA Tools: MODELSIM,XILINX ISEE
CONCLUSION
I have designed network ROUTER and I have verified the functionality of the ROUTER with VERILOG which has one input and
eight output ports with each 16-bit observed its functional of ROUTER.For design we had verified functionality of router by giving
different test cases to different FIFOs based on header address of the packet.

REFERENCES:
[1]D.Chiou,MEMOCODE2011Hardware/SoftwareCoDesignContest,https://ramp.ece.utexas.edu/redmine/
Attachments/
DesignContest.pdf
[2] Blue spec Inc, http://www.bluespec.com
[3]Xilinx,ML605HardwareUserGuide,http://www.xilinx.com/support/documentation/boardsand its/ug534.pdf
[4]Xilinx,LogiCOREIPProcessor Local Bus (PLB) v4.6,http://www.xilinx.com/support/documentation/ip documentation/plb
v46.pdf
[5] Application Note: Using the Router Interface to Communicate Motorola, ANN91/D Rev. 1, 01/2001.
[6] Cisco Router OSPF: Design& Implementation Guide, Publisher: McGraw-Hill
[7] Nortel Secure Router 4134, Nortel Networks Pvt. Ltd.
[8] LRM, IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language IEEE STD
1364-1995.
Books:
[9]. Chris Spears SYSTEMVERILOG FOR VERIFICATION, Publisher: Springer.
[10]. Bhaskar. J, A Verilog HDL Primer,

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