SST26VF064B / SST26VF064BA

2.5V/3.0V 64 Mbit Serial Quad I/O (SQI) Flash Memory

Features
Single Voltage Read and Write Operations
- 2.7-3.6V or 2.3-3.6V
Serial Interface Architecture
- Nibble-wide multiplexed I/Os with SPI-like serial
command structure
- Mode 0 and Mode 3
- x1/x2/x4 Serial Peripheral Interface (SPI) Protocol
High Speed Clock Frequency
- 2.7-3.6V: 104 MHz max
- 2.3-3.6V: 80 MHz max
Burst Modes
- Continuous linear burst
- 8/16/32/64 Byte linear burst with wrap-around
Superior Reliability
- Endurance: 100,000 Cycles (min)
- Greater than 100 years Data Retention
Low Power Consumption:
- Active Read current: 15 mA (typical @ 104 MHz)
- Standby Current: 15 A (typical)
Fast Erase Time
- Sector/Block Erase: 18 ms (typ), 25ms (max)
- Chip Erase: 35 ms (typ), 50 ms (max)
Page-Program
- 256 Bytes per page in x1 or x4 mode
End-of-Write Detection
- Software polling the BUSY bit in status register
Flexible Erase Capability
- Uniform 4 KByte sectors
- Four 8 KByte top and bottom parameter
overlay blocks
- One 32 KByte top and bottom overlay block
- Uniform 64 KByte overlay blocks
Write-Suspend
- Suspend Program or Erase operation to access
another block/sector
Software Reset (RST) mode
Software Protection
- Individual-Block Write Protection with permanent
lock-down capability
- 64 KByte blocks, two 32 KByte blocks, and
eight 8 KByte parameter blocks
- Read Protection on top and bottom 8 KByte
parameter blocks

2015 Microchip Technology Inc.

Security ID
- One-Time Programmable (OTP) 2 KByte, Secure ID
- 64 bit unique, factory pre-programmed identifier
- User-programmable area
Temperature Range
- Industrial: -40C to +85C
- Extended: -40C to +105C
Packages Available
- 8-contact WDFN (6mm x 5mm)
- 8-contact WDFN (6mm x 8 mm)
- 8-lead SOIJ (5.28 mm)
- 16-lead SOIC (7.50 mm)
- 24-ball TBGA (6mm x 8mm)
All devices are RoHS compliant

Product Description
The Serial Quad I/O (SQI) family of flash-memory
devices features a six-wire, 4-bit I/O interface that
allows for low-power, high-performance operation in a
low pin-count package. SST26VF064B/064BA also
support full command-set compatibility to traditional
Serial Peripheral Interface (SPI) protocol. System
designs using SQI flash devices occupy less board
space and ultimately lower system costs.
All members of the 26 Series, SQI family are manufactured with proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thickoxide tunneling injector attain better reliability and manufacturability compared with alternate approaches.
SST26VF064B/064BA significantly improve performance and reliability, while lowering power consumption. These devices write (Program or Erase) with a
single power supply of 2.3-3.6V. The total energy consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range,
the SuperFlash technology uses less current to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is
less than alternative flash memory technologies.
SST26VF064B/064BA are offered in 8-contact WDFN
(6 mm x 5 mm or 6mm x 8mm), 8-lead SOIJ (5.28 mm),
16-lead SOIC (7.50 mm), and 24-ball TBGA. See Figure 2-2 for pin assignments.
Two configurations are available upon order.
SST26VF064B default at power-up has the WP# and
HOLD# pins enabled, and the SIO2 and SIO3 pins disabled,
to
initiate
SPI-protocol
operations.

DS20005119G-page 1

SST26VF064B / SST26VF064BA
SST26VF064BA default at power-up has the WP# and
HOLD# pins disabled, and the SIO2 and SIO3 pins
enabled, to initiate Quad I/O operations. See I/O Configuration (IOC) on page 12 for more information about
configuring WP#/HOLD# and SIO3/SIO4 pins

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Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS20005119G-page 2

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
1.0

BLOCK DIAGRAM

FIGURE 1-1:

FUNCTIONAL BLOCK DIAGRAM

OTP

Address
Buffers
and
Latches

X - Decoder

SuperFlash
Memory

Y - Decoder

Page Buffer,
I/O Buffers
and
Data Latches

Control Logic

Serial Interface

WP# HOLD# SCK

CE#

SIO [3:0]
25119 B1.0

2015 Microchip Technology Inc.

DS20005119G-page 3

SST26VF064B / SST26VF064BA
2.0

PIN DESCRIPTION

FIGURE 2-1:

PIN DESCRIPTION FOR 8-LEAD SOIJ

CE#

VDD

SO/SIO1

HOLD/SIO3

Top View
WP#/SIO2

SCK

VSS

SI/SIO0
25119 08-soic S2A P1.0

FIGURE 2-2:

PIN DESCRIPTION FOR 8-CONTACT WDFN

CE#

SO/SIO1

VDD

HOLD/SIO3

Top View
WP#/SIO2

SCK

VSS

SI/SIO0
25119 08-wson QA P1.0

FIGURE 2-3:

PIN DESCRIPTION FOR 16-LEAD SOIC

SCK

HOLD#/SIO3

SI/SIO0

VDD
NC

Top View

NC

NC

NC

NC

NC

NC

NC

CE#

VSS

SO/SIO1

WP#/SIO2
16-SOIC P1.0

DS20005119G-page 4

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
FIGURE 2-4:

PIN DESCRIPTION FOR 24-BALL TBGA

Top View
4
NC

NC

SI/
SIO0

NC

NC

CE#

S0/
SIO1

NC

NC

NC

NC

NC

NC

NC

NC

VDD

NC

VSS

NC

NC

SCK

NC

WP#/ HOLD#/
SIO2 SIO3

3
2

TABLE 2-1:

T4D-P1.0

PIN DESCRIPTION

Symbol

Pin Name

Functions

SCK

Serial Clock

To provide the timing of the serial interface.

Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.

SIO[3:0]

Serial Data
Input/Output

To transfer commands, addresses, or data serially into the device or data out of
the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The Enable Quad I/O (EQIO)
command instruction configures these pins for Quad I/O mode.

SI

Serial Data Input

for SPI mode

To transfer commands, addresses or data serially into the device. Inputs are
latched on the rising edge of the serial clock. SI is the default state after a power
on reset.

SO

Serial Data Output

for SPI mode

To transfer data serially out of the device. Data is shifted out on the falling edge
of the serial clock. SO is the default state after a power on reset.

CE#

Chip Enable

The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence; or in the case of Write operations,
for the command/data input sequence.

WP#

Write Protect

The WP# is used in conjunction with the WPEN and IOC bits in the Configuration register to prohibit write operations to the Block-Protection register. This pin
only works in SPI, single-bit and dual-bit Read mode.

HOLD#

Hold

Temporarily stops serial communication with the SPI Flash memory while the
device is selected. This pin only works in SPI, single-bit and dual-bit Read mode
and must be tied high when not in use.

VDD

Power Supply

To provide power supply voltage.

VSS

Ground

2015 Microchip Technology Inc.

DS20005119G-page 5

SST26VF064B / SST26VF064BA
3.0

MEMORY ORGANIZATION

The SST26VF064B/064BA SQI memory array is organized in uniform, 4 KByte erasable sectors with the following erasable blocks: eight 8 KByte parameter, two
32 KByte overlay, and one-hundred twenty-six
64 KByte overlay blocks. See Figure 3-1.

FIGURE 3-1:

MEMORY MAP
Top of Memory Block
8 KByte
8 KByte
8 KByte
8 KByte
32 KByte

...

64 KByte

2 Sectors for 8 KByte blocks

8 Sectors for 32 KByte blocks
16 Sectors for 64 KByte blocks

64 KByte

...

4 KByte
4 KByte

4 KByte
4 KByte

64 KByte

32 KByte
8 KByte
8 KByte
8 KByte
8 KByte

Bottom of Memory Block

25119 F41.0

DS20005119G-page 6

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
4.0

DEVICE OPERATION

SST26VF064B/064BA support both Serial Peripheral

Interface (SPI) bus protocol and a 4-bit multiplexed SQI
bus protocol. To provide backward compatibility to traditional SPI Serial Flash devices, the devices initial
state after a power-on reset is SPI mode which supports multi-I/O (x1/x2/x4) Read/Write commands. A
command instruction configures the device to SQI
mode. The dataflow in the SQI mode is similar to the
SPI mode, except it uses four multiplexed I/O signals
for command, address, and data sequence.

bus master is in stand-by mode and no data is being

transferred. The SCK signal is low for Mode 0 and SCK
signal is high for Mode 3. For both modes, the Serial
Data I/O (SIO[3:0]) is sampled at the rising edge of the
SCK clock signal for input, and driven after the falling
edge of the SCK clock signal for output. The traditional
SPI protocol uses separate input (SI) and output (SO)
data signals as shown in Figure 4-1. The SQI protocol
uses four multiplexed signals, SIO[3:0], for both data in
and data out, as shown in Figure 4-2. This means the
SQI protocol quadruples the traditional bus transfer
speed at the same clock frequency, without the need
for more pins on the package.

SQI Flash Memory supports both Mode 0 (0,0) and

Mode 3 (1,1) bus operations. The difference between
the two modes is the state of the SCK signal when the

FIGURE 4-1:

SPI PROTOCOL (TRADITIONAL 25 SERIES SPI DEVICE)

CE#
SCK

MODE 3

MODE 3

MODE 0

MODE 0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SI

MSB

SO

HIGH IMPEDANCE

DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB

FIGURE 4-2:

25119 F03.0

SQI SERIAL QUAD I/O PROTOCOL

CE#
MODE 3

MODE 3

CLK
MODE 0

SIO(3:0)

MODE 0

C1 C0

A5

A4

A3

A2

A1

A0

H0

L0

H1

L1

H2

L2

H3

L3

MSB
25119 F04.0

4.1

Device Protection

SST26VF064B/064BA offer a flexible memory protection scheme that allows the protection state of each
individual block to be controlled separately. In addition,
the Write-Protection Lock-Down register prevents any
change of the lock status during device operation. To
avoid inadvertent writes during power-up, the device is
write-protected by default after a power-on reset cycle.
A Global Block-Protection Unlock command offers a
single command cycle that unlocks the entire memory
array for faster manufacturing throughput.
For extra protection, there is an additional non-volatile
register that can permanently write-protect the BlockProtection register bits for each individual block. Each
of the corresponding lock-down bits are one time programmable (OTP)once written, they cannot be
erased. Data that had been previously programmed
into these blocks cannot be altered by programming or
erase and is not reversible

2015 Microchip Technology Inc.

4.1.1

INDIVIDUAL BLOCK PROTECTION

SST26VF064B/064BA have a Block-Protection register which provides a software mechanism to write-lock

the individual memory blocks and write-lock, and/or
read-lock, the individual parameter blocks. The BlockProtection register is 144 bits wide: two bits each for the
eight 8 KByte parameter blocks (write-lock and readlock), and one bit each for the remaining 32 KByte and
64 KByte overlay blocks (write-lock). See Table 5-6 for
address range protected per register bit.
Each bit in the Block-Protection register (BPR) can be
written to a 1 (protected) or 0 (unprotected). For the
parameter blocks, the most significant bit is for readlock, and the least significant bit is for write-lock. Readlocking the parameter blocks provides additional security for sensitive data after retrieval (e.g., after initial
boot). If a block is read-locked all reads to the block
return data 00H.

DS20005119G-page 7

SST26VF064B / SST26VF064BA
The Write Block-Protection Register command is a
two-cycle command which requires that Write-Enable
(WREN) is executed prior to the Write Block-Protection
Register command. The Global Block-Protection
Unlock command clears all write protection bits in the
Block-Protection register.

4.1.2

WRITE-PROTECTION LOCK-DOWN
(VOLATILE)

To prevent changes to the Block-Protection register,

use the Lock-Down Block-Protection Register (LBPR)
command to enable Write-Protection Lock-Down.
Once Write-Protection Lock-Down is enabled, the
Block-Protection register can not be changed. To avoid
inadvertent lock down, the WREN command must be
executed prior to the LBPR command.
To reset Write-Protection Lock-Down, performing a power
cycle on the device is required. The Write-Protection
Lock-Down status may be read from the Status register.

4.1.3

WRITE-LOCK LOCK-DOWN (NONVOLATILE)

The non-Volatile Write-Lock Lock-Down register is an

alternate register that permanently prevents changes
to the block-protect bits. The non-Volatile Write-Lock
Lock-Down register (nVWLDR) is 136 bits wide per
device: one bit each for the eight 8-KByte parameter
blocks, and one bit each for the remaining 32 KByte
and 64 KByte overlay blocks. See Table 5-6 for address
range protected per register bit.
Writing 1 to any or all of the nVWLDR bits disables the
change mechanism for the corresponding Write-Lock
bit in the BPR, and permanently sets this bit to a 1
(protected) state. After this change, both bits will be set
to 1, regardless of the data entered in subsequent
writes to either the nVWLDR or the BPR. Subsequent
writes to the nVWLDR can only alter available locations
that have not been previously written to a 1. This
method provides write-protection for the corresponding
memory-array block by protecting it from future program or erase operations.

DS20005119G-page 8

Writing a 0 in any location in the nVWLDR has no

effect on either the nVWLDR or the corresponding
Write-Lock bit in the BPR.
Note that if the Block-Protection register had been previously locked down, see Write-Protection Lock-Down
(Volatile), the device must be power cycled before
using the nVWLDR. If the Block-Protection register is
locked down and the Write nVWLDR command is
accessed, the command will be ignored.

4.2

Hardware Write Protection

The hardware Write Protection pin (WP#) is used in

conjunction with the WPEN and IOC bits in the configuration register to prohibit write operations to the BlockProtection and Configuration registers. The WP# pin
function only works in SPI single-bit and dual-bit read
mode when the IOC bit in the configuration register is
set to 0.
The WP# pin function is disabled when the WPEN bit
in the configuration register is 0. This allows installation of the SST26VF064B/064BA in a system with a
grounded WP# pin while still enabling Write to the
Block-Protection register. The Lock-Down function of
the Block-Protection Register supersedes the WP# pin,
see Table 4-1 for Write Protection Lock-Down states.
The factory default setting at power-up of the WPEN bit
is 0, disabling the Write Protect function of the WP#
after power-up. WPEN is a non-volatile bit; once the bit
is set to 1, the Write Protect function of the WP# pin
continues to be enabled after power-up. The WP# pin
only protects the Block-Protection Register and Configuration Register from changes. Therefore, if the WP#
pin is set to low before or after a Program or Erase
command, or while an internal Write is in progress, it
will have no effect on the Write command.
The IOC bit takes priority over the WPEN bit in the configuration register. When the IOC bit is 1, the function
of the WP# pin is disabled and the WPEN bit serves no
function. When the IOC bit is 0 and WPEN is 1, setting the WP# pin active low prohibits Write operations
to the Block Protection Register.

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 4-1:

WRITE PROTECTION LOCK-DOWN STATES

WP#

IOC

WPEN

WPLD

Not Allowed

Protected

Not Allowed

Writable

Not Allowed

Protected

01

02

Allowed

Writable

Not Allowed

Writable

Allowed

Writable

Not Allowed

Writable

13

Allowed

Writable

Execute WBPR Instruction

Configuration Register

1. Default at power-up Register settings for SST26VF064B

2. Factory default setting is 0. This is a non-volatile bit; default at power-up is the value set prior to power-down.
3. Default at power-up Register settings for SST26VF064BA

4.3

Security ID

SST26VF064B/064BA offer a 2 KByte Security ID (Sec

ID) feature. The Security ID space is divided into two
parts one factory-programmed, 64-bit segment and
one user-programmable segment. The factory-programmed segment is programmed during manufacturing with a unique number and cannot be changed. The
user-programmable segment is left unprogrammed for
the customer to program as desired.
Use the Program Security ID (PSID) command to program the Security ID using the address shown in Table
5-5. The Security ID can be locked using the Lockout
Security ID (LSID) command. This prevents any future
write operations to the Security ID.
The factory-programmed portion of the Security ID
cant be programmed by the user; neither the factoryprogrammed nor user-programmable areas can be
erased.

4.4

Hold Operation

The HOLD# pin pauses active serial sequences without resetting the clocking sequence. This pin is active
after every power up and only operates during SPI
single-bit and dual-bit modes. Two factory configurations are available: SST26VF064B ships with the IOC

FIGURE 4-3:

bit set to 0 and the HOLD# pin function enabled;

SST26VF064BA ships with the IOC bit set to 1 and the
HOLD# pin function disabled. The HOLD# pin is always
disabled in SQI mode and only works in SPI single-bit
and dual-bit read mode.
To activate the Hold mode, CE# must be in active low
state. The Hold mode begins when the SCK active low
state coincides with the falling edge of the HOLD# signal. The Hold mode ends when the HOLD# signals rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the
active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active
low state, then the device exits Hold mode when the
SCK next reaches the active low state. See Figure 4-3.
Once the device enters Hold mode, SO will be in high
impedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, it
resets the internal logic of the device. As long as
HOLD# signal is low, the memory remains in the Hold
condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be
driven active low.

HOLD CONDITION WAVEFORM.

SCK

HOLD#
Active

Hold

Active

Hold

Active
25119 F46.0

2015 Microchip Technology Inc.

DS20005119G-page 9

SST26VF064B / SST26VF064BA
4.5

Status Register

The Status register is a read-only register that provides

the following status information: whether the flash
memory array is available for any Read or Write operation, if the device is write-enabled, whether an erase
or program operation is suspended, and if the Block-

TABLE 4-2:

Protection register and/or Security ID are locked down.

During an internal Erase or Program operation, the Status register may be read to determine the completion of
an operation in progress. Table 4-2 describes the function of each bit in the Status register.

STATUS REGISTER
Default at
Power-up

Read/Write (R/
W)

Write operation status

1 = Internal Write operation is in progress
0 = No internal Write operation is in progress

WEL

Write-Enable Latch status

1 = Device is write-enabled
0 = Device is not write-enabled

WSE

Write Suspend-Erase status

1 = Erase suspended
0 = Erase is not suspended

WSP

Write Suspend-Program status

1 = Program suspended
0 = Program is not suspended

WPLD

Write Protection Lock-Down status

1 = Write Protection Lock-Down enabled
0 = Write Protection Lock-Down disabled

SEC1

Security ID status
1 = Security ID space locked
0 = Security ID space not locked

01

Bit

Name

Function

BUSY

RES

Reserved for future use

BUSY

Write operation status

1 = Internal Write operation is in progress
0 = No internal Write operation is in progress

1. The Security ID status will always be 1 at power-up after a successful execution of the Lockout Security ID instruction, otherwise default at power-up is 0.

DS20005119G-page 10

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
4.5.1

WRITE-ENABLE LATCH (WEL)

The Write-Enable Latch (WEL) bit indicates the status

of the internal memorys Write-Enable Latch. If the
WEL bit is set to 1, the device is write enabled. If the
bit is set to 0 (reset), the device is not write enabled
and does not accept any memory Program or Erase,
Protection Register Write, or Lock-Down commands.
The Write-Enable Latch bit is automatically reset under
the following conditions:

Power-up
Reset
Write-Disable (WRDI) instruction
Page-Program instruction completion
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Block-Protection register instruction
Lock-Down Block-Protection register instruction
Program Security ID instruction completion
Lockout Security ID instruction completion
Write-Suspend instruction
SPI Quad Page program instruction completion
Write Status Register

4.5.2

WRITE SUSPEND ERASE STATUS

(WSE)

The Write Suspend-Erase status (WSE) indicates

when an Erase operation has been suspended. The
WSE bit is 1 after the host issues a suspend command
during an Erase operation. Once the suspended Erase
resumes, the WSE bit is reset to 0.

TABLE 4-3:
Bit

4.5.3

WRITE SUSPEND PROGRAM

STATUS (WSP)

The Write Suspend-Program status (WSP) bit indicates

when a Program operation has been suspended. The
WSP is 1 after the host issues a suspend command
during the Program operation. Once the suspended
Program resumes, the WSP bit is reset to 0.

4.5.4

WRITE PROTECTION LOCK-DOWN

STATUS (WPLD)

The Write Protection Lock-Down status (WPLD) bit

indicates when the Block-Protection register is lockeddown to prevent changes to the protection settings.
The WPLD is 1 after the host issues a Lock-Down
Block-Protection command. After a power cycle, the
WPLD bit is reset to 0.

4.5.5

SECURITY ID STATUS (SEC)

The Security ID Status (SEC) bit indicates when the

Security ID space is locked to prevent a Write command. The SEC is 1 after the host issues a Lockout
SID command. Once the host issues a Lockout SID
command, the SEC bit can never be reset to 0.

4.5.6

BUSY

The Busy bit determines whether there is an internal

Erase or Program operation in progress. If the BUSY
bit is 1, the device is busy with an internal Erase or
Program operation. If the bit is 0, no Erase or Program
operation is in progress.

4.5.7

CONFIGURATION REGISTER

The Configuration register is a Read/Write register that

stores a variety of configuration information. See Table
4-3 for the function of each bit in the register.

CONFIGURATION REGISTER

Name

Function

Default at Power-up

Read/Write (R/W)

RES

Reserved

IOC

I/O Configuration for SPI Mode

1 = WP# and HOLD# pins disabled
0 = WP# and HOLD# pins enabled

01

R/W

RES

Reserved

BPNV

Block-Protection Volatility State

1 = No memory block has been permanently locked
0 = Any block has been permanently locked

RES

Reserved

RES

Reserved

RES

Reserved

WPEN

Write-Protection Pin (WP#) Enable

1 = WP# enabled
0 = WP# disabled

02

R/W

0
1
2
3

1. SST26VF064B default at Power-up is 0

SST26VF064BA default at Power-up is 1
2. Factory default setting. This is a non-volatile bit; default at power-up will be the setting prior to power-down.

2015 Microchip Technology Inc.

DS20005119G-page 11

SST26VF064B / SST26VF064BA
4.5.8

I/O CONFIGURATION (IOC)

The I/O Configuration (IOC) bit re-configures the I/O

pins. The IOC bit is set by writing a 1 to Bit 1 of the
Configuration register. When IOC bit is 0 the WP# pin
and HOLD# pin are enabled (SPI or Dual Configuration
setup). When IOC bit is set to 1 the SIO2 pin and SIO3
pin are enabled (SPI Quad I/O Configuration setup).
The IOC bit must be set to 1 before issuing the following SPI commands: SQOR (6BH), SQIOR (EBH),
RBSPI (ECH), and SPI Quad page program (32H).
Without setting the IOC bit to 1, those SPI commands
are not valid. The I/O configuration bit does not apply
when in SQI mode. The default at power-up for
SST26VF064B is 0 and for SST26VF064BA is 1.

4.5.9

BLOCK-PROTECTION VOLATILITY
STATE (BPNV)

The Block-Protection Volatility State bit indicates

whether any block has been permanently locked with
the nVWLDR. When no bits in the nVWLDR have been
set, the BPNV is 1; this is the default state from the
factory. When one or more bits in the nVWLDR are set
to 1, the BPNV bit will also be 0 from that point forward, even after power-up.

4.5.10

WRITE-PROTECT ENABLE (WPEN)

The Write-Protect Enable (WPEN) bit is a non-volatile

bit that enables the WP# pin.
The Write-Protect (WP#) pin and the Write-Protect
Enable (WPEN) bit control the programmable hardware write-protect feature. Setting the WP# pin to low,
and the WPEN bit to 1, enables Hardware write-protection. To disable Hardware write protection, set either
the WP# pin to high or the WPEN bit to 0. There is
latency associated with writing to the WPEN bit. Poll
the BUSY bit in the Status register, or wait TWPEN, for
the completion of the internal, self-timed Write operation. When the chip is hardware write protected, only
Write operations to Block-Protection and Configuration
registers are disabled. See Hardware Write Protection on page 8 and Table 4-1 on page 9 for more information about the functionality of the WPEN bit.

DS20005119G-page 12

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.0

INSTRUCTIONS

Instructions are used to read, write (erase and program), and configure the SST26VF064B/064BA. The
complete list of the instructions is provided in Table 5-1.

TABLE 5-1:

DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

Instruction Description

Mode

Command
Cycle1

SPI

SQI

Address
Cycle(s)2, 3

Dummy
Cycle(s)3

Data
Cycle(s)3

00H

Max
Freq4

Configuration
NOP

No Operation

RSTEN

Reset Enable

66H

RST5

Reset Memory

99H

1 to

1 to

1 to

1 to

1 to

1 to

1 to

EQIO

Enable Quad I/O

38H

RSTQIO6

Reset Quad I/O

FFH

RDSR

Read Status Register

05H

WRSR

Write Status Register

01H

RDCR

Read Configuration
Register

35H

104 MHz/
80 MHz

Read
Read

Read Memory

03H

HighSpeed
Read

Read Memory at Higher

Speed

0BH

SQOR7

SPI Quad Output Read

6BH

1 to

SQIOR8

SPI Quad I/O Read

EBH

1 to

SDOR9

SPI Dual Output Read

3BH

1 to

SDIOR10

SPI Dual I/O Read

BBH

SB

Set Burst Length

C0H

X
X

1 to

n to

n to

3 to

3 to

1 to

RBSQI

SQI Read Burst with Wrap

0CH

RBSPI8

SPI Read Burst with Wrap

ECH

JEDEC-ID JEDEC-ID Read

9FH

Quad J-ID Quad I/O J-ID Read

AFH

SFDP

Serial Flash Discoverable

Parameters

5AH

WREN

Write Enable

06H

WRDI

Write Disable

04H

11

SE

Erase 4 KBytes of Memory

Array

20H

BE12

Erase 64, 32 or 8 KBytes of

Memory Array

D8H

CE

Erase Full Array

C7H

PP

Page Program

02H

1 to 256

32H

1 to 256

40 MHz

104 MHz/
80 MHz

Identification
X

104 MHz/
80 MHz

Write

SPI Quad SQI Quad Page

PP7
Program

2015 Microchip Technology Inc.

104 MHz/
80 MHz

DS20005119G-page 13

SST26VF064B / SST26VF064BA
TABLE 5-1:

DEVICE OPERATION INSTRUCTIONS FOR SST26VF064B/064BA

Instruction Description

Mode

Command
Cycle1

SPI

SQI

Address
Cycle(s)2, 3

Dummy
Cycle(s)3

Data
Cycle(s)3

Max
Freq4
104 MHz/
80 MHz

WRSU

Suspends Program/Erase

B0H

WRRE

Resumes Program/Erase

30H

RBPR

Read Block-Protection
Register

72H

1 to18

1 to18

WBPR

Write Block-Protection
Register

42H

1 to 18

LBPR

Lock Down
Block-Protection
Register

8DH

nVWLDR

non-Volatile Write LockDown Register

E8H

1 to 18

ULBPR

Global Block Protection

Unlock

98H

RSID

Read Security ID

88H

Protection

1 to 2048

1 to 2048

PSID

Program User
Security ID area

A5H

1 to 256

LSID

Lockout Security ID Programming

85H

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

104 MHz/
80 MHz

Command cycle is two clock periods in SQI mode and eight clock periods in SPI mode.
Address bits above the most significant bit of each density can be VIL or VIH.
Address, Dummy/Mode bits, and Data cycles are two clock periods in SQI and eight clock periods in SPI mode.
The max frequency for all instructions is up to 104 MHz from 2.7-3.6V and up to 80 MHz from 2.3-3.6V unless otherwise noted.
RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
Device accepts eight-clock command in SPI mode, or two-clock command in SQI mode.
Data cycles are two clock periods. IOC bit must be set to 1 before issuing the command.
Address, Dummy/Mode bits, and data cycles are two clock periods. IOC bit must be set to 1 before issuing the command.
Data cycles are four clock periods.
Address, Dummy/Mode bits, and Data cycles are four clock periods.
Sector Addresses: Use AMS - A12, remaining address are dont care, but must be set to VIL or VIH.
Blocks are 64 KByte, 32 KByte, or 8KByte, depending on location. Block Erase Address: AMS - A16 for 64 KByte; AMS - A15
for 32 KByte; AMS - A13 for 8 KByte. Remaining addresses are dont care, but must be set to VIL or VIH.

DS20005119G-page 14

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.1

No Operation (NOP)

The Reset operation requires the Reset-Enable command followed by the Reset command. Any command
other than the Reset command after the Reset-Enable
command will disable the Reset-Enable.

The No Operation command only cancels a Reset

Enable command. NOP has no impact on any other
command.

5.2

Once the Reset-Enable and Reset commands are successfully executed, the device returns to normal operation Read mode and then does the following: resets the
protocol to SPI mode, resets the burst length to 8
Bytes, clears all the bits, except for bit 4 (WPLD) and
bit 5 (SEC), in the Status register to their default states,
and clears bit 1 (IOC) in the configuration register to its
default state. A device reset during an active Program
or Erase operation aborts the operation, which can
cause the data of the targeted address range to be corrupted or lost. Depending on the prior operation, the
reset timing may vary. Recovery from a Write operation
requires more latency time than recovery from other
operations. See Table 8-2 on page 49 for Rest timing
parameters.

Reset-Enable (RSTEN) and Reset

(RST)

The Reset operation is used as a system (software)

reset that puts the device in normal operating Ready
mode. This operation consists of two commands:
Reset-Enable (RSTEN) followed by Reset (RST).
To reset the SST26VF064B/064BA, the host drives
CE# low, sends the Reset-Enable command (66H),
and drives CE# high. Next, the host drives CE# low
again, sends the Reset command (99H), and drives
CE# high, see Figure 5-1.

FIGURE 5-1:

RESET SEQUENCE
TCPH
CE#
MODE 3

MODE 3

MODE 3

CLK
MODE 0

SIO(3:0)

MODE 0

MODE 0

C1 C0

C3 C2
25119 F05.0

Note: C[1:0] = 66H; C[3:2] = 99H

5.3

Read (40 MHz)

will automatically increment until the highest memory

address is reached. Once the highest memory address
is reached, the address pointer will automatically return
to the beginning (wrap-around) of the address space.

The Read instruction, 03H, is supported in SPI bus protocol only with clock frequencies up to 40 MHz. This
command is not supported in SQI bus protocol. The
device outputs the data starting from the specified
address location, then continuously streams the data
output through all addresses until terminated by a lowto-high transition on CE#. The internal address pointer

FIGURE 5-2:

Initiate the Read instruction by executing an 8-bit command, 03H, followed by address bits A[23:0]. CE# must
remain active low for the duration of the Read cycle.
See Figure 5-2 for Read Sequence.

READ SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

ADD.

03

SI

MSB

MSB
SO

15 16

23 24

31 32

39 40

47 48

55 56

63 64

70

MODE 0

HIGH IMPEDANCE

ADD.

ADD.
N
DOUT
MSB

2015 Microchip Technology Inc.

N+1
DOUT

N+2
DOUT

N+3
DOUT

N+4
DOUT
25119 F29.0

DS20005119G-page 15

SST26VF064B / SST26VF064BA
5.4

Enable Quad I/O (EQIO)

The Enable Quad I/O (EQIO) instruction, 38H, enables

the flash device for SQI bus operation. Upon completion of the instruction, all instructions thereafter are

FIGURE 5-3:

expected to be 4-bit multiplexed input/output (SQI

mode) until a power cycle or a Reset Quad I/O instruction is executed. See Figure 5-3.

ENABLE QUAD I/O SEQUENCE

CE#
MODE 3

SCK

MODE 0

SIO0

38

SIO[3:1]
25119 F43.0

Note: SIO[3:1] must be driven VIH

5.5

Reset Quad I/O (RSTQIO)

where it can accept new command instruction. An additional RSTQIO is required to reset the device to SPI
mode.

The Reset Quad I/O instruction, FFH, resets the device

to 1-bit SPI protocol operation or exits the Set Mode
configuration during a read sequence. This command
allows the flash device to return to the default I/O state
(SPI) without a power cycle, and executes in either 1bit or 4-bit mode. If the device is in the Set Mode configuration, while in SQI High-Speed Read mode, the
RSTQIO command will only return the device to a state

FIGURE 5-4:

To execute a Reset Quad I/O operation, the host drives

CE# low, sends the Reset Quad I/O command cycle
(FFH) then, drives CE# high. Execute the instruction in
either SPI (8 clocks) or SQI (2 clocks) command
cycles. For SPI, SIO[3:1] are dont care for this command, but should be driven to VIH or VIL. See Figures
5-4 and 5-5.

RESET QUAD I/O SEQUENCE (SPI)

CE#
MODE 3

SCK

MODE 0

FF

SIO0
SIO[3:1]

25119 F73.0

Note: SIO[3:1]

FIGURE 5-5:

RESET QUAD I/O SEQUENCE (SQI)

CE#
MODE 3

SCK
SIO(3:0)

MODE 0

25119 F74.0

DS20005119G-page 16

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.6

High-Speed Read

Initiate High-Speed Read by executing an 8-bit command, 0BH, followed by address bits A[23-0] and a
dummy byte. CE# must remain active low for the duration of the High-Speed Read cycle. See Figure 5-6 for
the High-Speed Read sequence for SPI bus protocol.

The High-Speed Read instruction, 0BH, is supported in

both SPI bus protocol and SQI protocol. This instruction
supports frequencies of up to 104 MHz from 2.7-3.6V
and up to 80 MHz from 2.3-3.6V.On power-up, the
device is set to use SPI.

FIGURE 5-6:

HIGH-SPEED READ SEQUENCE (SPI) (C[1:0] = 0BH)

CE#
MODE 3

0 1 2 3 4 5 6 7 8

15 16

23 24

31 32

39 40

47 48

55 56

63 64

80

71 72

SCK MODE 0

0B

SI/SIO0

ADD.

ADD.

ADD.

X
N
DOUT
MSB

HIGH IMPEDANCE

SO/SIO1

N+1
DOUT

N+2
DOUT

N+3
DOUT

N+4
DOUT
25119 F31.0

In SQI protocol, the host drives CE# low then send the
Read command cycle command, 0BH, followed by
three address cycles, a Set Mode Configuration cycle,
and two dummy cycles. Each cycle is two nibbles
(clocks) long, most significant nibble first.

mand, 0BH, and does not require the op-code to be

entered again. The host may initiate the next Read
cycle by driving CE# low, then sending the four-bits
input for address A[23:0], followed by the Set Mode
configuration bits M[7:0], and two dummy cycles. After
the two dummy cycles, the device outputs the data
starting from the specified address location. There are
no restrictions on address location access.

After the dummy cycles, the device outputs data on the

falling edge of the SCK signal starting from the specified address location. The device continually streams
data output through all addresses until terminated by a
low-to-high transition on CE#. The internal address
pointer automatically increments until the highest memory address is reached, at which point the address
pointer returns to address location 000000H. During
this operation, blocks that are Read-locked will output
data 00H.

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. While in
the Set Mode configuration, the RSTQIO command will
only return the device to a state where it can accept
new command instruction. An additional RSTQIO is
required to reset the device to SPI mode. See Figure 510 for the SPI Quad I/O Mode Read sequence when
M[7:0] = AXH.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SQI High-Speed Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another Read com-

FIGURE 5-7:

HIGH-SPEED READ SEQUENCE (SQI)

CE#
0

MODE 0 MSN

LSN

C0

C1

MODE 3

A5

A4

A3

A2

A1

A0

M1

M0

10

11

12

13

14

15

20

21

SCK
SIO(3:0)

Command

Address

Mode

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

Hx = High Data Nibble, Lx = Low Data Nibble C[1:0]=0BH

2015 Microchip Technology Inc.

Dummy

H0

L0

Data Byte 0

H8

L8

Data Byte 7
25119 F47.0

DS20005119G-page 17

SST26VF064B / SST26VF064BA
5.7

SPI Quad-Output Read

The SPI Quad-Output Read instruction supports frequencies of up to 104 MHz from 2.7-3.6V and up to 80
MHz from 2.3-3.6V. SST26VF064B requires the IOC bit
in the configuration register to be set to 1 prior to executing the command. Initiate SPI Quad-Output Read by
executing an 8-bit command, 6BH, followed by address
bits A[23-0] and a dummy byte. CE# must remain
active low for the duration of the SPI Quad Mode Read.
See Figure 5-8 for the SPI Quad Output Read
sequence.

FIGURE 5-8:

Following the dummy byte, the device outputs data

from SIO[3:0] starting from the specified address location. The device continually streams data output
through all addresses until terminated by a low-to-high
transition on CE#. The internal address pointer automatically increments until the highest memory address
is reached, at which point the address pointer returns
to the beginning of the address space.

SPI QUAD OUTPUT READ

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

15 16

23 24

31 32

39 40 41

MODE 0

SIO0

6BH
OP Code

A[23:16]

A[15:8]
Address

A[7:0]

b4 b0

b4 b0

Dummy

Data
Byte 0

Data
Byte N

SIO1

b5 b1

b5 b1

SIO2

b6 b2

b6 b2

SIO3

b7 b3

b7 b3

Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

DS20005119G-page 18

25119 F48.3

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.8

SPI Quad I/O Read

The SPI Quad I/O Read (SQIOR) instruction supports

frequencies of up to 104 MHz from 2.7-3.6V and up to
80 MHz from 2.3-3.6V. SST26VF064B requires the
IOC bit in the configuration register to be set to 1 prior
to executing the command. Initiate SQIOR by executing an 8-bit command, EBH. The device then switches
to 4-bit I/O mode for address bits A[23-0], followed by
the Set Mode configuration bits M[7:0], and two dummy
bytes.CE# must remain active low for the duration of
the SPI Quad I/O Read. See Figure 5-9 for the SPI
Quad I/O Read sequence.

The Set Mode Configuration bit M[7:0] indicates if the

next instruction cycle is another SPI Quad I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another Read command, EBH, and does not require the op-code to be
entered again. The host may set the next SQIOR cycle
by driving CE# low, then sending the four-bit wide input
for address A[23:0], followed by the Set Mode configuration bits M[7:0], and two dummy cycles. After the two
dummy cycles, the device outputs the data starting
from the specified address location. There are no
restrictions on address location access.

Following the dummy bytes, the device outputs data

from the specified address location. The device continually streams data output through all addresses until
terminated by a low-to-high transition on CE#. The
internal address pointer automatically increments until
the highest memory address is reached, at which point
the address pointer returns to the beginning of the
address space.

FIGURE 5-9:

When M[7:0] is any value other than AXH, the device

expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,
execute the Reset Quad I/O command, FFH. See Figure 5-10 for the SPI Quad I/O Mode Read sequence
when M[7:0] = AXH.

SPI QUAD I/O READ SEQUENCE

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

MODE 0

SIO0

EBH

A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0 b4 b0

SIO1

A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1 b5 b1

SIO2

A22 A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2 b6 b2

SIO3

A23 A19 A15 A11 A7 A3 M7 M3 X X X X b7 b3 b7 b3

MSN LSN

Address
Note: MSN= Most Significant Nibble, LSN = Least Significant Nibble

2015 Microchip Technology Inc.

Set
Mode

Dummy

Data Data
Byte 0 Byte 1
25119 F49.2

DS20005119G-page 19

SST26VF064B / SST26VF064BA
FIGURE 5-10:

BACK-TO-BACK SPI QUAD I/O READ SEQUENCES WHEN M[7:0] = AXH

CE#
0 1 2 3 4 5 6 7 8 9 10 11 12 13

SCK
SIO0

b4 b0 b4 b0

A20 A16 A12 A8 A4 A0 M4 M0 X X X X b4 b0

SIO1

b5 b1 b5 b1

A21 A17 A13 A9 A5 A1 M5 M1 X X X X b5 b1

SIO2

b6 b2 b6 b2

A22 A18 A14 A10 A6 A2 M6 M2 X X X X b6 b2

MSN LSN

SIO3

b7 b3 b7 b3

A23 A19 A15 A11 A7 A3 M7 M3 X X X X b7 b3

Data Data
Byte Byte
N+1
N

Set
Mode

Address

Dummy

Data
Byte 0
25119 F50.2

Note: MSN=

5.9

Set Burst

sends the Set Burst command cycle (C0H) and one

data cycle, then drives CE# high. After power-up or
reset, the burst length is set to eight Bytes (00H). See
Table 5-2 for burst length data and Figures 5-11 and 512 for the sequences.

The Set Burst command specifies the number of bytes

to be output during a Read Burst command before the
device wraps around. It supports both SPI and SQI protocols. To set the burst length the host drives CE# low,

TABLE 5-2:

BURST LENGTH DATA

Burst Length

High Nibble (H0)

Low Nibble (L0)

8 Bytes

0h

0h

16 Bytes

0h

1h

32 Bytes

0h

2h

64 Bytes

0h

3h

FIGURE 5-11:

SET BURST LENGTH SEQUENCE (SQI)

CE#
MODE 3

SCK
SIO(3:0)

MODE 0

C1 C0 H0 L0
MSN LSN
25119 F32.0

Note: MSN = Most Significant

Nibble, LSN = Least Significant Nibble, C[1:0]=C0H

DS20005119G-page 20

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
FIGURE 5-12:

SET BURST LENGTH SEQUENCE (SPI)

CE#
MODE 3

SCK
SIO0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

MODE 0

C0

DIN

SIO[3:1]
25119 F51.0

Note: SIO[3:1] must

5.10

SQI Read Burst with Wrap (RBSQI)

SQI Read Burst with wrap is similar to High Speed

Read in SQI mode, except data will output continuously
within the burst length until a low-to-high transition on
CE#. To execute a SQI Read Burst operation, drive
CE# low then send the Read Burst command cycle
(0CH), followed by three address cycles, and then
three dummy cycles. Each cycle is two nibbles (clocks)
long, most significant nibble first.
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low-tohigh transition on CE#.
During RBSQI, the internal address pointer automatically increments until the last byte of the burst is
reached, then it wraps around to the first byte of the
burst. All bursts are aligned to addresses within the
burst length, see Table 5-3. For example, if the burst
length is eight Bytes, and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h,
03h, 04h, 05h, 06h, etc. The pattern repeats until the
command is terminated by a low-to-high transition on
CE#.
During this operation, blocks that are Read-locked will
output data 00H.

TABLE 5-3:

5.11

SPI Read Burst with Wrap (RBSPI)

SPI Read Burst with Wrap (RBSPI) is similar to SPI

Quad I/O Read except the data will output continuously
within the burst length until a low-to-high transition on
CE#. To execute a SPI Read Burst with Wrap operation, drive CE# low, then send the Read Burst command cycle (ECH), followed by three address cycles,
and then three dummy cycles.
After the dummy cycle, the device outputs data on the
falling edge of the SCK signal starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low-tohigh transition on CE#.
During RBSPI, the internal address pointer automatically increments until the last byte of the burst is
reached, then it wraps around to the first byte of the
burst. All bursts are aligned to addresses within the
burst length, see Table 5-3. For example, if the burst
length is eight Bytes, and the start address is 06h, the
burst sequence would be: 06h, 07h, 00h, 01h, 02h,
03h, 04h, 05h, 06h, etc. The pattern repeats until the
command is terminated by a low-to-high transition on
CE#.
During this operation, blocks that are Read-locked will
output data 00H.

BURST ADDRESS RANGES

Burst Length

Burst Address Ranges

8 Bytes

00-07H, 08-0FH, 10-17H, 18-1FH...

16 Bytes

00-0FH, 10-1FH, 20-2FH, 30-3FH...

32 Bytes

00-1FH, 20-3FH, 40-5FH, 60-7FH...

64 Bytes

00-3FH, 40-7FH, 80-BFH, C0-FFH

0

2015 Microchip Technology Inc.

DS20005119G-page 21

SST26VF064B / SST26VF064BA
5.12

SPI Dual-Output Read

Following the dummy byte, the SST26VF064B/064BA

outputs data from SIO[1:0] starting from the specified
address location. The device continually streams data
output through all addresses until terminated by a lowto-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached, at which point the address pointer
returns to the beginning of the address space.

The SPI Dual-Output Read instruction supports frequencies of up to 104 MHz from 2.7-3.6V and up to 80
MHz from 2.3-3.6V. Initiate SPI Dual-Output Read by
executing an 8-bit command, 3BH, followed by address
bits A[23-0] and a dummy byte. CE# must remain
active low for the duration of the SPI Dual-Output Read
operation. See Figure 5-13 for the SPI Quad Output
Read sequence.

FIGURE 5-13:

FAST READ, DUAL-OUTPUT SEQUENCE

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

15 16

23 24

SIO0

3BH

A[23:16]

A[15:8]

SIO1
OP Code

Address

Note: MSB = Most Significant Bit.

5.13

39 40 41

31 32

MODE 0

SPI Dual I/O Read

The SPI Dual I/O Read (SDIOR) instruction supports

up to 80 MHz frequency. Initiate SDIOR by executing
an 8-bit command, BBH. The device then switches to
2-bit I/O mode for address bits A[23-0], followed by the
Set Mode configuration bits M[7:0]. CE# must remain
active low for the duration of the SPI Dual I/O Read.
See Figure 5-14 for the SPI Dual I/O Read sequence.

A[7:0]

b6 b5 b3 b1

b6 b5 b3 b1

MSB
b7 b4 b2 b0

b7 b4 b2 b0

Dummy

Data
Byte 0

Data
Byte N
25119 F52.3

execute the Reset Quad I/O command, FFH. See Figure 5-15 for the SPI Dual I/O Read sequence when
M[7:0] = AXH.

Following the Set Mode configuration bits, the

SST26VF064B/064BA outputs data from the specified
address location. The device continually streams data
output through all addresses until terminated by a lowto-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached, at which point the address pointer
returns to the beginning of the address space.
The Set Mode Configuration bit M[7:0] indicates if the
next instruction cycle is another SPI Dual I/O Read
command. When M[7:0] = AXH, the device expects the
next continuous instruction to be another SDIOR command, BBH, and does not require the op-code to be
entered again. The host may set the next SDIOR cycle
by driving CE# low, then sending the two-bit wide input
for address A[23:0], followed by the Set Mode configuration bits M[7:0]. After the Set Mode configuration bits,
the device outputs the data starting from the specified
address location. There are no restrictions on address
location access.
When M[7:0] is any value other than AXH, the device
expects the next instruction initiated to be a command
instruction. To reset/exit the Set Mode configuration,

DS20005119G-page 22

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
FIGURE 5-14:

SPI DUAL I/O READ SEQUENCE

CE#
MODE 3

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

MODE 0

SCK
SIO0

6 4 2 0 6 4 2 0 6 4 2 0 6 4

BBH

SIO1

7 5 3 1 7 5 3 1 7 5 3 1 7 5
A[23:16]

A[7:0]

A[15:8]

M[7:0]

CE#(cont)
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

SCK(cont)
I/O Switches from Input to Output

SIO0(cont)

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB

SIO1(cont)

MSB

MSB

MSB

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0

Byte 2

Byte 1

Byte 3
25119 F53.1

Note: MSB=

FIGURE 5-15:

BACK-TO-BACK SPI DUAL I/O READ SEQUENCES WHEN M[7:0] = AXH

CE#
MODE 3

0 1 2

3 4 5 6 7 8 9 10 11 12 13 14 15

MODE 0

SCK
I/O Switch

SIO0 6 4
MSB

SIO1 7 5

6 4 2 0 6 4 2 0 6 4 2 0 6 4

6 4 2 0
MSB

7 5 3 1 7 5 3 1 7 5 3 1 7 5

7 5 3 1

A[23:16]

A[15:8]

A[7:0]

M[7:0]

CE#(cont)
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SCK(cont)
I/O Switches from Input to Output

SIO0(cont)

6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
MSB

SIO1(cont)

MSB

MSB

MSB

7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
Byte 0

Byte 1

Byte 2

Byte 3
25119 F54.1

Note: MSB=

2015 Microchip Technology Inc.

DS20005119G-page 23

SST26VF064B / SST26VF064BA
5.14

JEDEC-ID Read (SPI Protocol)

Immediately
following
the
command
cycle,
SST26VF064B/064BA output data on the falling edge
of the SCK signal. The data output stream is continuous until terminated by a low-to-high transition on CE#.
The device outputs three bytes of data: manufacturer,
device type, and device ID, see Table 5-4. See Figure
5-16 for instruction sequence.

Using traditional SPI protocol, the JEDEC-ID Read

instruction identifies the device as SST26VF064B/
064BA and the manufacturer as Microchip. To execute a JECEC-ID operation the host drives CE# low
then sends the JEDEC-ID command cycle (9FH).

TABLE 5-4:

DEVICE ID DATA OUTPUT

Device ID

Product

Manufacturer ID (Byte 1)

Device Type (Byte 2)

Device ID (Byte 3)

SST26VF064B/064BA

BFH

26H

43H

FIGURE 5-16:

JEDEC-ID SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

MODE 0

SI

SO

9F
HIGH IMPEDANCE

26

BF
MSB

Device ID

MSB
25119 F38.0

5.15

Read Quad J-ID Read (SQI

Protocol)

Immediately following the command cycle and one

dummy cycle, SST26VF064B/064BA output data on
the falling edge of the SCK signal. The data output
stream is continuous until terminated by a low-to-high
transition of CE#. The device outputs three bytes of
data: manufacturer, device type, and device ID, see
Table 5-4. See Figure 5-17 for instruction sequence.

The Read Quad J-ID Read instruction identifies the

device as SST26VF064B/064BA and manufacturer as
Microchip. To execute a Quad J-ID operation the host
drives CE# low and then sends the Quad J-ID command cycle (AFH). Each cycle is two nibbles (clocks)
long, most significant nibble first.

FIGURE 5-17:

QUAD J-ID READ SEQUENCE

CE#
MODE 3

C0

C1

MSN

LSN

H0

L0

H2

L2

10

11

12

13

SCK
MODE 0

SIO(3:0)

Dummy

BFH

H1

L1

26H

Device ID

H0

L0

H1

BFH

L1

26H

HN

LN

N
25119 F55.0

Note: MSN = Most significant Nibble; LSN= Least Significant Nibble. C{1:0]=AFH

DS20005119G-page 24

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.16

Serial Flash Discoverable

Parameters (SFDP)

ware support for all future Serial Flash device families.

See Table 11-1 on page 66 for address and data values.

The Serial Flash Discoverable Parameters (SFDP)

contain information describing the characteristics of the
device. This allows device-independent, JEDEC IDindependent, and forward/backward compatible soft-

FIGURE 5-18:

Initiate SFDP by executing an 8-bit command, 5AH, followed by address bits A[23-0] and a dummy byte. CE#
must remain active low for the duration of the SFDP
cycle. For the SFDP sequence, see Figure 5-18.

SERIAL FLASH DISCOVERABLE PARAMETERS SEQUENCE

CE#
MODE 3
SCK

0 1 2 3 4 5 6 7 8

15 16

23 24

31 32

39 40

47 48

55 56

63 64

71 72

80

MODE 0

5A

SI

ADD.

ADD.

ADD.

X
N
DOUT
MSB

HIGH IMPEDANCE

SO

N+1
DOUT

N+2
DOUT

N+3
DOUT

N+4
DOUT
25119 F56.0

5.17

Sector-Erase

To execute a Sector-Erase operation, the host drives

CE# low, then sends the Sector Erase command cycle
(20H) and three address cycles, and then drives CE#
high. Address bits [AMS:A12] (AMS = Most Significant
Address) determine the sector address (SAX); the
remaining address bits can be VIL or VIH. To identify the
completion of the internal, self-timed, Write operation,
poll the BUSY bit in the Status register, or wait TSE. See
Figures 5-19 and 5-20 for the Sector-Erase sequence.

The Sector-Erase instruction clears all bits in the

selected 4 KByte sector to 1, but it does not change a
protected memory area. Prior to any write operation,
the Write-Enable (WREN) instruction must be executed.

FIGURE 5-19:

4 KBYTE SECTOR-ERASE SEQUENCE SQI MODE

CE#
MODE 3

SCK

MODE 0

SIO(3:0)

C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
25119 F07.0

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble, C[1:0] = 20H

FIGURE 5-20:

4 KBYTE SECTOR-ERASE SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

15 16

23 24

31

MODE 0

20

SI
MSB

SO

ADD.

ADD.

ADD.

MSB

HIGH IMPEDANCE
25119 F57.0

2015 Microchip Technology Inc.

DS20005119G-page 25

SST26VF064B / SST26VF064BA
5.18

Block-Erase

To execute a Block-Erase operation, the host drives

CE# low then sends the Block-Erase command cycle
(D8H), three address cycles, then drives CE# high.
Address bits AMS-A13 determine the block address
(BAX); the remaining address bits can be VIL or VIH. For
32 KByte blocks, A14:A13 can be VIL or VIH; for 64
KByte blocks, A15:A13 can be VIL or VIH. Poll the BUSY
bit in the Status register, or wait TBE, for the completion
of the internal, self-timed, Block-Erase operation. See
Figures 5-21 and 5-22 for the Block-Erase sequence.

The Block-Erase instruction clears all bits in the

selected block to 1. Block sizes can be 8 KByte, 32
KByte or 64 KByte depending on address, see Figure
3-1, Memory Map, for details. A Block-Erase instruction
applied to a protected memory area will be ignored.
Prior to any write operation, execute the WREN instruction. Keep CE# active low for the duration of any command sequence.

FIGURE 5-21:

BLOCK-ERASE SEQUENCE (SQI)

CE#
MODE 3

SCK

MODE 0

SIO(3:0)

C1 C0 A5 A4 A3 A2 A1 A0
MSN LSN
25119 F08.0

Note: MSN = Most Significant Nibble,

LSN = Least Significant Nibble
C[1:0] = D8H

FIGURE 5-22:

BLOCK-ERASE SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

D8

SI
MSB

SO

15 16

23 24

31

MODE 0

ADDR

ADDR

ADDR

MSB

HIGH IMPEDANCE
25119 F58.0

DS20005119G-page 26

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.19

Chip-Erase

To execute a Chip-Erase operation, the host drives

CE# low, sends the Chip-Erase command cycle (C7H),
then drives CE# high. Poll the BUSY bit in the Status
register, or wait TSCE, for the completion of the internal,
self-timed, Write operation. See Figures 5-23 and 5-24
for the Chip Erase sequence.

The Chip-Erase instruction clears all bits in the device

to 1. The Chip-Erase instruction is ignored if any of the
memory area is protected. Prior to any write operation,
execute the WREN instruction.

FIGURE 5-23:

CHIP-ERASE SEQUENCE (SQI)

CE#
MODE 3

SCK

MODE 0

SIO(3:0)

C1 C0
25119 F09.1

Note: C[1:0] = C7H

FIGURE 5-24:

CHIP-ERASE SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7

MODE 0

C7

SI
MSB

SO

HIGH IMPEDANCE
25119 F59.0

2015 Microchip Technology Inc.

DS20005119G-page 27

SST26VF064B / SST26VF064BA
5.20

Page-Program

partial Byte to be ignored. Poll the BUSY bit in the Status register, or wait TPP, for the completion of the internal, self-timed, Write operation. See Figures 5-25 and
5-26 for the Page-Program sequence.

The Page-Program instruction programs up to 256

Bytes of data in the memory, and supports both SPI
and SQI protocols. The data for the selected page
address must be in the erased state (FFH) before initiating the Page-Program operation. A Page-Program
applied to a protected memory area will be ignored.
Prior to the program operation, execute the WREN
instruction.

When executing Page-Program, the memory range for

the SST26VF064B/064BA is divided into 256 Byte
page boundaries. The device handles shifting of more
than 256 Bytes of data by maintaining the last 256
Bytes of data as the correct data to be programmed. If
the target address for the Page-Program instruction is
not the beginning of the page boundary (A[7:0] are not
all zero), and the number of bytes of data input exceeds
or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page.

To execute a Page-Program operation, the host drives

CE# low then sends the Page Program command cycle
(02H), three address cycles followed by the data to be
programmed, then drives CE# high. The programmed
data must be between 1 to 256 Bytes and in whole Byte
increments; sending less than a full Byte will cause the

FIGURE 5-25:

PAGE-PROGRAM SEQUENCE (SQI)

CE#
MODE 3

SCK

10

12

MODE 0

SIO(3:0)

C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2

HN LN

MSN LSN
Data Byte 0 Data Byte 1 Data Byte 2

Data Byte 255

25119 F10.1

Note:
MSN = Most Significant Nibble, LSN = Least Significant Nibble

FIGURE 5-26:

PAGE-PROGRAM SEQUENCE (SPI)

CE#
MODE 3

SCK

23 24

15 16

0 1 2 3 4 5 6 7 8

31 32

39

MODE 0

SI

ADD.

02
MSB

SO

ADD.

ADD.

Data Byte 0

LSB MSB

LSB MSB

LSB

HIGH IMPEDANCE

2079

2078

2077

2076

2075

2074

2073

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

2072

CE#(cont)

SCK(cont)
SI(cont)

Data Byte 1
MSB

SO(cont)

Data Byte 255

Data Byte 2
LSB MSB

LSB

MSB

LSB

HIGH IMPEDANCE
25119 F60.1

DS20005119G-page 28

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.21

SPI Quad Page-Program

The SPI Quad Page-Program instruction programs up

to 256 Bytes of data in the memory. The data for the
selected page address must be in the erased state
(FFH) before initiating the SPI Quad Page-Program
operation. A SPI Quad Page-Program applied to a protected memory area will be ignored. SST26VF064B
requires the ICO bit in the configuration register to be
set to 1 prior to executing the command. Prior to the
program operation, execute the WREN instruction.
To execute a SPI Quad Page-Program operation, the
host drives CE# low then sends the SPI Quad PageProgram command cycle (32H), three address cycles
followed by the data to be programmed, then drives
CE# high. The programmed data must be between 1 to
256 Bytes and in whole Byte increments. The com-

FIGURE 5-27:

mand cycle is eight clocks long, the address and data

cycles are each two clocks long, most significant bit
first. Poll the BUSY bit in the Status register, or wait TPP,
for the completion of the internal, self-timed, Write
operation.See Figure 5-27.
When executing SPI Quad Page-Program, the memory
range for the SST26VF064B/064BA is divided into 256
Byte page boundaries. The device handles shifting of
more than 256 Bytes of data by maintaining the last 256
Bytes of data as the correct data to be programmed. If
the target address for the SPI Quad Page-Program
instruction is not the beginning of the page boundary
(A[7:0] are not all zero), and the of bytes of data input
exceeds or overlaps the end of the address of the page
boundary, the excess data inputs wrap around and will
be programmed at the start of that target page.

SPI QUAD PAGE-PROGRAM SEQUENCE

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

MODE 0

SIO0

32H

A20A16A12 A8 A4 A0 b4 b0 b4 b0

b4 b0

SIO1

A21 A17A13 A9 A5 A1 b5 b1 b5 b1

b5 b1

SIO2

A22 A18A14A10 A6 A2 b6 b2 b6 b2

b6 b2

MSN LSN

SIO3

A23 A19 A15 A11 A7 A3 b7 b3 b7 b3

b7 b3

Data Data
Byte 0 Byte 1

Data
Byte
255

Address

25119 F61.0

5.22

Write-Suspend and Write-Resume

Write-Suspend allows the interruption of Sector-Erase,

Block-Erase, SPI Quad Page-Program, or Page-Program operations in order to erase, program, or read
data in another portion of memory. The original operation can be continued with the Write-Resume command. This operation is supported in both SQI and SPI
protocols.
Only one write operation can be suspended at a time;
if an operation is already suspended, the device will
ignore the Write-Suspend command. Write-Suspend
during Chip-Erase is ignored; Chip-Erase is not a valid
command while a write is suspended. The WriteResume command is ignored until any write operation
(Program or Erase) initiated during the Write-Suspend
is complete. The device requires a minimum of 500 s
between each Write-Suspend command.

2015 Microchip Technology Inc.

5.23

Write-Suspend During SectorErase or Block-Erase

Issuing a Write-Suspend instruction during SectorErase or Block-Erase allows the host to program or
read any sector that was not being erased. The device
will ignore any programming commands pointing to the
suspended sector(s). Any attempt to read from the suspended sector(s) will output unknown data because the
Sector- or Block-Erase will be incomplete.
To execute a Write-Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle
(B0H), then drives CE# high. The Status register indicates that the erase has been suspended by changing
the WSE bit from 0 to 1, but the device will not accept
another command until it is ready. To determine when
the device will accept a new command, poll the BUSY
bit in the Status register or wait TWS.

DS20005119G-page 29

SST26VF064B / SST26VF064BA
5.24

Write Suspend During Page

Programming or SPI Quad Page
Programming

Issuing a Write-Suspend instruction during Page Programming allows the host to erase or read any sector
that is not being programmed. Erase commands pointing to the suspended sector(s) will be ignored. Any
attempt to read from the suspended page will output
unknown data because the program will be incomplete.
To execute a Write Suspend operation, the host drives
CE# low, sends the Write Suspend command cycle
(B0H), then drives CE# high. The Status register indicates that the programming has been suspended by
changing the WSP bit from 0 to 1, but the device will
not accept another command until it is ready. To determine when the device will accept a new command, poll
the BUSY bit in the Status register or wait TWS.

5.25

Write-Resume

Write-Resume restarts a Write command that was suspended, and changes the suspend status bit in the Status register (WSE or WSP) back to 0.
To execute a Write-Resume operation, the host drives
CE# low, sends the Write Resume command cycle
(30H), then drives CE# high. To determine if the internal, self-timed Write operation completed, poll the
BUSY bit in the Status register, or wait the specified
time TSE, TBE or TPP for Sector-Erase, Block-Erase, or
Page-Programming, respectively. The total write time
before suspend and after resume will not exceed the
uninterrupted write times TSE, TBE or TPP.

5.26

Read Security ID

The Read Security ID operation is supported in both

SPI and SQI modes. To execute a Read Security ID
(SID) operation in SPI mode, the host drives CE# low,
sends the Read Security ID command cycle (88H), two
address cycles, and then one dummy cycle. To execute

TABLE 5-5:

a Read Security ID operation in SQI mode, the host

drives CE# low and then sends the Read Security ID
command, two address cycles, and three dummy
cycles.
After the dummy cycles, the device outputs data on the
falling edge of the SCK signal, starting from the specified address location. The data output stream is continuous through all SID addresses until terminated by a
low-to-high transition on CE#. See Table 5-5 for the
Security ID address range.

5.27

Program Security ID

The Program Security ID instruction programs one to

2040 Bytes of data in the user-programmable, Security
ID space. This Security ID space is one-time programmable (OTP). The device ignores a Program Security
ID instruction pointing to an invalid or protected
address, see Table 5-5. Prior to the program operation,
execute WREN.
To execute a Program SID operation, the host drives
CE# low, sends the Program Security ID command
cycle (A5H), two address cycles, the data to be programmed, then drives CE# high. The programmed data
must be between 1 to 256 Bytes and in whole Byte
increments.
The device handles shifting of more than 256 Bytes of
data by maintaining the last 256 Bytes of data as the
correct data to be programmed. If the target address for
the Program Security ID instruction is not the beginning
of the page boundary, and the number of data input
exceeds or overlaps the end of the address of the page
boundary, the excess data inputs wrap around and will
be programmed at the start of that target page.
The Program Security ID operation is supported in both
SPI and SQI mode. To determine the completion of the
internal, self-timed Program SID operation, poll the
BUSY bit in the software status register, or wait TPSID
for the completion of the internal self-timed Program
Security ID operation.

PROGRAM SECURITY ID

Program Security ID

Address Range

Unique ID Pre-Programmed at factory

0000 0007H

User Programmable

0008H 07FFH

DS20005119G-page 30

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.28

Lockout Security ID

mands function in both SPI and SQI modes. The Status

register may be read at any time, even during a Write
operation. When a Write is in progress, poll the BUSY
bit before sending any new commands to assure that
the new commands are properly received by the
device.

The Lockout Security ID instruction prevents any future

changes to the Security ID, and is supported in both
SPI and SQI modes. Prior to the operation, execute
WREN.
To execute a Lockout SID, the host drives CE# low,
sends the Lockout Security ID command cycle (85H),
then drives CE# high. Poll the BUSY bit in the software
status register, or wait TPSID, for the completion of the
Lockout Security ID operation.

5.29

To Read the Status or Configuration registers, the host

drives CE# low, then sends the Read-Status-Register
command cycle (05H) or the Read Configuration Register command (35H). A dummy cycle is required in
SQI mode. Immediately after the command cycle, the
device outputs data on the falling edge of the SCK signal. The data output stream continues until terminated
by a low-to-high transition on CE#. See Figures 5-28
and 5-29 for the instruction sequence.

Read-Status Register (RDSR) and

Read-Configuration Register
(RDCR)

The Read-Status Register (RDSR) and Read-Configuration Register (RDCR) commands output the contents
of the Status and Configuration registers. These com-

FIGURE 5-28:

READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER

SEQUENCE (SQI)
CE#
MODE 3

SCK MODE 0
MSN LSN

SIO(3:0)

C1 C0 X

X H0 L0 H0 L0

Dummy

Data Byte

H0 L0

Data Byte

Data Byte

25119 F11.1

Note: MSN = Most Significant Nibble; LSN = Least Significant Nibble, C[1:0]=05H or 35H

FIGURE 5-29:

READ-STATUS-REGISTER AND READ-CONFIGURATION REGISTER

SEQUENCE (SPI)

CE#
MODE 3

SCK

10

11

12

13

14

MODE 0

05 or 35

SI
MSB

SO

HIGH IMPEDANCE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MSB

Status or Configuration
Register Out
25119 F62.0

2015 Microchip Technology Inc.

DS20005119G-page 31

SST26VF064B / SST26VF064BA
5.30

Write-Status Register (WRSR)

low, then sends the Write-Status Register command

cycle (01H), two cycles of data, and then drives CE#
high. Values in the second data cycle will be accepted
by the device. See Figures 5-30 and 5-31.

The Write-Status Register (WRSR) command writes

new values to the Configuration register. To execute a
Write-Status Register operation, the host drives CE#

FIGURE 5-30:

WRITE-STATUS-REGISTER SEQUENCE (SQI)

CE#
MODE 3

SCK

MODE 0
MSN LSN

SIO[3:0]

C1 C0 XX XX H0 L0
Command Status
Byte

Configuration
Byte

25119 F63.1

Note: MSN = Most Significant Nibble;

FIGURE 5-31:

WRITE-STATUS-REGISTER SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

MODE 0

01

SI
MSB
SO

STATUS
CONFIGURATION
REGISTER
REGISTER
XX XX XX XX XX XX XX XX 7 6 5 4 3 2 1 0
MSB

MSB

HIGH IMPEDANCE
25119 F64.1

Note: XX = Dont Care

DS20005119G-page 32

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.31

Write-Enable (WREN)

Protection Register, Lock-Down Block-Protection Register, Non-Volatile Write-Lock Lock-Down Register, SPI
Quad Page program, and Write-Status Register. To
execute a Write Enable the host drives CE# low then
sends the Write Enable command cycle (06H) then
drives CE# high. See Figures 5-32 and 5-33 for the
WREN instruction sequence.

The Write Enable (WREN) instruction sets the WriteEnable-Latch bit in the Status register to 1, allowing
Write operations to occur. The WREN instruction must
be executed prior to any of the following operations:
Sector Erase, Block Erase, Chip Erase, Page Program,
Program Security ID, Lockout Security ID, Write Block-

FIGURE 5-32:

WRITE-ENABLE SEQUENCE (SQI)

CE#
MODE 3

SCK

MODE 0

SIO[3:0]

25119 F12.1

FIGURE 5-33:

WRITE-ENABLE SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7

MODE 0

06

SI
MSB

SO

HIGH IMPEDANCE
25119 F18.0

2015 Microchip Technology Inc.

DS20005119G-page 33

SST26VF064B / SST26VF064BA
5.32

Write-Disable (WRDI)

during any internal write operations. Any Write operation started before executing WRDI will complete. Drive
CE# high before executing WRDI.

The Write-Disable (WRDI) instruction sets the WriteEnable-Latch bit in the Status register to 0, preventing
Write operations. The WRDI instruction is ignored

FIGURE 5-34:

To execute a Write-Disable, the host drives CE# low,

sends the Write Disable command cycle (04H), then
drives CE# high. See Figures 5-34 and 5-35.

WRITE-DISABLE (WRDI) SEQUENCE (SQI)

CE#
MODE 3

SCK

MODE 0

SIO(3:0)

25119 F33.1

FIGURE 5-35:

WRITE-DISABLE (WRDI) SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7

MODE 0

04

SI
MSB

SO

HIGH IMPEDANCE
25119 F19.0

DS20005119G-page 34

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.33

Read Block-Protection Register

(RBPR)

After the command cycle, the device outputs data on

the falling edge of the SCK signal starting with the most
significant bit(s), see Table 5-6 for definitions of each bit
in the Block-Protection register. The RBPR command
does not wrap around. After all data has been output,
the device will output 0H until terminated by a low-tohigh transition on CE#. Figures 5-36 and 5-37.

The Read Block-Protection Register instruction outputs

the Block-Protection register data which determines
the protection status. To execute a Read Block-Protection Register operation, the host drives CE# low, and
then sends the Read Block-Protection Register command cycle (72H). A dummy cycle is required in SQI
mode.

FIGURE 5-36:

READ BLOCK-PROTECTION REGISTER SEQUENCE (SQI)

CE#
MODE 3

10

12

SCK
SIO[3:0]

C1 C0 X

X H0 L0 H1 L1 H2 L2 H3 L3 H4 L4
MSN LSN
BPR [m:m-7]

HN LN
BPR [7:0]

25119 F34.2

Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble

Block-Protection Register (BPR), m = 143 for SST26VF064B/064BA, C[1:0]=72H

FIGURE 5-37:

READ BLOCK-PROTECTION REGISTER SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

15 16

23 24

32 33

MODE 0

SIO0

72H
OP Code

SIO

Data Byte 0

Data Byte 1 Data Byte 2

Data Byte N
25119 F48.0

2015 Microchip Technology Inc.

DS20005119G-page 35

SST26VF064B / SST26VF064BA
5.34

Write Block-Protection Register

(WBPR)

To execute a Write Block-Protection Register operation

the host drives CE# low, sends the Write Block-Protection Register command cycle (42H), sends 18 cycles of
data, and finally drives CE# high. Data input must be
most significant bit(s) first. See Table 5-6 for definitions
of each bit in the Block-Protection register. See Figures
5-38 and 5-39.

The Write Block-Protection Register (WBPR) command changes the Block-Protection register data to
indicate the protection status. Execute WREN before
executing WBPR.

FIGURE 5-38:

WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SQI)

CE#
MODE 3

SCK

10

12

MODE 0

SIO(3:0)

C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5

HN LN

MSN LSN
BPR [143:136]

BPR [7:0]
25119 F35.1

Note: MS
N = Most Significant Nibble, LSN = Least Significant Nibble
Block-Protection Register (BPR) C[1:0]=42H

FIGURE 5-39:

WRITE BLOCK-PROTECTION REGISTER SEQUENCE (SPI).

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

15 16

23 24

31 32

MODE 0
OP Code

SI

42H

Data Byte0

Data Byte1 Data Byte2

Data ByteN

SO
25119 F66.1

Note: C[1:0]=42H

DS20005119G-page 36

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.35

Lock-Down Block-Protection
Register (LBPR)

cycling; this allows the Block-Protection register to be

changed. Execute WREN before initiating the LockDown Block-Protection Register instruction.

The Lock-Down Block-Protection Register instruction

prevents changes to the Block-Protection register
during device operation. Lock-Down resets after power

FIGURE 5-40:

To execute a Lock-Down Block-Protection Register, the

host drives CE# low, then sends the Lock-Down BlockProtection Register command cycle (8DH), then drives
CE# high.

LOCK-DOWN BLOCK-PROTECTION REGISTER (SQI)

CE#
MODE 3

SCK

MODE 0

SIO(3:0)

C1 C0
25119 F30.1

Note: C[1:0]=8DH

FIGURE 5-41:

LOCK-DOWN BLOCK-PROTECTION REGISTER (SPI)

CE#
MODE 3

SCK
SIO0

MODE 0

8D

SIO[3:1]
25119 F67.0

2015 Microchip Technology Inc.

DS20005119G-page 37

SST26VF064B / SST26VF064BA
5.36

Non-Volatile Write-Lock LockDown Register (nVWLDR)

After CE# goes high, the non-volatile bits are programmed and the programming time-out must complete before any additional commands, other than
Read Status Register, can be entered. Poll the BUSY
bit in the Status register, or wait TPP, for the completion
of the internal, self-timed, Write operation. Data inputs
must be most significant bit(s) first.

The Non-Volatile Write-Lock Lock-Down Register

(nVWLDR) instruction controls the ability to change the
Write-Lock bits in the Block-Protection register. Execute WREN before initiating the nVWLDR instruction.
To execute nVWLDR, the host drives CE# low, then
sends the nVWLDR command cycle (E8H), followed by
18 cycles of data, and then drives CE# high.

FIGURE 5-42:

WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)

CE#
MODE 3

SCK

10

12

MODE 0

SIO(3:0)

8 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5

HN LN

MSN LSN
BPR [m:m-7]

BPR [7:0]
25119 F36.0

Note:
MSN= Most Significant Nibble; LSN = Least Significant Nibble
Write-Lock Lock-Down Register (nVWLDR) m = 143

FIGURE 5-43:

WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)

CE#
MODE 3

SCK

0 1 2 3 4 5 6 7 8

15 16

23 24

31 32

MODE 0
OP Code

SI

E8H

Data Byte0

Data Byte1 Data Byte2

Data ByteN

SO
25119 F69.1

DS20005119G-page 38

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
5.37

Global Block-Protection Unlock

(ULBPR)

To execute a ULBPR instruction, the host drives CE#

low, then sends the ULBPR command cycle (98H), and
then drives CE# high.

The Global Block-Protection Unlock (ULBPR) instruction clears all write-protection bits in the Block-Protection register, except for those bits that have been
locked down with the nVWLDR command. Execute
WREN before initiating the ULBPR instruction.

FIGURE 5-44:

GLOBAL BLOCK-PROTECTION UNLOCK (SQI)

CE#
MODE 3

SCK

MODE 0

SIO(3:0)

C1 C0
25119 F20.1

Note: C[1:0]=98H

FIGURE 5-45:

GLOBAL BLOCK-PROTECTION UNLOCK (SPI)

CE#
MODE 3

SCK
SIO0

MODE 0

98

SIO[3:1]
25119 F68.0

2015 Microchip Technology Inc.

DS20005119G-page 39

SST26VF064B / SST26VF064BA
TABLE 5-6:

BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (1 OF 4)1

BPR Bits

Read Lock

Write Lock/
nVWLDR2

Address Range

Protected Block
Size

143
141

142

7FE000H - 7FFFFFH

8 KByte

140

7FC000H - 7FDFFFH

8 KByte

139

138

7FA000H - 7FBFFFH

8 KByte

137

136

7F8000H - 7F9FFFH

8 KByte

135

134

006000H - 007FFFH

8 KByte

133

132

004000H - 005FFFH

8 KByte

131

130

002000H - 003FFFH

8 KByte

129

128

000000H - 001FFFH

8 KByte

127

7F0000H - 7F7FFFH

32 KByte

126

008000H - 00FFFFH

32 KByte

125

7E0000H - 7EFFFFH

64 KByte

124

7D0000H - 7DFFFFH

64 KByte

123

7C0000H - 7CFFFFH

64 KByte

122

7B0000H - 7BFFFFH

64 KByte

121

7A0000H - 7AFFFFH

64 KByte

120

790000H - 79FFFFH

64 KByte

119

780000H - 78FFFFH

64 KByte

118

770000H - 77FFFFH

64 KByte

117

760000H - 76FFFFH

64 KByte

116

750000H - 75FFFFH

64 KByte

115

740000H - 74FFFFH

64 KByte

114

730000H - 73FFFFH

64 KByte

113

720000H - 72FFFFH

64 KByte

112

710000H - 71FFFFH

64 KByte

111

700000H - 70FFFFH

64 KByte

DS20005119G-page 40

110

6F0000H - 6FFFFFH

64 KByte

109

6E0000H - 6EFFFFH

64 KByte

108

6D0000H - 6DFFFFH

64 KByte

107

6C0000H - 6CFFFFH

64 KByte

106

6B0000H - 6BFFFFH

64 KByte

105

6A0000H - 6AFFFFH

64 KByte

104

690000H - 69FFFFH

64 KByte

103

680000H - 68FFFFH

64 KByte

102

670000H - 67FFFFH

64 KByte

101

660000H - 66FFFFH

64 KByte

100

650000H - 65FFFFH

64 KByte

99

640000H - 64FFFFH

64 KByte

98

630000H - 63FFFFH

64 KByte

97

620000H - 62FFFFH

64 KByte

96

610000H - 61FFFFH

64 KByte

95

600000H - 60FFFFH

64 KByte

94

5F0000H - 5FFFFFH

64 KByte

93

5E0000H - 5EFFFFH

64 KByte

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 5-6:

BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (CONTINUED) (2 OF 4)1

BPR Bits

Read Lock

Write Lock/
nVWLDR2

Address Range

Protected Block
Size

92

5D0000H - 5DFFFFH

64 KByte

91

5C0000H - 5CFFFFH

64 KByte

2015 Microchip Technology Inc.

90

5B0000H - 5BFFFFH

64 KByte

89

5A0000H - 5AFFFFH

64 KByte

88

590000H - 59FFFFH

64 KByte

87

580000H - 58FFFFH

64 KByte

86

570000H - 57FFFFH

64 KByte

85

560000H - 56FFFFH

64 KByte

84

550000H - 55FFFFH

64 KByte

83

540000H - 54FFFFH

64 KByte

82

530000H - 53FFFFH

64 KByte

81

520000H - 52FFFFH

64 KByte

80

510000H - 51FFFFH

64 KByte

79

500000H - 50FFFFH

64 KByte

78

4F0000H - 4FFFFFH

64 KByte

77

4E0000H - 4EFFFFH

64 KByte

76

4D0000H - 4DFFFFH

64 KByte

75

4C0000H - 4CFFFFH

64 KByte

74

4B0000H - 4BFFFFH

64 KByte

73

4A0000H - 4AFFFFH

64 KByte

72

490000H - 49FFFFH

64 KByte

71

480000H - 48FFFFH

64 KByte

70

470000H - 47FFFFH

64 KByte

69

460000H - 46FFFFH

64 KByte

68

450000H - 45FFFFH

64 KByte

67

440000H - 44FFFFH

64 KByte

66

430000H - 43FFFFH

64 KByte

65

420000H - 42FFFFH

64 KByte

64

410000H - 41FFFFH

64 KByte

63

400000H - 40FFFFH

64 KByte

62

3F0000H - 3FFFFFH

64 KByte

61

3E0000H - 3EFFFFH

64 KByte

60

3D0000H - 3DFFFFH

64 KByte

59

3C0000H - 3CFFFFH

64 KByte

58

3B0000H - 3BFFFFH

64 KByte

57

3A0000H - 3AFFFFH

64 KByte

56

390000H - 39FFFFH

64 KByte

55

380000H - 38FFFFH

64 KByte

54

370000H - 37FFFFH

64 KByte

53

360000H - 36FFFFH

64 KByte

52

350000H - 35FFFFH

64 KByte

51

340000H - 34FFFFH

64 KByte

50

330000H - 33FFFFH

64 KByte

DS20005119G-page 41

SST26VF064B / SST26VF064BA
TABLE 5-6:

BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (CONTINUED) (3 OF 4)1

BPR Bits

Read Lock

DS20005119G-page 42

Write Lock/
nVWLDR2

Address Range

Protected Block
Size

49

320000H - 32FFFFH

64 KByte

48

310000H - 31FFFFH

64 KByte

47

300000H - 30FFFFH

64 KByte

46

2F0000H - 2FFFFFH

64 KByte

45

2E0000H - 2EFFFFH

64 KByte

44

2D0000H - 2DFFFFH

64 KByte

43

2C0000H - 2CFFFFH

64 KByte

42

2B0000H - 2BFFFFH

64 KByte

41

2A0000H - 2AFFFFH

64 KByte

40

290000H - 29FFFFH

64 KByte

39

280000H - 28FFFFH

64 KByte

38

270000H - 27FFFFH

64 KByte

37

260000H - 26FFFFH

64 KByte

36

250000H - 25FFFFH

64 KByte

35

240000H - 24FFFFH

64 KByte

34

230000H - 23FFFFH

64 KByte

33

220000H - 22FFFFH

64 KByte

32

210000H - 21FFFFH

64 KByte

31

200000H - 20FFFFH

64 KByte

30

1F0000H - 1FFFFFH

64 KByte

29

1E0000H - 1EFFFFH

64 KByte

28

1D0000H - 1DFFFFH

64 KByte

27

1C0000H - 1CFFFFH

64 KByte

26

1B0000H - 1BFFFFH

64 KByte

25

1A0000H - 1AFFFFH

64 KByte

24

190000H - 19FFFFH

64 KByte

23

180000H - 18FFFFH

64 KByte

22

170000H - 17FFFFH

64 KByte

21

160000H - 16FFFFH

64 KByte

20

150000H - 15FFFFH

64 KByte

19

140000H - 14FFFFH

64 KByte

18

130000H - 13FFFFH

64 KByte

17

120000H - 12FFFFH

64 KByte

16

110000H - 11FFFFH

64 KByte

15

100000H - 10FFFFH

64 KByte

14

0F0000H - 0FFFFFH

64 KByte

13

0E0000H - 0EFFFFH

64 KByte

12

0D0000H - 0DFFFFH

64 KByte

11

0C0000H - 0CFFFFH

64 KByte

10

0B0000H - 0BFFFFH

64 KByte

0A0000H - 0AFFFFH

64 KByte

090000H - 09FFFFH

64 KByte

080000H - 08FFFFH

64 KByte

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 5-6:

BLOCK-PROTECTION REGISTER FOR SST26VF064B/064BA (CONTINUED) (4 OF 4)1

BPR Bits

Read Lock

Write Lock/
nVWLDR2

Address Range

Protected Block
Size

070000H - 07FFFFH

64 KByte

060000H - 06FFFFH

64 KByte

050000H - 05FFFFH

64 KByte

040000H - 04FFFFH

64 KByte

030000H - 03FFFFH

64 KByte

020000H - 02FFFFH

64 KByte

010000H - 01FFFFH

64 KByte

1. The default state after a power-on reset is write-protected BPR[143:0] = 5555 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
2. nVWLDR bits are one-time-programmable. Once a nVWLDR bit is set, the protection state of that particular block is permanently write-locked.

2015 Microchip Technology Inc.

DS20005119G-page 43

SST26VF064B / SST26VF064BA
6.0

ELECTRICAL SPECIFICATIONS

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.

TABLE 6-1:

OPERATING RANGE

Range

Ambient Temp

Industrial

-40C to +85C

Extended

-40C to +105C

DS20005119G-page 44

VDD
2.3-3.6V

TABLE 6-2:

AC CONDITIONS OF TEST1

Input Rise/Fall Time

Output Load

3ns

CL = 30 pF

1. See Figure 8-5

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
6.1

Power-Up Specifications

All functionalities and DC specifications are specified

for a VDD ramp rate of greater than 1V per 100 ms (0V
to 3.0V in less than 300 ms). See Table 6-3 and Figure
6-1 for more information.

TABLE 6-3:

When VDD drops from the operating voltage to below

the minimum VDD threshold at power-down, all operations are disabled and the device does not respond to
commands. Data corruption may result if a power-down
occurs while a Write-Registers, program, or erase
operation is in progress. See Figure 6-2.

RECOMMENDED SYSTEM POWER-UP/DOWN TIMINGS

Symbol

Parameter

TPU-READ1

VDD Min to Read Operation

100

TPU-WRITE1

VDD Min to Write Operation

100

Power-down Duration

100

ms

TPD

VOFF

Minimum

VDD off time

Max

0.3

Units

Condition

0V recommended

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

FIGURE 6-1:

POWER-UP TIMING DIAGRAM

VDD

VDD Max
Chip selection is not allowed.
Commands may not be accepted or properly
interpreted by the device.

VDD Min
TPU-READ
TPU-WRITE

Device fully accessible

Time
25119 F27.0

2015 Microchip Technology Inc.

DS20005119G-page 45

SST26VF064B / SST26VF064BA
FIGURE 6-2:

POWER-DOWN AND VOLTAGE DROP DIAGRAM

VDD

VDD Max
No Device Access Allowed

VDD Min
TPU

Device
Access
Allowed

VOFF

TPD

Time
25119 F72.0

DS20005119G-page 46

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
7.0

DC CHARACTERISTICS

TABLE 7-1:

DC OPERATING CHARACTERISTICS (VDD = 2.3 - 3.6V)

Limits

Symbol

Parameter

IDDR1

Read Current

IDDR2

Min

Typ

Max

Units

15

mA

VDD=VDD Max,
CE#=0.1 VDD/0.9 VDD@40 MHz,
SO=open

Read Current

20

mA

VDD = VDD Max,

CE#=0.1 VDD/0.9 VDD@104 MHz,
SO=open

IDDW

Program and Erase Current

25

mA

VDD Max

ISB

Standby Current

45

CE#=VDD, VIN=VDD or VSS

VIN=GND to VDD, VDD=VDD Max

ILI

Input Leakage Current

ILO

Output Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

TABLE 7-2:

15

Test Conditions

VOUT=GND to VDD, VDD=VDD Max

0.8

VDD=VDD Min

VDD=VDD Max

0.2

IOL=100 A, VDD=VDD Min

IOH=-100 A, VDD=VDD Min

0.7 VDD
VDD-0.2

CAPACITANCE (TA = 25C, F=1 MHZ, OTHER PINS OPEN)

Parameter

Description

COUT1

Output Pin Capacitance

CIN1

Input Capacitance

Test Condition

Maximum

VOUT = 0V

8 pF

VIN = 0V

6 pF

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 7-3:

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Minimum Specification

Units

Test Method

NEND1

Endurance

100,000

Cycles

JEDEC Standard A117

TDR1

Data Retention

100

Years

ILTH1

Latch Up

100 + IDD

mA

JEDEC Standard A103

JEDEC Standard 78

1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

TABLE 7-4:

WRITE TIMING PARAMETERS (VDD = 2.3 - 3.6V)

Symbol

Parameter

Maximum

Units

TSE

Sector-Erase

Minimum

25

ms

TBE

Block-Erase

25

ms

TSCE

Chip-Erase

50

ms

TPP1

Page-Program

1.5

ms

TPSID

Program Security-ID

1.5

ms

TWS

Write-Suspend Latency

25

TWpen

Write-Protection Enable Bit Latency

25

ms

1. Estimate for typical conditions less than 256 bytes: Programming Time (s) = 55 + (3.75 x # of bytes)

2015 Microchip Technology Inc.

DS20005119G-page 47

SST26VF064B / SST26VF064BA
8.0

AC CHARACTERISTICS

TABLE 8-1:

AC OPERATING CHARACTERISTICS (VDD1 = 2.3 - 3.6V)

Limits - 40 MHz

Symbol

Parameter

FCLK

Serial Clock Frequency

Min

Max

Limits - 80 MHz
Min

Max

40

Limits - 104 MHz

Min

80

25

Units

104

MHz

TCLK

Serial Clock Period

TSCKH

Serial Clock High Time

TSCKL

Serial Clock Low Time

11

5.5

4.5

ns

TSCKR2

Serial Clock Rise Time (slew rate)

0.1

0.1

0.1

V/ns

TSCKF2

Serial Clock Fall Time (slew rate)

0.1

0.1

0.1

V/ns

TCES3

CE# Active Setup Time

ns

TCEH3
TCHS3
TCHH3

CE# Active Hold Time

ns

CE# Not Active Setup Time

ns

CE# Not Active Hold Time

ns

TCPH

CE# High Time

25

12.5

12

ns

TCHZ

CE# High to High-Z Output

TCLZ

SCK Low to Low-Z Output

ns

11

12.5

Max

5.5

9.6

ns

4.5

19

12.5

ns

12

ns

THLS

HOLD# Low Setup Time

ns

THHS

HOLD# High Setup Time

ns

THLH

HOLD# Low Hold Time

ns

THHH

HOLD# High Hold Time

ns

THZ

HOLD# Low-to-High-Z Output

ns

TLZ

HOLD# High-to-Low-Z Output

ns

TDS

Data In Setup Time

ns

TDH

Data In Hold Time

ns

TOH

Output Hold from SCK Change

TV

Output Valid from SCK

1.
2.
3.
4.

8/5 4

8/5 4

ns
8/5 4

ns

Maximum operating frequency for 2.7-3.6V is 104 MHz and for 2.3-3.6V is 80 MHz.
Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
Relative to SCK.
30 pF/10 pF

FIGURE 8-1:

HOLD TIMING DIAGRAM

CE#
THHH

THHS

THLS

SCK
THZ

THLH
TLZ

SO

SI

HOLD#
25119 F43.1

DS20005119G-page 48

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
FIGURE 8-2:

SERIAL INPUT TIMING DIAGRAM

TCPH

CE#
TCHH

TCES

TCEH

TSCKF

TCHS

SCK
TDS
SIO[3:0]

TDH

TSCKR
LSB

MSB

25119 F70.1

FIGURE 8-3:

SERIAL OUTPUT TIMING DIAGRAM

CE#
TSCKH

TSCKL

SCK
TCLZ
SIO[3:0]

TOH

TCHZ
LSB

MSB
TV

TABLE 8-2:

25119 F25.1

RESET TIMING PARAMETERS

TR(i)

Parameter

Minimum

Maximum

Units

TR(o)

Reset to Read (non-data operation)

20

ns

TR(p)

Reset Recovery from Program or Suspend

100

TR(e)

Reset Recovery from Erase

ms

FIGURE 8-4:

RESET TIMING DIAGRAM

TCPH
CE#
MODE 3

MODE 3

MODE 3

CLK
MODE 0

SIO(3:0)

MODE 0

C1 C0

MODE 0

C3 C2
25119 F14.0

Note: C[1:0] = 66H; C[3:2] = 99H

2015 Microchip Technology Inc.

DS20005119G-page 49

SST26VF064B / SST26VF064BA
FIGURE 8-5:

AC INPUT/OUTPUT REFERENCE WAVEFORMS

VIHT
VHT
INPUT

VHT
REFERENCE POINTS

VLT

OUTPUT

VLT

VILT
25119 F28.0

AC test inputs are driven at VIHT (0.9VDD) for a logic 1 and VILT (0.1VDD) for a logic 0. Measurement reference points for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and
fall times (10% 90%) are <3 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test

DS20005119G-page 50

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
9.0

PACKAGING INFORMATION

9.1

Package Marking
8-Lead SOIJ (5.28 mm)

Example

26F064B
SM e3
1506343

8-Lead WDFN (5x6 mm)

XXXXXXXX
XXXXXXXX
YYWWNNN
8-Lead WDFN (6x8 mm)

XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
24-Ball TBGA (6x8 mm)

XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN

16-Lead SOIC (7.50 mm)

Example

26F064B
MF e3
1506343
Example

26F064B
MN e3
1506343

Example

26F064B
TD e3
1506343

Example

26F064B
SO e3
1506343

Continued

2015 Microchip Technology Inc.

DS20005119G-page 51

SST26VF064B / SST26VF064BA

1st Line Marking Codes

Part Number

SOIJ

WDFN

TBGA

SOIC

SST26VF064B

26F064B

26F064B

26F064B

26F064B

SST26VF064BA

26F064B

26F064B

26F064B

26F064B

Legend: XX...X
Y
YY
WW
NNN

e3

Part number or part number code

Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)

Note:

For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.

Note:

In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS20005119G-page 52

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
9.2

Package Diagrams

8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN]
Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D

(DATUM A)

(DATUM B)
E
NOTE 1
2X
0.15 C
1

2X

0.15 C

TOP VIEW
A1

0.10 C
A

SEATING
PLANE
A3

SIDE VIEW

0.08 C
0.10

D2

C A B

e
1

0.10

C A B

NOTE 1
E2

SEE DETAIL A
BOTTOM VIEW

8Xb
0.10
0.05

C A B
C

Microchip Technology Drawing C04-210B Sheet 1 of 2

2015 Microchip Technology Inc.

DS20005119G-page 53

SST26VF064B / SST26VF064BA

8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [WDFN]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Note:

(DATUM A)

e/2
e

DETAIL A

Notes:

Units
Dimension Limits
N
Number of Terminals
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
D
Overall Width
D2
Exposed Pad Width
E
Overall Length
E2
Exposed Pad Length
b
Terminal Width
L
Terminal Length
K
Terminal-to-Exposed-Pad

MIN

0.70
0.00

0.35
0.50
0.20

MILLIMETERS
NOM
8
1.27 BSC
0.75
0.02
0.20 REF
5.00 BSC
4.00 BSC
6.00 BSC
3.40 BSC
0.42
0.60
-

MAX

0.80
0.05

0.48
0.70
-

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-210B Sheet 2 of 2

DS20005119G-page 54

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA

8-Lead Very, Very Thin Small Outline No-Lead (MN) - 6x8 mm Body [WDFN]
(Also Called WSON)
Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

(DATUM A)

(DATUM B)
E
NOTE 1
2X
0.15 C
1

2X
0.15 C

TOP VIEW

A1

0.10 C

SEATING
PLANE
A3

0.08 C

SIDE VIEW
0.10

D2
1

C A B

NOTE 1

0.10

C A B

E2
(DATUM B)
(DATUM A)

8X K
b
e

BOTTOM VIEW

0.07
0.05

C A B
C

Microchip Technology Drawing C04-172A Sheet 1 of 2

2015 Microchip Technology Inc.

DS20005119G-page 55

SST26VF064B / SST26VF064BA

8-Lead Very, Very Thin Small Outline No-Lead (MN) - 6x8 mm Body [WDFN]
(Also Called WSON)
Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

Notes:

Units
Dimension Limits
N
Number of Terminals
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
E
Overall Width
E2
Exposed Pad Width
D
Overall Length
D2
Exposed Pad Length
b
Terminal Width
L
Terminal Length
K
Terminal-to-Exposed-Pad

MIN

0.70
0.00

0.35
0.45
0.20

MILLIMETERS
NOM
8
1.27 BSC
0.75
0.02
0.20 REF
8.00 BSC
6.00 BSC
6.00 BSC
4.80 BSC
0.40
0.50
-

MAX

0.80
0.05

0.45
0.55
-

1. Terminal 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-172A Sheet 2 of 2

DS20005119G-page 56

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2015 Microchip Technology Inc.

DS20005119G-page 57

SST26VF064B / SST26VF064BA

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005119G-page 58

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

2015 Microchip Technology Inc.

DS20005119G-page 59

SST26VF064B / SST26VF064BA

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS20005119G-page 60

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA

24-Ball Thin Profile Ball Grid Array (TD) - 6x8 mm Body [TBGA]
Note:

)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
;
 &
'

'$780%




(


;
 &

127(

&

'

'$780$

'

7239,(:
'(7$,/$
$

6($7,1*
3/$1(
&

$

6,'(9,(:
'
H'

H(

(



H(
'(7$,/%

H'
$ %

&

'

%277209,(:
0LFURFKLS7HFKQRORJ\'UDZLQJ&%6KHHWRI

2015 Microchip Technology Inc.

DS20005119G-page 61

SST26VF064B / SST26VF064BA

24-Ball Thin Profile Ball Grid Array (TD) - 6x8 mm Body [TBGA]
)RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ

Note:

 &
 &
6($7,1*
3/$1(
&

'(7$,/$

Q;E



& $ %
&

'(7$,/%

8QLWV
'LPHQVLRQ/LPLWV
Q
1XPEHURI6ROGHU%DOOV
H'
6ROGHU%DOO;3LWFK
H(
6ROGHU%DOO<3LWFK
2YHUDOO+HLJKW
$
%DOO+HLJKW
$
'
2YHUDOO/HQJWK
'
2YHUDOO6ROGHU%DOO<3LWFK
(
2YHUDOO:LGWK
2YHUDOO6ROGHU%DOO<3LWFK
(
E
6ROGHU%DOO:LGWK

0,1






0,//,0(7(56
120

%6&
%6&


%6&
%6&
%6&
%6&


0$;






Notes:
 %DOO$YLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD
 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0
%6&%DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV
5()5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\
 %DOOLQWHUIDFHWRSDFNDJHERG\PPQRPLQDOGLDPHWHU
0LFURFKLS7HFKQRORJ\'UDZLQJ&%6KHHWRI

DS20005119G-page 62

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 9-1:

REVISION HISTORY

Revision

Description

Date

Initial release of data sheet

Mar 2012

Revised figures 5-8-5-10on pages 18-20, figures 5-13-5-15 on pages

22-23, figures 5-25- 5-28 on pages 28- 31, figures 5-36-5-39 on pages
36-36, and figures 5-42-5-43 on pages 38-38
Updated the SFDP Table: Table 11-1 on page 66

Jun 2012

Apr 2013

Updated document to new format

Revised CPNs to reflect the new package codes
Updated package drawings to the new format
Revised Hardware Write Protection on page 8, Write-Suspend and
Write-Resume on page 29, and Lock-Down Block-Protection Register (LBPR) on page 37
Updated Power-Up Specifications on page 45

Updated Product Identification System on page 65

Updated package description for MF package from WSON to WDFN

Sep 2013

Updated SPI Dual I/O Read on page 22

Significantly revised Table 11-1 on page 66

Apr 2014

Revised Product Description on page 1

Added footnote to Table 7-4 on page 47
Added information for MN package 8-WDFN
Added Part Markings
Updated Package definitions for Product Identification System on
page 65

Feb 2015

Added 2.3-3.6V information throughout

Added Extended temperature range
Updated Product Description on page 1.

Sep 2015

2015 Microchip Technology Inc.

DS20005119G-page 63

SST26VF064B / SST26VF064BA
THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:

Users of Microchip products can receive assistance

through several channels:

Product Support Data sheets and errata,

application notes and sample programs, design
resources, users guides and hardware support
documents, latest software releases and archived
software
General Technical Support Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
Business of Microchip Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support

Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchips customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under Support, click on
Customer Change Notification and follow the
registration instructions.

DS20005119G-page 64

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
10.0

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.

Device

Tape/Reel
Indicator

Device:

XXX

Operating
Frequency

Temperature

XX
Package

SST26VF064B

= 64 Mbit, 2.5V/3.0V, SQI Flash Memory

WP#/Hold# pin Enable at power-up
SST26VF064BA = 64 Mbit, 2.5V/3.0V, SQI Flash Memory
WP#/Hold# pin Disable at power-up

Tape and
Reel Flag:

T
(blank)

= Tape and Reel

= Tube or Tray

Operating
Frequency:

104

= 104 MHz

Temperature:

I
V

= -40C to +85C
= -40C to +105C

Package:

MF
MN
SM
SO
TD

=
=
=
=
=

2015 Microchip Technology Inc.

WDFN (6mm x 5mm Body), 8-lead

WDFN (6mm x 8mm Body), 8-lead
SOIJ (5.28 mm Body), 8-lead
SOIC (7.50 mm Body), 16-lead
TBGA(>1mm pitch, <1.2mmheight,
6mm x 8 mm Body), 24-lead

Valid Combinations:
SST26VF064B-104I/MF
SST26VF064BT-104I/MF
SST26VF064BA-104I/MF
SST26VF064BAT-104I/MF
SST26VF064B-104V/MF
SST26VF064BT-104V/MF
SST26VF064B-104I/MN
SST26VF064BT-104I/MN
SST26VF064B-104V/MN
SST26VF064BT-104V/MN
SST26VF064B-104I/SM
SST26VF064BT-104I/SM
SST26VF064BA-104I/SM
SST26VF064BAT-104I/SM
SST26VF064B-104V/SM
SST26VF064BT-104V/SM
SST26VF064B-104I/SO
SST26VF064BT-104I/SO
SST26VF064BA-104I/SO
SST26VF064BAT-104I/SO
SST26VF064B-104V/SO
SST26VF064BT-104V/SO
SST26VF064B-104I/TD
SST26VF064BT-104I/TD

DS20005119G-page 65

SST26VF064B / SST26VF064BA
11.0

APPENDIX

TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (1 OF 16)

Bit Address

Data

Comments
SFDP Header

SFDP Header: 1st DWORD

00H

A7:A0

53H

01H

A15:A8

46H

02H

A23:A16

44H

03H

A31:A24

50H

SFDP Signature
SFDP Signature=50444653H

SFDP Header: 2nd DWORD

04H

A7:A0

06H

SFDP Minor Revision Number

05H

A15:A8

01H

SFDP Major Revision Number

06H

A23:A16

02H

Number of Parameter Headers (NPH)=3

07H

A31:A24

FFH

Unused. Contains FF and can not be changed.

Parameter Headers

JEDEC Flash Parameter Header:

08H

09H

A7:A0

A15:A8

1st

DWORD

00H

Parameter ID Least Significant Bit (LSB) Number.

When this field is set to 00H, it indicates a JEDEC-specified header. For
vendor-specified headers, this field must be set to the vendors manufacturer ID.

06H

Parameter Table Minor Revision Number

Minor revisions are either clarifications or changes that add parameters
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.

0AH

A23:A16

01H

Parameter Table Major Revision Number

Major revisions are changes that reorganize or add parameters to locations that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined discoverable parameters. Major Revision starts at 01H

0BH

A31:A24

10H

Parameter Table Length

Number of DWORDs that are in the Parameter table

JEDEC Flash Parameter Header: 2nd DWORD

0CH

A7:A0

30H

0DH

A15:A8

00H

0EH

A23:A16

00H

0FH

A31:A24

FFH

Parameter Table Pointer (PTP)

A 24-bit address that specifies the start of this headers Parameter table
in the SFDP structure. The address must be DWORD-aligned.
Parameter ID Most Significant Bit (MSB) Number

JEDEC Sector Map Parameter Header: 3rd DWORD

10H

11H

12H

A7:A0

A15:A8

A23:A16

DS20005119G-page 66

81H

Parameter ID LSB Number.

Sector map, function-specific table is assigned 81H

00H

Parameter Table Minor Revision Number

Minor revisions are either clarifications or changes that add parameters
in existing Reserved locations. Minor revisions do NOT change overall
structure of SFDP. Minor Revision starts at 00H.

01H

Parameter Table Major Revision Number

Major revisions are changes that reorganize or add parameters to locations that are NOT currently Reserved. Major revisions would require
code (BIOS/firmware) or hardware change to get previously defined discoverable parameters. Major Revision starts at 01H

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (2 OF 16)

Address

Bit Address

Data

Comments

13H

A31:A24

06H

Parameter Table Length

Number of DWORDs that are in the Parameter table

JEDEC Sector Map Parameter Header: 4th DWORD

14H

A7:A0

00H

15H

A15:A8

01H

16H

A23:A16

00H

17H

A31:A24

FFH

Parameter Table Pointer (PTP)

This 24-bit address specifies the start of this headers Parameter Table in
the SFDP structure. The address must be DWORD-aligned.
Parameter ID MSB Number

Microchip (Vendor) Parameter Header: 5th DWORD

18H

A7:A0

BFH

ID Number
Manufacture ID (vendor specified header)

19H

A15:A8

00H

Parameter Table Minor Revision Number

1AH

A23:A16

01H

Parameter Table major Revision Number, Revision 1.0

1BH

A31:A24

18H

Parameter Table Length, 24 Double Words

Microchip (Vendor) Parameter Header: 6th DWORD

1CH

A7:A0

00H

1DH

A15:A8

02H

1EH

A23:A16

00H

1FH

A31:A24

01H

Parameter Table Pointer (PTP)

This 24-bit address specifies the start of this headers Parameter Table in
the SFDP structure. The address must be DWORD-aligned.
Used to indicate bank number (vendor specific)
JEDEC Flash Parameter Table

JEDEC Flash Parameter Table:

1st

DWORD
Block/Sector Erase Sizes
00: Reserved
01: 4 KByte Erase
10: Reserved
11: Use this setting only if the 4 KByte erase is unavailable.

A1:A0

A2
30H

FDH

A3

Volatile Status Register

0:
Target flash has nonvolatile status bit. Write/Erase commands do
not require status register to be written on every power on.
1:
Target flash volatile status bits

A4

Write Enable Opcode Select for Writing to Volatile Status Register

0:
0x50. Enables a status register write when bit 3 is set to 1.
1:
0x06 Enables a status register write when bit 3 is set to 1.
Unused. Contains 111b and can not be changed

A7:A5
31H

Write Granularity
0:
Single-byte programmable devices or buffer programmable devices
with buffer is less than 64 bytes (32 Words).
1:
For buffer programmable devices when the buffer size is 64
bytes (32 Words) or larger.

A15:A8

2015 Microchip Technology Inc.

20H

4 KByte Erase Opcode

DS20005119G-page 67

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (3 OF 16)

Bit Address

Data

Supports (1-1-2) Fast Read

0:
(1-1-2) Fast Read NOT supported
1:
(1-1-2) Fast Read supported

A16

Address Bytes
Number of bytes used in addressing flash array read, write and erase
00: 3-Byte only addressing
01: 3- or 4-Byte addressing (e.g. defaults to 3-Byte mode; enters 4-Byte
mode on command)
10: 4-Byte only addressing
11: Reserved

A18:A17

Supports Double Transfer Rate (DTR) Clocking

Indicates the device supports some type of double transfer rate clocking.
0:
DTR NOT supported
1:
DTR Clocking supported

A19

A20

Supports (1-2-2) Fast Read

Device supports single input opcode, dual input address, and dual output
data Fast Read.
0:
(1-2-2) Fast Read NOT supported.
1:
(1-2-2) Fast Read supported.

A21

Supports (1-4-4) Fast Read

Device supports single input opcode, quad input address, and quad output data Fast Read
0:
(1-4-4) Fast Read NOT supported.
1:
(1-4-4) Fast Read supported.

A22

Supports (1-1-4) Fast Read

Device supports single input opcode & address and quad output data
Fast Read.
0:
(1-1-4) Fast Read NOT supported.
1:
(1-1-4) Fast Read supported.

32H

F1H

Unused. Contains 1 can not be changed.

A23
33H

Comments

A31:A24

JEDEC Flash Parameter Table:

Unused. Contains FF can not be changed

FFH
2nd

DWORD

34H

A7:A0

FFH

35H

A15:A8

FFH

36H

A23:A16

FFH

37H

A31:A24

03H

Flash Memory Density

SST26VF064B/064BA = 03FFFFFFH

JEDEC Flash Parameter Table: 3rd DWORD

A4:A0
38H

44H
A7:A5

39H

A15:A8

DS20005119G-page 68

EBH

(1-4-4) Fast Read Number of Wait states (dummy clocks) needed

before valid output
00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input
address phase instruction
Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode
Bits
010b: 2 dummy clocks (8 mode bits) are needed with a single input
opcode, quad input address and quad output data Fast Read Instruction.
(1-4-4) Fast Read Opcode
Opcode for single input opcode, quad input address, and quad output
data Fast Read.

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (4 OF 16)

Bit Address

Data

Comments

08H

(1-1-4) Fast Read Number of Wait states (dummy clocks) needed

before valid output
01000b: 8 dummy bits are needed with a single input opcode & address
and quad output data Fast Read Instruction

A20:A16
3AH

(1-1-4) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction

A23:A21

3BH

A31:A24

6BH

(1-1-4) Fast Read Opcode

Opcode for single input opcode & address and quad output data Fast
Read.

JEDEC Flash Parameter Table: 4th DWORD

A4:A0
3CH

08H

(1-1-2) Fast Read Number of Mode Bits

000b: No mode bits are needed with a single input opcode & address and
quad output data Fast Read Instruction

A7:A5
3DH

A15:A8

3BH

A20:A16
3EH

80H

A31:A24

(1-1-2) Fast Read Opcode

Opcode for single input opcode& address and dual output data Fast Read.
(1-2-2) Fast Read Number of Wait states (dummy clocks) needed
before valid output
00000b: 0 clocks of dummy cycle.
(1-2-2) Fast Read Number of Mode Bits (in clocks)
100b: 4 clocks of mode bits are needed

A23:A21
3FH

(1-1-2) Fast Read Number of Wait states (dummy clocks) needed

before valid output
01000b: 8 dummy clocks are needed with a single input opcode, address
and dual output data fast read instruction.

BBH

(1-2-2) Fast Read Opcode

Opcode for single input opcode, dual input address, and dual output data
Fast Read.

JEDEC Flash Parameter Table: 5th DWORD

Supports (2-2-2) Fast Read
Device supports dual input opcode& address and dual output data Fast
Read.
0:
(2-2-2) Fast Read NOT supported.
1:
(2-2-2) Fast Read supported.

A0

40H

A3:A1

FEH

A4

Reserved. Bits default to all 1s.

Supports (4-4-4) Fast Read
Device supports Quad input opcode & address and quad output data
Fast Read.
0:
(4-4-4) Fast Read NOT supported.
1:
(4-4-4) Fast Read supported.
Reserved. Bits default to all 1s.

A7:A5
41H

A15:A8

FFH

Reserved. Bits default to all 1s.

42H

A23:A16

FFH

Reserved. Bits default to all 1s.

43H

A31:A24

FFH

Reserved. Bits default to all 1s.

2015 Microchip Technology Inc.

DS20005119G-page 69

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (5 OF 16)

Bit Address

Data
th

JEDEC Flash Parameter Table: 6

Comments

DWORD

44H

A7:A0

FFH

Reserved. Bits default to all 1s.

45H

A15:A8

FFH

Reserved. Bits default to all 1s.

00H

(2-2-2) Fast Read Number of Wait states (dummy clocks) needed

before valid output
00000b: No dummy bit is needed

A20:A16
46H

(2-2-2) Fast Read Number of Mode Bits

000b: No mode bits are needed

A23:A21
47H

A31:A24

FFH

(2-2-2) Fast Read Opcode

Opcode for dual input opcode& address and dual output data Fast Read.
(not supported)

JEDEC Flash Parameter Table: 7th DWORD

48H

A7:A0

FFH

Reserved. Bits default to all 1s.

49H

A15:A8

FFH

Reserved. Bits default to all 1s.

44H

(4-4-4) Fast Read Number of Wait states (dummy clocks) needed

before valid output
00100b: 4 clocks dummy are needed with a quad input opcode &
address and quad output data Fast Read Instruction

A20:A16
4AH

(4-4-4) Fast Read Number of Mode Bits

010b: 2 clocks mode bits are needed with a quad input opcode & address
and quad output data Fast Read Instruction

A23:A21
4BH

A31:A24

0BH

(4-4-4) Fast Read Opcode

Opcode for quad input opcode/address, quad output data Fast Read

JEDEC Flash Parameter Table: 8th DWORD

4CH

A7:A0

0CH

Sector Type 1 Size

4 KByte, Sector/block size = 2N bytes

4DH

A15:A8

20H

Sector Type 1 Opcode

Opcode used to erase the number of bytes specified by Sector Type 1
Size

4EH

A23:A16

0DH

Sector Type 2 Size

8 KByte, Sector/block size = 2N bytes

4FH

A31:A24

D8H

Sector Type 2 Opcode

Opcode used to erase the number of bytes specified by Sector Type 2
Size

JEDEC Flash Parameter Table: 9th DWORD

50H

A7:A0

0FH

Sector Type 3 Size

32 KByte, Sector/block size = 2N bytes

51H

A15:A8

D8H

Sector Type 3 Opcode

Opcode used to erase the number of bytes specified by Sector Type 3
Size

52H

A23:A16

10H

Sector Type 4 Size

64 KByte, Sector/block size = 2N bytes

53H

A31:A24

D8H

Sector Type 4 Opcode

Opcode used to erase the number of bytes specified by Sector Type 4
Size

DS20005119G-page 70

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (6 OF 16)

Bit Address

Data

JEDEC Flash Parameter Table: 10

th

A7:A4

Erase Type 1 Erase, Typical time

Typical Time = (count +1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
A10:A9 units (00b:1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A8:A4 count = 18 = 10010b
A10:A9 unit = 1ms = 00b

A10:A8

A10:A8=001b

A15:A11

Erase Type 2 Erase, Typical time

Typical time = (count+1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
A17:A16 units (00b:1ms, 01b:16ms, 10b:128ms, 11b:1s)
A15:A11 count = 18 =10010b
A17:A16 unit = 1ms =00b

54H

56H

20H

91H

A17:A16

A17:A16=00b

A23:A18

Erase Type 3 Erase, Typical time

Typical time = (count+1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
A24:A23 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A22:A18 count = 18 = 10010b
A24:A23 unit = 1ms = 00b

48H

A24=0b

A24

57H

DWORD
Multiplier from typical erase time to maximum erase time
Maximum time = 2*(count + 1)*Typical erase time
Count = 0
A3:A0= 0000b

A3:A0

55H

Comments

A31:A25

24H

Erase Type 4 Erase, Typical time

Typical time = (count+1)*units
1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s
A31:A30 units (00b: 1ms, 01b: 16ms, 10b:128ms, 11b:1s)
A29:A25 count=18=10010b
A31:A30 unit = 1ms =00b

JEDEC Flash Parameter Table: 11th DWORD

A3:A0
58H

80H

Multiplier from Typical Program Time to Maximum Program Time

Maximum time = 2*(count +1)*Typical program time.
Count =0.
A3:A0=0000b

A7:A4

Page Size
Page size = 2N bytes.
N=8
A7:A4 =1000b

A13:A8

Page Program Typical time

Program time = (count+1)*units
A13 units (0b: 8s, 1b: 64s)
A12:A8 count=11 = 01111b
A13 unit = 64s = 1b

59H

6FH

A15:A14

2015 Microchip Technology Inc.

Byte Program Typical time, first byte

Typical time = (count+1)*units
A18 units (0b: 1s, 1b: 8s)
A17:A14 count = 5 = 0101b
A18 =8s=1b

DS20005119G-page 71

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (7 OF 16)

Bit Address

Data

A18:A16=101b

A18:A16

5AH

A23:A19

1DH

A30:A:24
5BH

Comments

81H

Byte Program Typical time, Additional Byte

Typical time = (count+1)*units
A23 units (0b: 1s, 1b: 8s)
A22:A19 count = 3 = 0011b
A23=1s=0b
Chip Erase Typical Time
Typical time = (count+1)*units
16ms to 512ms, 256ms to 8192ms, 4s to 128s, 64s to 2048s
A28:A24 count =1=00001b
A30:A29 units =16ms=00b
Reserved
A31=1b

A31

JEDEC Flash Parameter Table: 12th DWORD

Prohibited Operations During Program Suspend
xxx0b: May not initiate a new erase anywhere
xxx1b:May not initiate a new erase in the program suspended page size
xx0xb:May not initiate a new page program anywhere
xx1xb: May not initiate a new page program in program suspended page size.
x0xxb:Refer to the Data Sheet
x1xxb: May not initiate a read in the program suspended page size
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 1:0 are sufficient

A3:A0

5CH

EDH

A7:A4

Reserved = 1b

A8

Program Resume to Suspend Interval

The device requires this typical amount of time to make progress on the
program operation before allowing another suspend.
Interval =500s
Program resume to suspend interval =(count+1)*64s
A12:A9= 7 =0111b

A12:A9

5DH

0FH

A15:A13

DS20005119G-page 72

Prohibited Operation During Erase Suspend

xxx0b: May not initiate a new erase anywhere
xxx1b:May not initiate a new erase in the erase suspended page size
xx0xb:May not initiate a new page program anywhere
xx1xb: May not initiate a new page program in erase suspended
erase type size.
x0xxb:Refer to the Data Sheet
x1xxb: May not initiate a read in the erase suspended page size
0xxxb: Additional erase or program restrictions apply
1xxxb: The erase and program restrictions in bits 5:4 are sufficient

Suspend in-progress program max latency

Maximum time required by the flash device to suspend an in-progress
program and be ready to accept another command which accesses the
flash array.
Max latency = 25s
program max latency =(count+1)*units
units (00b:128ns, 01b:1s, 10b:8s, 11b:64s)
A17:A13= count = 24 = 11000b
A19:A18 = 1s =01b

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

5EH

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (8 OF 16)

Bit Address

Data

Comments

A19:A16

0111b

A23:A20

Erase Resume to Suspend Interval

The device requires this typical amount of time to make progress on the
erase operation before allowing another suspend.
Interval = 500s
Erase resume to suspend interval =(count+1)*64s
A23:A20= 7 =0111b

77H

A30:A24
5FH

38H

Suspend in-progress erase max latency

Maximum time required by the flash device to suspend an in-progress
erase and be ready to accept another command which accesses the
flash array.
Max latency = 25s
Erase max latency =(count+1)*units
units (00b:128ns, 01b:1s, 10b:8s, 11b:64s)
A28:A24= count = 24 = 11000b
A30:A29 = 1s =01b
Suspend/Resume supported
0:supported
1:not supported

A31

JEDEC Flash Parameter Table: 13th DWORD

A7:A0

30H

Program Resume Instruction

61H

A15:A8

B0H

Program Suspend Instruction

62H

A23:A16

30H

Resume Instruction

63H

A31:A24

B0H

Suspend Instruction

60H

JEDEC Flash Parameter Table:

14th

64H

65H
66H

A7:A2
A14:A8
A15
A22:A16
A23

F7H

FFH

A31

Status Register Polling Device Busy

111101b: Use of legacy polling is supported by reading the status register
with 05h instruction and checking WIP bit [0] (0=ready, 1=busy)
Exit Deep Power-down to next operation delay
Exit Power-down Instruction

FFH

Enter Power-down instruction

FFH

Deep Power-down Supported

0:supported
1:not supported

A30:A24
67H

DWORD
Reserved = 11b

A1:A0

JEDEC Flash Parameter Table: 15th DWORD

A3:A0
68H

29H
A7:A4

2015 Microchip Technology Inc.

4-4-4 mode disable sequences

Xxx1b: issue FF instruction
1xxxb: issue the Soft Reset 66/99 sequence.
4-4-4 mode enable sequences
X_xx1xb: issue instruction 38h

DS20005119G-page 73

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

69H

6AH

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (9 OF 16)

Bit Address

Data

Comments

A8

4-4-4 mode enable sequences

A8 = 0

A9

0-4-4 mode supported

0:not supported
1:supported

C2H

A15:A10

0-4-4 Mode Exit Method

X1_xxxx:Mode Bit[7:0] Not= AXh
1x_xxxx Reserved = 1

A19:A16

0-4-4 Mode Entry Method

X1xxb: M[7:0]=AXh
1xxxb:Reserved =1

A22:A20

Quad Enable Requirements (QER)

101b: Quad Enable is bit 1 of the configuration register.

5CH

HOLD and Reset Disable

0:feature is not supported

A23
6BH

A31:A24

JEDEC Flash Parameter Table:

6C

A6:A0

Reserved bits = 0xFF

FFH
16th

DWORD

F0H

Reserved =1b

A7
A13:A8
6D

Volatile or Non-Volatile Register and Write Enable Instructions for

Status Register 1
Xx1_xxxxb:Status Register 1 contains a mix of volatile and non-volatile
bits. The 06h instruction is used to enable writing to the register.
X1x_xxxxb: Reserved = 1
1xx_xxxxb: Reserved = 1

30H

Soft Reset and Rescue Sequence Support

X1_xxxxb: reset enable instruction 66h is issued followed by reset
instruction 99h.
1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences.
Exit 4-Byte Addressing
Not supported

A15:A14
6E

A23:A16

C0H

Exit 4-Byte Addressing

Not supported
A23 and A22 are Reserved bits which are = 1

6F

A31:A24

80H

Enter 4-Byte Addressing

Not supported
1xxx_xxxx: Reserved = 1

JEDEC Sector Map Parameter Table

100H

A7:A0

FFH

Sector Map
A7:A2=Reserved=111111b
A1=Descriptor Type = Map=1b
A0=Last map = 1b

101H

A15:A8

00H

Configuration ID = 00h

102H

A23:A16

04H

Region Count = 5 Regions

103H

A31:A24

FFH

Reserved = FFh

104H

A7:A0

F3H

Region 0 supports 4Kbyte erase and 8Kbyte erase

A3:A0=0011b
A7:A4=Reserved=1111b

DS20005119G-page 74

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (10 OF 16)

Bit Address

Data

Comments
Region 0 Size
4 * 8Kbytes = 32Kbytes
Count=32Kbytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh

105H

A15:A8

7FH

106H

A23:A16

00H

107H

A31:A24

00H

108H

A7:A0

F5H

Region 1 supports 4Kbyte erase and 32Kbyte erase

A3:A0 = 0101b
A7:A4=Reserved = 1111b
Region 1 size
1 * 32Kbytes = 32Kbytes
Count=32Kbytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh

109H

A15:A8

7FH

10AH

A23:A16

00H

10BH

A31:A24

00H

10CH

A7:A0

F9H

Region 2 supports 4 KByte erase and 64 KByte erase

A3:A0 = 1001b
A7:A4=Reserved = 1111b
Region 2 size
126 * 64 KBytes = 8064 KBytes
Count=8064Kbytes/256 bytes= 32256
Value = count -1 =32255
A31:A8 = 007DFFh

10DH

A15:A8

FFH

10EH

A23:A16

7DH

10FH

A31:A24

00H

110H

A7:A0

F5H

Region 3 supports 4 KByte erase and 32 KByte erase

A3:A0 = 0101b
A7:A4=Reserved = 1111b
Region 3 size
1 * 32 KBytes = 32 KBytes
Count=32 KBytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh

111H

A15:A8

7FH

112H

A23:A16

00H

113H

A31:A24

00H

114H

A7:A0

F3H

Region 4 supports 4 KByte erase and 8 KByte erase

A3:A0=0011b
A7:A4=Reserved=1111b
Region 4 Size
4 * 8 KBytes = 32 KBytes
Count=32Kbytes/256 bytes= 128
Value = count -1 =127
A31:A8 = 00007Fh

115H

A15:A8

7FH

116H

A23:A16

00H

117H

A31:A24

00H

2015 Microchip Technology Inc.

DS20005119G-page 75

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (11 OF 16)

Bit Address

Data

Comments

SST26VF064B/064BA (Vendor) Parameter Table

SST26VF064B/064BA Identification
200H

A7:A0

BFH

Manufacturer ID

201H

A15:A8

26H

Memory Type

202H

A23:A16

43H

Device ID
SST26VF064B/064BA=43H

203H

A31:A24

FFH

Reserved. Bits default to all 1s.

SST26VF064B/064BA Interface
Interfaces Supported
000: SPI only
001: Power up default is SPI; Quad can be enabled/disabled
010: Reserved
:
:
111: Reserved

A2:A0

A3
204H

B9H

Supports Enable Quad

0:
not supported
1:
supported
Supports Hold#/Reset# Function
000: Hold#
001: Reset#
010: HOLD/Reset#
011: Hold# & I/O when in SQI(4-4-4), 1-4-4 or 1-1-4 Read

A6:A4

A7

Supports Software Reset

0:
not supported
1:
supported

A8

Supports Quad Reset

0:
not supported
1:
supported

A10:A9

Reserved. Bits default to all 1s

A13:A11

Byte-Program or Page-Program (256 Bytes)

011: Byte Program/Page Program in SPI and Quad Page Program once
Quad is enabled

205H

5FH
A14

Program-Erase Suspend Supported

0:
Not Supported
1:
Program/Erase Suspend Supported

A15

Deep Power-Down Mode Supported

0:
Not Supported
1:
Deep Power-Down Mode Supported

DS20005119G-page 76

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

206H

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (12 OF 16)

Bit Address

Data

A16

OTP Capable (Security ID) Supported

0:
not supported
1:
supported

A17

Supports Block Group Protect

0:
not supported
1:
supported

A18

FDH

Reserved. Bits default to all 1s.

A23:A20
A31:A24

Supports Independent Block Protect

0:
not supported
1:
supported
Supports Independent non Volatile Lock (Block or Sector becomes
OTP)
0:
not supported
1:
supported

A19

207H

Comments

FFH

Reserved. Bits default to all 1s.

VDD Minimum Supply Voltage
2.3V (F230H)

208H

A7:A0

30H

209H

A15:A8

F2H

20AH

A23:A16

60H

20BH

A31:A24

F3H

20CH

A7:A0

32H

20DH

A15:A8

FFH

Reserved. Bits default to all 1s.

20EH

A23:A16

0AH

Typical time out for page program: 1.0ms (xxH*(0.1ms)

20FH

A31:A24

12H

Typical time out for Sector-Erase/Block-Erase: 18 ms

Typical time out for Sector/Block-Erase is in ms. Represented by conversion
of the actual time from the decimal to hexadecimal number.

210H

A7:A0

23H

Typical time out for Chip-Erase: 35 ms

Typical time out for Chip-Erase is in ms. Represented by conversion of
the actual time from the decimal to hexadecimal number.

211H

A15:A8

46H

Max. time out for Byte-Program: 70 s

Typical time out for Byte Program is in s. Represented by conversion of
the actual time from the decimal to hexadecimal number.

212H

A23:A16

FFH

Reserved. Bits default to all 1s.

213H

A31:A24

0FH

Max time out for Page-Program: 1.5ms.

Typical time out for Page Program in xxH * (0.1ms) ms

214H

A7:A0

19H

Max. time out for Sector Erase/Block Erase: 25ms.

Max time out for Sector/Block Erase in ms

215H

A15:A8

32H

Max. time out for Chip Erase: 50ms.

Max time out for Chip Erase in ms.

216H

A23:A16

0FH

Max. time out for Program Security ID: 1.5 ms

Max time out for Program Security ID in xxH*(0.1ms) ms

217H

A31:A24

19H

Max. time out for Write-Protection Enable Latency: 25 ms

Max time out for Write-Protection Enable Latency is in ms. Represented by conversion of the actual time from the decimal to hexadecimal number.

218H

A23:A16

19H

Max. time Write-Suspend Latency: 25 s

Max time out for Write-Suspend Latency is in s. Represented by conversion of
the actual time from the decimal to hexadecimal number.

219H

A31:A24

FFH

Max. time to Deep Power-Down

0FFH = Reserved

2015 Microchip Technology Inc.

VDD Maximum Supply Voltage

3.6V (F360H)
Typical time out for Byte-Program: 50 s
Typical time out for Byte Program is in s. Represented by conversion of
the actual time from the decimal to hexadecimal number.

DS20005119G-page 77

SST26VF064B / SST26VF064BA
TABLE 11-1:

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (13 OF 16)

Address

Bit Address

Data

Comments

21AH

A23:A16

FFH

Max. time out from Deep Power-Down mode to Standby mode

0FFH = Reserved

21BH

A31:A24

FFH

Reserved. Bits default to all 1s.

21CH

A23:A16

FFH

Reserved. Bits default to all 1s.

21DH

A31:A24

FFH

Reserved. Bits default to all 1s.

21EH

A23:A16

FFH

Reserved. Bits default to all 1s.

21FH

A31:A24

FFH

Reserved. Bits default to all 1s.

00H

No Operation

Supported Instructions
220H

A7:A0

221H

A15:A8

66H

Reset Enable

222H

A23:A16

99H

Reset Memory

223H

A31:A24

38H

Enable Quad I/O

224H

A7:A0

FFH

Reset Quad I/O

225H

A15:A8

05H

Read Status Register

226H

A23:A16

01H

Write Status Register

227H

A31:A24

35H

Read Configuration Register

228H

A7:A0

06H

Write Enable

229H

A15:A8

04H

Write Disable

22AH

A23:A16

02H

Byte Program or Page Program

22BH

A31:A24

32H

SPI Quad Page Program

22CH

A7:A0

B0H

Suspends Program/Erase

22DH

A15:A8

30H

Resumes Program/Erase

22EH

A23:A16

72H

Read Block-Protection register

22FH

A31:A24

42H

Write Block Protection Register

230H

A7:A0

8DH

Lock Down Block Protection Register

231H

A15:A8

E8H

non-Volatile Write-Lock Down Register

232H

A23:A16

98H

Global Block Protection Unlock

233H

A31:A24

88H

Read Security ID

234H

A7:A0

A5H

Program User Security ID Area

235H

A15:A8

85H

Lockout Security ID Programming

236H

A23:A16

C0H

Set Burst Length

237H

A31:A24

9FH

JEDEC-ID

238H

A7:A0

AFH

Quad J-ID

239H

A15:A8

5AH

SFDP

23AH

A23:A16

FFH

Deep Power-Down Mode

FFH = Reserved

23BH

A31:A24

FFH

Release Deep Power-Down Mode

FFH = Reserved

A4:A0
23CH

06H

(1-4-4) SPI nB Burst with Wrap Number of Mode Bits

000b: Set Mode bits are not supported

A7:A5
23DH

A15:A8

DS20005119G-page 78

(1-4-4) SPI nB Burst with Wrap Number of Wait states (dummy

clocks) needed before valid output
00110b: 6 clocks of dummy cycle

ECH

(1-4-4) SPI nB Burst with Wrap Opcode

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (14 OF 16)

Bit Address

Data

Comments

06H

(4-4-4) SQI nB Burst with Wrap Number of Wait states (dummy

clocks) needed before valid output
00110b: 6 clocks of dummy cycle

A20:A16
23EH

(4-4-4) SQI nB Burst with Wrap Number of Mode Bits

000b: Set Mode bits are not supported

A23:A21
23FH

A31:A24

0CH

(4-4-4) SQI nB Burst with Wrap Opcode

00H

(1-1-1) Read Memory Number of Wait states (dummy clocks) needed

before valid output
00000b: Wait states/dummy clocks are not supported.

A4:A0
240H

(1-1-1) Read Memory Number of Mode Bits

000b: Mode bits are not supported,

A7:A5
241H

A15:A8

03H

(1-1-1) Read Memory Opcode

08H

(1-1-1) Read Memory at Higher Speed Number of Wait states

(dummy clocks) needed before valid output
01000: 8 clocks (8 bits) of dummy cycle

A20:A16
242H

(1-1-1) Read Memory at Higher Speed Number of Mode Bits

000b: Mode bits are not supported,

A23:A21
A31:A24

0BH

(1-1-1) Read Memory at Higher Speed Opcode

244H

A7:A0

FFH

Reserved. Bits default to all 1s.

245H

A15:A8

FFH

Reserved. Bits default to all 1s.

246H

A23:A16

FFH

Reserved. Bits default to all 1s.

247H

A31:A24

FFH

Reserved. Bits default to all 1s.

A7:A0

FFH

Security ID size in bytes

Example: If the size is 2 KBytes, this field would be 07FFH

243H

Security ID
248H

Security ID Range
249H

A15:A8

07H

Unique ID
(Pre-programmed at factory)

0000H - 0007H

User Programmable

0008H - 07FFH

24AH

A23:A16

FFH

Reserved. Bits default to all 1s.

24BH

A31:A24

FFH

Reserved. Bits default to all 1s.

Memory Organization/Block Protection Bit Mapping 1

24CH

A7:A0

02H

Section 1: Sector Type Number:

Sector type in JEDEC Parameter Table (bottom, 8 KByte)

24DH

A15:A8

02H

Section 1 Number of Sectors

Four of 8KB block (2n)

FFH

Section 1 Block Protection Bit Start

((2m) +1)+ c, c=FFH or -1, m= 7 for 64 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.

24EH

A23:A16

2015 Microchip Technology Inc.

DS20005119G-page 79

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (15 OF 16)

Bit Address

Data

Comments

24FH

A31:A24

06H

Section 1 (bottom) Block Protection Bit End

((2m) +1)+ c, c=06H or 6, m= 7 for 64 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.

250H

A7:A0

03H

Section 2: Sector Type Number

Sector type in JEDEC Parameter Table (32KB Block)

251H

A15:A8

00H

Section 2 Number of Sectors

One of 32KB Block (2n, n=0)

FDH

Section 2 Block Protection Bit Start

((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.

252H

A23:A16

253H

A31:A24

FDH

Section 2 Block Protection Bit End

((2m) +1)+ c, c=FDH or -3, m= 7 for 64 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.

254H

A7:A0

04H

Section 3: Sector Type Number

Sector type in JEDEC Parameter Table (64KB Block)

255H

A15:A8

07H

Section 3 Number of Sectors

126 of 64KB Block (2m-2, m= 7 for 64 Mb)

256H

A23:A16

00H

Section 3 Block Protection Bit Start

Section 3 Block Protection Bit starts at 00H

257H

A31:A24

FCH

Section 3 Block Protection Bit End

((2m) +1)+ c, c=FCH or -4, m= 7 for 64 Mb

258H

A7:A0

03H

Section 4: Sector Type Number

Sector type in JEDEC Parameter Table (32KB Block)

259H

A15:A8

00H

Section 4 Number of Sectors

One of 32KB Block (2n, n=0)

FEH

Section 4 Block Protection Bit Start

((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.

25AH

A23:A16

25BH

A31:A24

FEH

Section 4 Block Protection Bit End

((2m) +1)+ c, c=FEH or -2, m= 7 for 64 Mb
The most significant (left-most) bit indicates the sign of the integer; it is
sometimes called the sign bit. If the sign bit is zero, then the number is
greater than or equal to zero, or positive. If the sign bit is one then the
number is less than zero or negative.

25CH

A7:A0

02H

Section 5 Sector Type Number:

Sector type in JEDEC Parameter Table (top, 8 KByte)

25DH

A15:A8

02H

Section 5 Number of Sectors

Four of 8KB block (2n)

DS20005119G-page 80

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
TABLE 11-1:
Address

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (CONTINUED) (16 OF 16)

Bit Address

25EH

A23:A16

25FH

A31:A24

Data

Comments

07H

Section 5 Block Protection Bit Start

((2m) +1)+ c, c=07H or 7, m= 7 for 64 Mb
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.

0EH

Section 5 (Top) Block Protection Bit End

(((2m) +1)+ c, c=0EH or 14, m= 7 for 64 Mb,
Address bits are Read Lock bit locations and Even Address bits are Write
Lock bit locations. The most significant (left-most) bit indicates the sign of
the integer; it is sometimes called the sign bit. If the sign bit is zero, then
the number is greater than or equal to zero, or positive. If the sign bit is
one then the number is less than zero or negative.

1. See Mapping Guidance Details for more detailed mapping information

11.1

Mapping Guidance Details

The SFDP Memory Organization/Block Protection Bit

Mapping defines the memory organization including
uniform sector/block sizes and different contiguous
sectors/blocks sizes. In addition, this bit defines the

TABLE 11-2:

number of these uniform and different sectors/blocks

from address 000000H to the full range of Memory and
the associated Block Locking Register bits of each sector/block.
Each major Section is defined as follows:

SECTION DEFINITION

Major Section X

Section X: Sector Type Number

Section X: Number of Sectors
Section X: Block-Protection Register Bit Start Location
Section X: Block-Protection Register Bit End Location

A Major Section consists of Sector Type Number, Number of Sector of this type, and the Block-Protection Bit
Start/End locations. This is tied directly to JEDEC Flash
Parameter Table Sector Size Type (in 7th DWORD and
8th DWORD section). Note that the contiguous 4KByte
Sectors across the full memory range are not included
on this section because they are not defined in the
JEDEC Flash Parameter Table Sector Size Type section. Only the sectors/blocks that are dependently tied
with the Block-Protection Register bits are defined. A
major section is a partition of contiguous same-size
sectors/blocks. There will be several Major Sections as
you dissect across memory from 000000h to the full
range. Similar sector/block size that re-appear may be
defined as a different Major Section.

11.1.1

tor Type 4, size is represented by 04H. Contiguous

Same Sector Type # Size can re-emerge across the
memory range and this Sector Type # will indicate that
it is a separate/independent Major Section from the
previous contiguous sectors/blocks.

11.1.2

NUMBER OF SECTORS

Number of Sectors represents the number of contiguous sectors/blocks with similar size. A formula calculates the contiguous sectors/blocks with similar size.
Given the sector/block size, type, and the number of
sectors, the address range of these sectors/blocks can
be determined along with specific Block Locking Register bits that control the read/write protection of each
sectors/blocks.

SECTOR TYPE NUMBER

Sector Type Number is the sector/block size typed

defined in JEDEC Flash Parameter Table: SFDP
address locations 4CH, 4EH, 50H, and 52H. For SFDP
address location 4CH, which is Sector Type 1, the size
is represented by 01H; SFDP address location 4EH,
Sector Type 2, size is represented by 02H; SFDP
address location 50H, Sector Type 3, size is represented by 03H; and SFDP address location 52H, Sec-

2015 Microchip Technology Inc.

DS20005119G-page 81

SST26VF064B / SST26VF064BA
11.1.3

BLOCK-PROTECTION REGISTER
BIT START LOCATION (BPSL)

Block-Protection Register Bit Start Location (BPSL)

designates the start bit location in the Block-Protection
Register where the first sector/block of this Major Section begins. If the value of BPSL is 00H, this location is
the 0 bit location. If the value is other than 0, then this
value is a constant value adder (c) for a given formula,
(2m + 1) + (c). See Memory Configuration.
From the initial location, there will be a bit location for
every increment by 1 until it reaches the Block Protection Register Bit End Location (BPEL). This number
range from BPSL to BPEL will correspond to, and be
equal to, the number of sectors/blocks on this Major
Section.

TABLE 11-3:

11.1.4

BLOCK PROTECTION REGISTER

BIT END LOCATION (BPEL)

Block Protection Register Bit End Location designates

the end bit location in the Block Protection Register bit
where the last sector/block of this Major Section ends.
The value in this field is a constant value adder (c) for
a given formula or equation, (2m + 1) + (c). See Memory Configuration

11.1.5

MEMORY CONFIGURATION

For the SST26VF064B/064BA family, the memory configuration is setup with different contiguous block sizes
from bottom to the top of the memory. For example,
starting from bottom of memory it has four 8KByte
blocks, one 32KByte block, x number of 64KByte
blocks depending on memory size, then one 32KByte
block, and four 8KByte block on the top of memory. See
Table 11-3.

MEMORY BLOCK DIAGRAM REPRESENTATION

8 KByte Bottom Block

(from 000000H)

Section 1: Sector Type Number

Section 1: Number of Sectors
Section 1: Block-Protection Register Bit Start Location
Section 1: Block-Protection Register Bit End Location

32 KByte

Section 2: Sector Type Number

Section 2: Number of Sectors
Section 2: Block-Protection Register Bit Start Location
Section 2: Block-Protection Register Bit End Location

64 KByte

Section 3: Sector Type Number

Section 3: Number of Sectors
Section 3: Block-Protection Register Bit Start Location
Section 3: Block-Protection Register Bit End Location

32 KByte

Section 4: Sector Type Number

Section 4: Number of Sectors
Section 4: Block-Protection Register Bit Start Location
Section 4: Block-Protection Register Bit End Location

8 KByte (Top Block)

Section 5: Sector Type Number

Section 5: Number of Sectors
Section 5: Block-Protection Register Bit Start Location
Section 5: Block-Protection Register Bit End Location

Classifying these sector/block sizes via the Sector

Type derived from JEDEC Flash Parameter Table:
SFDP address locations 4EH, 50H, and 52H is as follows:
8KByte Blocks are classified as Sector Type 2
(@4EH of SFDP)
32KByte Blocks are classified as Sector Type 3
(@50H of SFDP)
64KByte Blocks are classified as Sector Type 4
(@52H of SFDP)

DS20005119G-page 82

For the Number of Sectors associated with the contiguous sectors/blocks, a formula is used to determine the
number of sectors/blocks of these Sector Types:
8KByte Block (Type 2) is calculated by 2n. n is a byte.
32KByte Block (Type 3) is calculated by 2n. n is a
byte.
64KByte Block (Type 4) is calculated by (2m - 2). m
can either be a 4, 5, 6, 7 or 8 depending on the memory size. This m field is going to be used for the
64KByte Block Section and will also be used for the
Block Protection Register Bit Location formula.

2015 Microchip Technology Inc.

SST26VF064B / SST26VF064BA
m will have a constant value for specific densities and
is defined as:

8Mbit = 4
16Mbit = 5
32Mbit = 6
64Mbit = 7
128Mbit = 8

Block Protect Register Start/End Bits are mapped in the

SFDP by using the formula (2m + 1) + (c). m is a constant value that represents the different densities from
8Mbit to 128Mbit (used also in the formula calculating
number of 64Kbyte Blocks above). The values that are

TABLE 11-4:

going to be placed in the Block Protection Bit Start/End

field table are the constant value adder (c) in the formula and are represented in twos compliment except
when the value is 00H. If the value is 00H, this location
is the 0 bit location. If the value is other than 0, then this
is a constant value adder (c) that will be used in the formula. The most significant (left most) bit indicates the
sign of the integer; it is sometimes called the sign bit.
If the sign bit is zero, then the number is greater than or
equal to zero, or positive. If the sign bit is one, then the
number is less than zero, or negative.
See Table 11-4 for an example of this formula.

BPSL/BPEL EQUATION WITH ACTUAL CONSTANT ADDER DERIVED FROM THE

FORMULA (2M + 1) + (C)

Block Size

8 Mbit to 128 Mbit

m

Comments

8 KByte (Type 2) Bottom

BPSL = (2 + 1) + 0FFH
BPEL = (2m + 1) + 04H

0FFH = -1; 06H = 6

Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.

32 KByte (Type 3)

BPSL = BPEL= (2m + 1) + 0FDH

0FDH= -3

64 KByte (Type 4)

BPSL = 00H
BPEL = (2m + 1) + 0FCH

00H is Block-Protection Register bit 0

location; 0FCH = -4

32 KByte (Type 3)

BPSL = BPEL= (2m + 1) + 0FEH

0FEH=-2

8 KByte (Type 2) Top

BPSL = (2m + 1) + 07H

BPEL = (2m + 1) + 0EH

07H = 7; 0EH = 14
Odd address bits are Read-Lock bit
locations and even address bits are
Write-Lock bit locations.

2015 Microchip Technology Inc.

DS20005119G-page 83

Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.

Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
2015, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-63277-731-7

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==
2015 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS20005119G-page 84

Worldwide Sales and Service

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DS20005119G-page 85