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Experiment-8: Aim: Design, Synthesis and Simulation of Binary To Excess3 Code Converter. Theory

This document describes the design, synthesis, and simulation of a binary to excess-3 code converter. It explains that excess-3 coding works by adding 3 to each decimal digit and converting the sum to binary coded decimal. A logic diagram and truth table are provided showing the binary to excess-3 conversion. VHDL code is given for an entity that takes in a 4-bit binary number and outputs the corresponding 4-bit excess-3 code. The code uses if-else statements to map each binary input to the correct excess-3 output. Simulation results confirming the correct operation are also shown.

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Ankit Kumar
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119 views3 pages

Experiment-8: Aim: Design, Synthesis and Simulation of Binary To Excess3 Code Converter. Theory

This document describes the design, synthesis, and simulation of a binary to excess-3 code converter. It explains that excess-3 coding works by adding 3 to each decimal digit and converting the sum to binary coded decimal. A logic diagram and truth table are provided showing the binary to excess-3 conversion. VHDL code is given for an entity that takes in a 4-bit binary number and outputs the corresponding 4-bit excess-3 code. The code uses if-else statements to map each binary input to the correct excess-3 output. Simulation results confirming the correct operation are also shown.

Uploaded by

Ankit Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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CHANDIGARH UNIVERSITY

EXPERIMENT-8
Aim: Design, synthesis and simulation of Binary to Excess3 code Converter.
Theory: To convert any decimal numbers into its excess- 3 form add 3 to each decimal digit
and then convert the sum to a BCD number As weights are not assigned, it is a kind of nonweighted codes.

Logic Diagram:

Truth Table:
Binary

Excess 3

0000
0001
0010
0011
0100
0101
0110
0111
1000
1001

0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity binary2excess is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);

Jashanpreet Sandhu
12BEC1092
ECE-II

CHANDIGARH UNIVERSITY
ex : out STD_LOGIC_VECTOR (3 downto 0));
end binary2excess;
architecture Behavioral of binary2excess is
begin
process(b)
begin
if(b="0000") then
ex<="0011";
elsif(b="0001")then
ex<="0100";
elsif(b="0010")then
ex<="0101";
elsif(b="0011")then
ex<="0110";
elsif(b="0100")then
ex<="0111";
elsif(b="0101")then
ex<="1000";
elsif(b="0110")then
ex<="1001";
elsif(b="0111")then
ex<="1010";
elsif(b="1000")then
ex<="1011";
elsif(b="1001")then
ex<="1100";
else
ex<="ZZZZ";
end if;
end process;
end Behavioral;

Simulation Results:

Jashanpreet Sandhu
12BEC1092
ECE-II

CHANDIGARH UNIVERSITY

Jashanpreet Sandhu
12BEC1092
ECE-II

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