PHY Validation of Thunderbolt & DisplayPort

Thunderbolt Overview
High Speed Data Bus for PCs
Brought to market by Intel/Apple in 2011
Interoperable with DisplayPort

Thunderbolt signaling is dual NRZ (64/66b Encoded)

10.3125 Gb/s data rate
It utilizes SFP+ technology with 2 diff Tx and Rx pairs.

Thunderbolt Electrical Validation

Tektronix DPOJET
Thunderbolt .5
7 MOI
Manual Test

Thunderbolt (.5
7 Spec
Revision)
10.3125Gbps

Thunderbolt
(future Interop)

Display Port DP1.2

RBR (1.6Gbps),

HBR (2.7Gbps)

HBR2 (5.4Gbps)

DP++
Tektronix DP12
Full test
automation

Dual Port Device Compliance Test Summary

Physical Layer Testing

1.
2.
3.
4.
5.
6.

(Rev 0.7 Spec)

TBT Transmitter MOI
TBT Receiver MOI
TBT Return Loss MOI
DP Source MOI
DP++ (HDMI) Source MOI
Power Delivery MOI

Functional Testing
Thunderbolt Functional CTS
Rev 3.0.1
1. ROM Validation
2. Basic Device Functionality
3. EFI
4. Downstream Device Functionality
5. Downstream Display Functionality
6. Extended Test Functionality
7. Complex Topology
8. DUT Specific Verification
9. Negative Testing
10. Firmware Update Validation

CTS Compliance Test Specification

MOI Method of Implementation (Test Procedure)
4

Single Port Device Compliance Test Summary

Physical Layer Testing Functional Testing

(Rev 0.7 Spec)
1. TBT Transmitter MOI
2. TBT Receiver MOI
3. TBT Return Loss MOI
4. Power Consumption

Thunderbolt Functional CTS

Rev 2.4 (IBL 488434)
1.
2.
3.
4.
5.
6.

ROM Validation
Basic Device Functionality
EFI
DUT Specific Verification
Negative Testing
Firmware Update Validation

CTS Compliance Test Specification

MOI Method of Implementation (Test Procedure)
5

HDMI Test Setup

DSA70804C or higher
SMA Differential Probes
Provides 3.3V bias

HT3 HDMI Compliance SW

Mac or equivalent tool used

to control downstream port
on a 2 port device
Both ports tested

Example of HDMI Passing Results

Automated Thunderbolt Tx Testing

Recommended Equipment

DPO/DSA/MSO71604 ( 16 GHz BW)

BSA125C (crosstalk source)

Option DJA (DPOJET)

Option TBT-TX (TekExpress)

TF-TB-TPA-P (Plug fixture) &

TBT-TPA-UH (port microcontroller)

Option TBT-TX
Compliance Automation Software
Automates scope setup & compliance
measurements per the Tek Thunderbolt MOI
Fast test execution
Simultaneous two lane testing
Automated DUT state control for devices
User-selectable tests
Creates complete test report

Thunderbolt Transmitter Testing

Step 1: Select Measurement Setup

Thunderbolt Transmitter Testing

Step 2: Select Measurements (total 18 measurements)

Thunderbolt Transmitter Testing

Step 3: Configure Acquisitions

Thunderbolt Transmitter Testing

Step 4: Start Tests and Generate Report

Test Challenge: De-Embedding

Transmitter Compliance Testing

Host/device compliance point at TP1 (mated plug/receptacle)
De-embedding required to remove fixture effects

S-Parameters are acquired from calibration fixture

Signal at TP1

Measured Signal

DUT

Test Fixture
TP1

15

10/31/2012

Apply Sparameters

Signal with Fixture

Effects Removed

Thunderbolt Fixture De-Embed results

Test Challenge: Crosstalk

Measuring Bounded Uncorrelated Jitter (BUJ) is Critical

Interconnect and board layout technology is advancing and the
greatest area of focus is in reducing the insertion loss and Signal-toCrosstalk ratio.

The implications of complex channel interaction can be observed and

identified by examining the type and amount of BUJ.
There is a strong Causeand-Effect relationship between Crosstalk
and BUJ which often gets classified as Random if special steps are
not observed.

BUJ in real time jitter analysis

BUJ in Thunderbolt example

New BUJ Decomposition Legacy Decomposition

TJ@BER1, Math1

10.105ps

TJ@BER1, Math1

11.159ps

RJ1, Math1

506.04fs

RJ1, Math1

694.31fs

PJ1, Math1

3.6968ps

PJ1, Math1

2.8264ps

DJ1, Math1

3.6968ps

DJ1, Math1

2.8264ps

NPJ1, Math1

881.89fs

TIE2, Math1

-25.694fs

TIE2, Math1

55.789fs

Rise Slew Rate1, Math1 9.2843V/ns

Rise Slew Rate1, Math1 9.2627V/ns

TJ@BER1, Math1

9.9087ps

TJ@BER1, Math1

10.315ps

RJ1, Math1

556.41fs

RJ1, Math1

680.95fs

PJ1, Math1

2.6685ps

PJ1, Math1

1.7365ps

DJ1, Math1

2.6685ps

DJ1, Math1

1.7365ps

NPJ1, Math1

592.92fs

TIE2, Math1

44.029fs

TIE2, Math1

89.108fs

Rise Slew Rate1, Math1 9.3228V/ns

Rise Slew Rate1, Math1 9.2542V/ns

Receiver Testing Overview

MOI critical to Rx Test
Includes step-by-step procedure along
with setup files for calibration

Calibration Setup

Physical
Setup

ISI Calibration

RJ calibration

SJ calibration

AC Common
Mode
calibration

Eye Height
Calibration
and TJ

RX Testing

Rx Testing
Steps to Run BER test:
Attach DUT & microcontroller

Turn on required stresses

Run RX BER script for 6 mins

Complete Thunderbolt Instrument Portfolio

Receiver Tests/Active Cable Tests
Receiver silicon and system margin
testing.
Tj, Rj, DDJ, BUJ, AC-CM

BSA125C 12.5 Gb/s BERTScope

DPP125B Digital Pre-Emphasis
Preprocessor
CR125A Clock Recovery Unit
TF-TB-TPA-P/R Plug & Receptacle
Test Fixtures

Channel Tests
Return Loss (HF,LF)
(SDD11,SDD22)

DSA8300 Sampling Oscilloscope

Common Mode Return Loss

(SCC22)

80SICON S-Parameter Analysis

Software for DSA8300

Channel Insertion Loss (SDD21)

TF-TB-TPA-P Test Fixture

80E04 20 GHz TDR Sampling Module

Near End Crosstalk (NEXT)

Transmitter Tests
AC Parametric measurements

Jitter
Eye Opening

DSA71604C with option TBT-TX

DPOJET Jitter Analysis software
TF-TB-TPA-P Test Fixture

Debug Example
TBT design fails during certification
Report shows voltage/timing failures

Whats the next step?

Drilling into Root Cause

Import saved waveforms into DPOJET
Re-run measurements that fail

Based on results can:

Compare against addition plots
Modify DPOJET or acquisition settings (filters, RL, etc.)
Investigate signal anomalies with DPOJET sync features

Final Resolution
Voltage droop on D- (Ch3) causes amplitude imbalance
Customer suspects RC time constant not set correctly (DC block/pull
down)
Compliance

Debug

Root Cause

DEMO

Display Port Source testing

1. Select
2. Acquire

3. Analyze
Can it be just that easy?

Customer needs in Display Port testing

Challenges
Device State control
Measurements algorithms
Setups

Requirements
Straight forward operations and setups
Complete testing for both single ended
and differential measurements
Flexibility in testing

Results
Pass or Fail
Margins and Limits
Complete and easy to read report
32

How does Tektronix help with Display Port testing

Tektronix offers a complete and easy testing
solution to support the testing needs for Display
Port.
Compliance and Characterization.
Minimum user intervention
Easy Pass fail status
Test result provide margins

Debugging
Automatic saving of the failed data set.
Offline failure analysis of the save data
Flexible probing for debugging

DisplayPort Test Point

Test Point Definitions

34

TP1: at the pins of the transmitter device.

TP2: at the test interface on a test access fixture
TP3: at the test interface on a test access
TP3_EQ: TP3 with equalizer applied.
TP4: at the pins of a receiving device.

Display Port 1.2 Update

Eye Diagram Test using Eye Compliance Pattern

An Eye diagram test for 800mV , 0dB pre-emphasis at TP2,TP3, TP3-EQ.

35

Tektronix Technology Innovation Forum 2011

Display Port 1.2 Update

Automation: DP Testing is a large task!

Combination Parameters For DP1.2 testing
Data Rate

-3

Lanes

-4

Pre-Emphasis

- 4 Levels

Voltage Swing

- 4 Levels

Post Cursor2

- 4 Levels

SSC

- 2 Levels(SSC On and Off)

Patterns

- 5 Supported Patterns

Test

Combination of tests
1. Differential tests
2. Single Ended tests

Waveforms(SSC, 4 Lanes possible Combinations)

Eye Diagram test

80

Pre-Emphasis Test

240

Non-Pre-Emphasis

32

Total Jitter

80

~432 Acquired signals for DP1.2 Normative Measurements per lane.

X4 lanes results in 1728 Automated Acquisitions per DUT.
Display Port 1.2 Update

DisplayPort Auxiliary Channel Controller (DP-AUX)

Why use Aux channel controller in
physical layer testing?

HPD
Aux
channel

Speeds up Test Time No User Interaction is

Required to Change Source Output Signal or
Validate Sink Silicon State or Error Count
No Need to Learn Vendor-specific Software A Single GUI Supports All Vendors
View & Log Decoded AUX Traffic and Hot
Plug Detect (HPD) Events from the Device
under Test to the DP-AUX DisplayPort AUX
Controller
Ability to Read and Write DPCD Registers
Supports Debug Activities
Tektronix DP-AUX can serves as a DP1.2
Sink, enabling the source to transmit the
required patterns for testing.

Display Port 1.2 Update

TekExpress DP1.2
Automation
Comprehensive Display Port
version 1.2 Physical Layer
Conformance and Compliance
verification tool.
All Core DP1.2 measurements
Keithley RF Switch and DPAUX fully automated solution.

Selected measurements can be

applied across all test
permutations
(SSC,CTLEs,swing,rates,preemphasis,etc) translates to
1728 measurements. DP12
will provide full user
intervention free, automated
testing. This is the killer value
proposition.
Factory Automation API for full product control in silicon automation systems.
Complimentary Fixtures and Compliance Interconnect Channel HW defined by VESA
make this package a full customer solution with no compromises.

Display Port 1.2 Update

DP1.2
Test Selection
DP1.2
Measurement
selection is now
provided as a function
of the user specified
test target capabilities.
If Post Curser 2
capabilities are not
present in the DUT,
the measurement list
will not show them.
Configuration
schematics and online
help available for all
measurements

Display Port 1.2 Update

Keithley RF Switch Integration and Automation

DisplayPort transmitter has both Differential tests and Single ended tests and
with the integration of RF switch we have complete automated solution without
any user intervention for switching between lanes with both single ended and
differential tests in sequential automated passes.

41

Keithley is now part of Tektronix.

Display Port 1.2 Update

DP1.2
Reporting
DP1.2
Custom html
reports which
include user
specified degrees
of detail.
Reports and
Session raw data
are stored together
allowing recalling a
previous run and
re-running the test
(with different
measurement
configurations or
limits) and regenerating a new
report, without the
actual DUT
present.

Display Port 1.2 Update

Challenges with Sink testing

Transmitting pattern
Three different Complex patterns

Stressor requirements
Rj, Sj, ISI Jitter stressors
Cross talk
Calibrated with CTLE equalizers

Error detection
Need access to internal register

Challenges to adding stressors

Calibration process for all rates
Different test points for each type of
calibration stress
Some stressor are calibrated with any
other stressors

What is different between calibrations

for the different rates
HBR2 contain two SJ tones
RBR/HBR single SJ tone.
HBR2/HBR Tj calibrated at TP3_EQ,
RBR Tj calibrated at TP3
All three have different duration of
testing

What next for Tektronix Display Port tool sets

Growing segment in Display Port is the
Embedded Display Port(eDP)
Currently CTS specification is V1.3
Specification 1.4 is just release on Sep.
2012, but CTS spec is not ready yet

Technology is used in Laptops and tables

and more
eDP used to replace LVDS
Sources moving to eDP
Display moving at a slower pace

Solution is a DPOJET plug in using the

ADK tool set.
Available 4th Quarter
Support all eDP measurements
Printable report

Complete Tektronix DisplayPort Instrument Portfolio for

Source testing
Equipment for Source testing

DSA71254C or higher for HBR2

DSA70804C or higher for HBR and RBR
P7313SMA for HBR2 (optional)
P7380SMA for HBR/RBR (optional)
VESA fixtures or Wilder technologies
fixtures
DP Aux control (Required for Automated
testing, optional for manual testing)
TekExpress DP12

Complete Tektronix DisplayPort Instrument Portfolio for

Reciever testing
Equipment for Receiver testing

BSA85C
BSA12500ISI
100ps TTC qty 2
6 dB attenuators qty 2
DC block Qty 2
Assorted SMA Cables
One to Three way power splitters
VESA fixtures or Wilder technologies fixtures
DP Aux control (optional if the customer has a way to read the registers)
Tektronix Display Port 1.2 MOI