IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.

8, AUGUST 2010

2747

Multilevel Optimal Predictive

Dynamic Voltage Restorer
J. Dionsio Barros, Member, IEEE, and J. Fernando Silva, Senior Member, IEEE

AbstractThis paper presents an optimal predictive controller

for a multilevel converter-based dynamic voltage restorer (DVR),
which is able to improve the voltage quality of sensitive loads
connected to the electrical power network. The optimal predictive
controlled multilevel DVR can restore sags and short interruptions
while reducing the total harmonic distortion (THD) of the ac
line voltages to values lower than 1%. The DVR is based on a
three-phase neutral point clamped converter to dynamically inject
a compensation voltage vector in series with the line voltage,
through series-connected transformer secondary windings. To assure high-quality voltages for sensitive loads, we devise optimal
predictive control laws for the injected compensation ac voltages.
A suitable quadratic weighed cost functional is used to choose
the voltage vector, minimizing both the ac voltage errors through
current injection and the dc side capacitor voltage unbalancing.
The performance of the proposed predictive controller is compared to classical proportional integral (PI): synchronous frame
and stationary frame (P+resonant) controllers. The line-side filter capacitor topology is compared to the regular converter-side
filter capacitor. Obtained experimental results show that the ac
voltages are almost sinusoidal in steady-state operation when
facing balanced and unbalanced sags and short interruptions with
unbalanced loads. Voltage THD is reduced to values lower than
1%; the DVR is behaving also as a series active power filter for the
ac voltages.
Index TermsDynamic voltage restorer (DVR), neutral point
clamped (NPC) multilevel converter, power quality, predictive
optimal control.

I. I NTRODUCTION

YNAMIC VOLTAGE RESTORERS (DVRs) are mainly

used to protect sensitive loads from the electrical network
voltage disturbances such as sags or swells and could be used
to reduce harmonic distortion of ac voltages. Voltage sags are
abrupt reductions (between 10% and 99%) in the ac voltage root
mean-square value, lasting less than 60 s. Typical sag depths
range from 50% to 90% of the nominal voltage and span from
10 ms to a few seconds. Voltage sags are given a great deal of
attention because of the wide usage of voltage-sensitive loads
such as adjustable speed drives, process control equipment, and
computing devices [1], [2]. Voltage sags can cause extensive
Manuscript received March 14, 2009; revised September 1, 2009; accepted
September 17, 2009. Date of publication October 20, 2009; date of current
version July 14, 2010. This work was supported in part by the Centro de Cincia
e Tecnologia da Madeira (CITMA), Fundo Social Europeu, POPRAM III, and
in part by the FCT-FEDER project PTDC/EEA-ELC/101341/2008.
J. D. Barros is with the Exact Sciences and Engineering Competence Centre,
University of Madeira, Campus Universitrio da Penteada, 9000-390 Funchal,
Portugal (e-mail: dbarros@uma.pt).
J. F. Silva is with the Department of Electrical and Computer Engineering,
Instituto Superior Tcnico, Technical University of Lisbon, 1049-001 Lisbon,
Portugal (e-mail: fernandos@alfa.ist.utl.pt).
Digital Object Identifier 10.1109/TIE.2009.2034172

interruption or disruption to the industrial process sector [3],

being, in many cases, the most severe power quality issue [1].
Power electronics can improve the quality of power in critical
loads, compensating sags, swells, and network ac voltage interruptions in the electrical network and reducing the voltage or
current total harmonic distortion (THD) [4]. Therefore, the application of power electronic systems such as DVRs and active
power filters (APF) to improve power quality in industrial and
commercial plants has become an important area of research
[2], [5].
The DVR is a good solution in mitigating sags in the upstream at the distribution level. The DVR injects a compensating voltage in series with the ac network line when an upstream
sag is detected to protect loads connected downstream of the
DVR. The DVR can also be used to limit the flow of large
line fault current of a downstream fault to restore the voltage at
the point of common coupling and to protect the DVR system
components in fault conditions.
Unlike uninterruptible power supplies (UPS) that must supply the total voltage and power to the sensitive load, the DVR
only needs to supply the sag depth compensating voltage,
meaning that the DVR power is usually much lower than the
nominal load power. Compared to UPS, the DVR presents also
smaller losses in steady-state operation [6][8].
The typical DVR topology essentially contains a voltage
source inverter (VSI), an injection transformer connected between the ac voltage line and the sensitive load, and a dc
energy storage device (Fig. 1) [3], [4], [9][14]. An alternative
DVR topology with a pulsewidth modulated autotransformer
[2] can minimize the number of switches, reducing the costs
and allowing, nevertheless, the rising of the THD output voltage
at the sensitive load.
The series-connected transformer secondary winding injects
the compensating voltages generated by the VSI to mitigate
voltage sags of the ac line (Fig. 1). Multilevel VSI converters
[15] such as diode-clamped converters [4], [16], multilevel
flying capacitor converters [17], [18], or multilevel cascaded
H-bridge converters [19][21] are able to synthesize voltage
waveforms with lower harmonic content than two-level converters [3], [11] and able to operate at higher dc voltages [22].
PWM-based modulation techniques [22], [23] or slidingmode controllers [24], [25] are the most used techniques in generating the injected voltages [23], [26]. However, these voltages
still present a considerable ripple, which reduces power quality
of the voltage applied on sensitive loads [27][29]. Optimal
predictive controllers can calculate in real time the future values
of the converter voltages and currents and minimize a cost
functional to choose the optimal vector, thus optimizing the

0278-0046/$26.00 2010 IEEE

2748

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

Fig. 1. Typical application of a DVR to protect sensitive loads. (a) Capacitor

filter placed on the converter side. (b) Capacitor filter placed on the line side.

ripple and THD to enhance the output voltage and the power
quality [18], [27][33].
The controlled VSI converts the stored energy (dc source)
into ac compensating voltages UDVR , which are filtered by a
second-order LC low-pass filter (Fig. 1). The filter capacitor
can be placed either on the converter side [Fig. 1(a)] or on the
line side of the series transformer winding [Fig. 1(b)] [4]. By
inserting the filtering capacitor on the converter side [Fig. 1(a)],
the high-frequency switching harmonics are filtered locally, but
the bandwidth of the injected compensating voltage is reduced,
and the capacitor cannot aid in the compensation of the load displacement power factor, since, dynamically, an LC tank circuit
is in series with the ac power supply. Oppositely, connecting
the filter capacitor on the series transformer line side [Fig. 1(b)]
does not limit the bandwidth of the injected compensating voltage, and the capacitor can aid in the displacement power factor
compensation in spite of sustaining the full line voltage, since
the ac power supply sees a parallel LC circuit. A systematic
method to design the high-order harmonics filter, considering
various issues concerning the DVR, is discussed in [9].
A crucial performance issue of the DVR is the need for fast
detection of the main ac voltage amplitude and the generation
of its fundamental frequency and phase, even under unbalanced
and distorted ac voltages. The performance of the DVR is
strongly influenced by the accuracy of the ac voltage synchronization [34]. To inject a series voltage to dynamically restore
the nominal ac voltages, it is mandatory to detect the sag depth.
Several methods were reported to obtain the sag depth information: The peak detection of the network ac voltage provides the
sag depth, but it can take up to half a cycle to obtain this information [3]; the detection of direct voltage component vd gives
the information about sag depth in a balanced system, but components with a frequency of 100 Hz occur in unbalanced voltage

systems, which can take up to a half a cycle before reaching the

minimum value of vd [3]; locking a narrow bandpass filter can
track changes in the network ac voltage phase, but it cannot directly return information regarding sag depth [3]; and applying
the Fourier transform to each phase returns the magnitude and
phase of each frequency component, but filtering out harmonics
other than the fundamental (50 Hz) introduces transient
delays [3]. An optimal predictive phase quadrature synchronizer that real time computes the phase shift correction factor
to quickly detect the phase of the network ac voltage, even
with balanced and unbalanced sags and swells, high-order THD
distortion, and short interruptions, is used here on a multilevel
DVR to generate the fundamental frequency [35], [36].
The DVR performance in steady state and in transient mode
also depends on the control laws, which shape the series compensating voltage to add to network ac voltage to compensate
the sag and to compensate the ac load voltage THD. Known
DVR system fundamental control strategies include the presag,
in-phase, and minimal energy [13]. Recent examples of successful control laws use a P+resonant [11], having high gains
around 50 Hz, to achieve good positive and negative sequence
fundamental voltage controls. The H control method is used
to achieve robust control of the DVR voltage [11]. A virtual
inductance DVR controller can ensure zero real power absorption during DVR compensation, thus minimizing the stress on
the DVR dc power supply [37]. Control strategies can reduce
the distortion of load voltage and save the dc-link capacitor
energy [13]. A DVR with a series converter on the sourceside connected through a dc-link capacitor to a back-to-back
shunt converter on the load side is proposed [14] to reduce the
capacitor energy storage and compared with a DVR topology
with a series converter on the load side and the shunt converter
on the source side [14].
Despite the control strategies and capable results in reducing
the impact of voltage sags to sensitive loads, most control
processes do not deal with the reduction of the voltage THD at
sensitive loads, mostly due to the injected compensation voltage. They are not concerned about voltage short interruptions,
neither with the sharp notches or overshoots that occur mostly
at the beginning and at the end of the sag.
The aim of this research paper is to design optimal output
voltage controllers to ensure constant ac voltage amplitude,
without interruptions and unbalances, while reducing the ac
voltage THD in the sensitive load, even during the presence
of sags, short interruptions, and high values of THD. The presented multilevel optimal DVR does not confine the control to
only one fundamental strategy, since the presag compensation
will be used to restore the existing amplitude voltage and phase
prior to the voltage short interruption, and the in-phase compensation will be used to mitigate sags, minimizing the DVR
voltage amplitude. The ac voltage waveform quality will be
improved using a multilevel converter-based DVR, and the filter
capacitor topology will be evaluated. A synchronous dq frame
predictive controller of the output ac voltage, which is able
to mitigate ac voltage disturbances, is designed (Section II-A)
and, using simulation and experimental results, compared
(Section IV) to a synchronous dq frame proportional integral
(PI) controller (Section II-B) and asynchronous (P+resonant)

BARROS AND SILVA: MULTILEVEL OPTIMAL PREDICTIVE DYNAMIC VOLTAGE RESTORER

Fig. 2.

Optimized feedback system of the DVR to improve power quality of the output ac voltage of sensitive loads.

Fig. 3.

Three-phase DVR simplified power circuit.

PI controller (Section II-C). Using the state-space model of the

three-phase neutral point clamped (NPC) multilevel converter,
an optimal predictive controller, also reducing the THD distortion of the ac voltages (Section III-A), is obtained. Additionally,
an optimal predictive phase quadrature synchronizer detects the
phase of the ac network voltage and generates the fundamental
frequency (Section III-B).
The filtering capacitor is placed on the ac side to improve
the mitigation capability of the DVR in a wide frequency range
of network ac voltage perturbations. This line-side capacitor
topology is compared to the converter-side capacitor placement.
Simulation and experimental tests show the DVR performance
and optimized critical load ac voltage THD, enabling the comparison to the referred methods (Section IV).
II. S ENSITIVE L OAD AC VOLTAGE C ONTROL
The control system of the NPC converter-based DVR usually
uses an ac load voltage control outer loop which generates the
current references iRef and iRef for the inner ac current loop
optimal predictive controllers (reported in Section III).
The structure of the optimal predictive multilevel DVR showing the interconnection of all subsystems and feedback control
loops is shown in Fig. 2. The optimal predictive controller
of the ac sensitive load voltages generates, through a limiter,
the current references iRef and iRef for the inner ac current

2749

loop optimal predictive controllers. An equivalent DVR model

connected to an ac network is derived next to design outer loop
controllers, including the optimal predictive controller for the
ac voltages.
The ac network voltages (U1 , U2 , and U3 ) are represented
using the equivalent network model with line inductances
(LLine ) and their loss resistors (RLine ) (Fig. 3). A three-phase
transformer with separated secondary windings, with each one
series connected with each line voltage, is used to inject the
compensation voltage. The filtering capacitors CL [Fig. 1(b)]
are placed on the line side to obtain high control bandwidth
while reducing the NPC converter high-frequency harmonics.
Assuming balanced operation and applying the Kirchhoff
laws to the DVR circuit (Fig. 3), the dynamic equations (1)
of the sensitive load ac voltages (UL1 , UL2 , and UL3 ), can be
written as functions of the circuit parameters (filter capacitor
CL and transformer ratio n = N2 /N1 )
dULj
1
1
=
ij
iLj ,
dt
nCL
CL

j = 1, 2, 3.

(1)

The dynamic equations (1) are suitable in designing outer

loop controllers for UL1 , UL2 , and UL3 output voltages. Their
control inputs are the NPC converter output ac currents i1 , i2 ,
and i3 . From the control viewpoint, the load currents iL1 , iL2 ,
and iL3 are perturbations.

2750

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

For control purposes, the isolated neutral output ac voltage

can be advantageously written in the and dq coordinates
[38]. Applying the ClarkeConcordia transformation to the
model of the output ac voltage (1), the model of the output ac
voltage (2) in the coordinates is obtained
   1


 dUL   1
0
0
CL
i
iL
dt
nCL
=
+
.
dUL
1
i
iL
0
0
C1L
nCL
dt
(2)
Applying the Park transformation to the output ac voltage
model in the coordinates (2), the model of the output ac
voltage (3) in the dq coordinates is obtained

  1
 
 dULd  
0
0
ULd
id
dt
nCL
=
+
dULq
1

0
U
iq
0
Lq
nCL
dt
 1


0
iLd
CL
. (3)
1
iLq
0
C

These predictive equations [(5) and (6)] are discrete feedback

control laws (sampling time TU Ldq = 360 s) for the sensitive load ac voltages in the dq coordinates, giving the currents
idRef(ts+1 ) and iqRef(ts+1 ) needed to track the critical load reference voltages ULdRef(ts+1 ) and ULqRef(ts+1 ) . The predictive
laws (5) and (6) differ from PI controllers, as they replace the
integral of the voltage errors by the measured (or estimated)
currents iLd(ts ) and iLq(ts ) , which for common inductive loads
are related to the integral of the voltages applied to the circuit.
The inner current loop to enforce the idRef(ts+1 ) and iqRef(ts+1 )
currents is described in Section III.
To test the optimal predictive controller of the sensitive load
ac voltage with the filter capacitor placed on the converter side
[Fig. 1(a)], a dynamic model similar to (3) was obtained, from
which the following predictive control laws were obtained:
idRef(ts+1 ) =

The ac voltage phase is the argument of the synchronous

frame rotating at the angular velocity of the ac voltages and
with zero initial angle, d = 0, between the component in
the coordinate system and direct d component in the dq
coordinate system
= t + d ,

d = 0.

(4)

The dynamic equations of the sensitive load ac voltage (3),

represented in the dq coordinates, are time invariant in steady
state but cross coupled and need to know the perturbations iLd
and iLq . Thus, decoupling control methods should be applied
to this time-invariant dynamic model of the DVR.
The design of compensators to obtain constant-amplitude ac
sinusoidal load voltages in the presence of load variations is the
objective of the next three sections. A new predictive controller
is obtained in Section II-A.
A. Optimal Predictive Controller of the
Sensitive Load AC Voltage
This new controller of the sensitive load ac voltages intends
to predict the value of the multilevel current references needed
to minimize the errors of load ac voltages (relatively to their
references). At time step ts = kTU Ldq (TU Ldq is the voltage loop sampling step), the prediction of the multilevel current
references for the next sampling step ts+1 = (k + 1)TU Ldq
[idRef(ts+1 ) (5) and iqRef(ts+1 ) (6)] is obtained by inverting the
dynamic equations of the sensitive load ac voltage (3), considering that the actual step (ts = kTU Ldq ) sampled load voltages
ULd(ts ) and ULq(ts ) must follow their references ULdRef(ts+1 )
and ULqRef(ts+1 ) in one voltage loop sampling time TU Ldq
idRef(ts+1 )

ULdRef(ts+1 ) ULd(ts )
= nCL
TU Ldq
nCL ULq(ts ) + niLd(ts )

iqRef(ts+1 ) = nCL

(5)

ULqRef(ts+1 ) ULq(ts )
TU Ldq

+ nCL ULd(ts ) + niLq(ts ) .

(6)

CLCONV ULdRef(ts+1 ) ULd(ts )

n
TU Ldq


CLCONV 
ULq(ts ) Uq(ts ) + niLd(ts )
n
(7)

iqRef(ts+1 ) =

CLCONV ULqRef(ts+1 ) ULq(ts )

n
TU Ldq
+


CLCONV 
ULd(ts ) Ud(ts ) + niLq(ts )
n
(8)

where CLCONV is the filter capacitor placed on the converter

side, having a capacitance CLCONV = n2 CL , and Ud(ts ) and
Uq(ts ) are the ac network voltages represented in the dq
coordinates.
The performance of the predictive controllers will be compared to PI controllers (synchronous and asynchronous), presented in the next sections.
B. Synchronous dq Frame PI Controller
of the Output AC Voltage
The design of the PI controller can be advantageously
made by decoupling the cross coupling terms on the dynamic
equations of the sensitive load ac voltage (3). For decoupling
purposes, two new auxiliary variables hd and hq are defined
hd = id + nCL ULq

(9)

hq = iq nCL ULd .

(10)

Substituting hd and hq [(9) and (10)] into the dynamic model

of the output ac voltage (3), a decoupled model is obtained
 dULd   1
   1


0
0
CL
hd
iLd
dt
nCL
=
+
.
dULq
1
hq
iLq
0
0
C1L
nCL
dt
(11)
Using this decoupled model (11) and two PI compensators
with gains KP and KI , similar feedback loops are achieved,

BARROS AND SILVA: MULTILEVEL OPTIMAL PREDICTIVE DYNAMIC VOLTAGE RESTORER

with one for each voltage component ULd and ULq , which in
closed loop are


KP
KI
1
s
+
nCL
KP ULdRef
CL siLd
ULd =

(12)
KP
KI
KP
KI
s2 + s nC
+ nC
s2 + s nC
+ nC
L
L
L
L


KP
KI
1
s
+
nCL
KP ULqRef
CL siLq

. (13)
ULq =
KP
KI
2 + s KP + KI
s2 + s nC
+
s
nC
nC
nC
L
L
L
L
In steady-state operation, the disturbance terms iLd and iLq
of the voltages ULd (12) and ULq (13) are nil (s = 0). The
denominator of the sensitive load ac voltage terms ULd (12)
and ULq (13) can be equated to a second-order system (s2 +
2n + n2 ) to obtain the parameters KP (14) and KI (15)
of the PI compensator as functions of the damping ratio
and undamped natural frequency n of the second-order
system [39]
KP = 2nn CL

(14)

KI = CL nn2 .

(15)

A damping ratio , which is a good compromise between the

step response speed and low overshoot, is [39]

2
.
(16)
=
2
The undamped natural frequency n should be chosen
to impose the control bandwidth. In discrete sampling time
implementation, the bandwidth is limited by the sampling
frequency fs
n  s

s = 2fs .

(18)

These PIs are synchronous frame dq controllers. They will be

compared to the asynchronous controllers [11] next revisited
(Section II-C), to enforce the reference currents in the
coordinates.
C. Asynchronous PI (P+resonant) Controller of the
Output AC Voltage
The dynamic equations of the output ac voltage (2), in the
coordinates, do not present cross coupling terms. Therefore, a
PI controller, with 0 frequency shift, can be used to generate
the current references of the DVR [40]
KI s
.
s2 + 02

HPI (s) = KP +

s2

KI cut s
.
+ 2cut s + 02

(21)

An extensive analysis of the P+resonant controller, applied

to DVRs, can be found in [11]. Here, it will be used for comparison of simulation and experimental performance (Section IV)
between the optimal predictive controller and the classical PI
compensator (synchronous dq frame and P+resonant).

III. O PTIMAL P REDICTIVE M ULTILEVEL

DVR C URRENT C ONTROL S YSTEM
The global performance of the DVR depends significantly on
its feedback system, which can be improved using an optimal
controller to track the needed idRef and iqRef current references
and an optimal synchronizer to the fundamental frequency.
In this section, the DVR current control feedback is made
predictive to improve the load ac voltage power quality. This
predictive current controller is the inner current control loop
for all the ac output voltage compensators of Section II.

A. Multilevel NPC VSI

iqRef = KP (ULqRef ULq )


+ KI (ULqRef ULq ) dt + nCL ULd . (19)

HPI (s) = KP +

These asynchronous PI controllers, called P+resonant [11],

[40], are tuned to the fundamental frequency 0 (250 rad/s).
Equation (20) represents a resonant regulator, which achieves
infinite gain and no steady-state error, at the fundamental
frequency 0 . However, this ideal function (20) cannot be
physically implemented. A practical controller can be obtained
by approximating the ideal 0 integrator using a high-gain lowpass filter with cutoff frequency cut [40]

(17)

The control laws of idRef (18) and iqRef (19) can be obtained
in the function of the output ac voltage errors from (9) and (10)
idRef = KP (ULdRef ULd )

+ KI (ULdRef ULd ) dt nCL ULq

2751

(20)

The NPC multilevel converter generates the ac currents i1 , i2 ,

and i3 , tracking references (from idRef and iqRef ) obtained from
the output ac voltage controllers (Section II). These currents
are needed to enforce the output ac voltages and must present
low ripple and zero tracking error to ensure high-quality voltage
waveforms.
Applying the Kirchhoff laws to the multilevel converter
circuit (Fig. 4) and the ClarkeConcordia transformation, the
dynamic equations of the ac currents i1 , i2 , and i3 and the capacitor voltages UC1 and UC2 are advantageously represented
in the coordinates i and i

di
dt
di
dt
dUC1
dt
dUC2
dt

R
L

0

=
1
C1
C2
2

0
R
L

C11

C22

L1
0
+
0
0

1
L
1
L

0
0
0
L1
0
0

0 UC1
UC2
0

0 UL U
n
0
UL U
1
n
C1
idc
1
2
L
2
L

(22)

C2

where i and i , with i {1, 2}, are functions depending

only on the switching variables k (24), which represent the

2752

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

Fig. 4. NPC multilevel of the DVR circuit.

multilevel converter insulated gate bipolar transistors (IGBTs)

(Fig. 4) state Skj (Skj = 0 IGBT is off and Skj = 1 IGBT is
on) [28]
 

i3
2
i2

i =
i1
3
2
2

 

2
3
3
i2
i3
i =
3
2
2
k (k + 1)
2
k (1 k )
=
2

1k =
2k

1,
k =
0,

1,

(23)

(Sk1 = 1 Sk2 = 1) (Sk3 = 0 Sk4 = 0)

(Sk1 = 0 Sk2 = 1) (Sk3 = 1 Sk4 = 0)
(Sk1 = 0 Sk2 = 0) (Sk3 = 1 Sk4 = 1).
(24)

The 27 possible combinations of i and i , values can be

used to plot the 27 multilevel vectors in Fig. 5 (the values inside
the brackets represent the voltage levels of each leg).
Model (22) is suitable in establishing the inner current loop
controllers for the NPC converter ac current i1 , i2 , and i3 .
Several control methods for the currents i and i were
proposed [16], [22][33], [40]. However, the optimal predictive
control method [28][33] is advantageous, as it minimizes
both the ac current i and i errors and the dc unbalance of
capacitor voltages UC1 and UC2 . Previous results show comparably better performances on the currents (lower ripple and
THD) and on the unbalance of capacitor voltages. The optimal
predictive current controller has the potential to improve the
overall performance of the DVR [28].

Fig. 5.

Available voltage vectors at the output of the multilevel converter.

The current optimum controller minimizes both the ac currents errors and the capacitor voltage difference using a suitable
quadratic cost functional (25) of the tracking errors given in
(26) and (27)

e2 (ts+1 ) e2 (ts+1 ) e2U C (ts+1 )
+
+
(25)
C(ts+1 ) =

U C
where
e (ts+1 ) = iRef (ts+1 ) i (ts+1 )
e (ts+1 ) = iRef (ts+1 ) i (ts+1 )

(26)

eU C (ts+1 ) = UC1 (ts+1 ) UC2 (ts+1 ).

(27)

BARROS AND SILVA: MULTILEVEL OPTIMAL PREDICTIVE DYNAMIC VOLTAGE RESTORER

iRef (ts+1 ) and iRef (ts+1 ) are the ac current references

given by the DVR ac voltage outer loop controller, with one
sample time forward ts+1 = (k + 1)T (a T sampling time
of 36 s) to compensate for the processor calculation delay. The
ac currents i (ts+1 ) and i (ts+1 ) are estimated from dynamic
model (22) [30]. To assure adjacent level voltage transition in
each multilevel converter leg, easing the semiconductors task
(as each leg voltage does not switch directly from +Udc to 0
or from 0 to +Udc ), only vectors needing just the switching of
two semiconductors per leg are used to calculate the cost (25) of
the application of each voltage vector to (22). In cost functional
(25), the errors are weighted by , , and U C to normalize
the distinct errors, which have different units and ranges, and
to define the priority level of each error variable. Therefore,
these weights are designs of degree of freedom but should be
anticipated considering the current and voltages ranges and
enforcing, as a first guess, that allowed errors obey e2 / =
e2 / e2U C /U C to give roughly equal weights to all the
controlled variables. Then, in practice, dc capacitor voltage
balancing has a lower priority level, so the term e2U C /U C in
steady state comparatively should weight less in cost functional.
This means that U C should be much bigger than or ,
which must be small (but higher than zero) to give a higher
priority level to the controlled currents.
Calculating the quadratic cost functional (25) at the next
sampling period, for the candidate 27 multilevel voltage vectors
(Fig. 5), the vector showing the minimum value of the cost
functional can be found among the available 27 vectors. This
optimal vector is chosen and decoded to obtain the IGBTs gate
drive signals of the multilevel converter.
B. Fundamental Frequency Synchronization
The measurement of the fundamental frequency and phase
of the network voltage is crucial for the DVR control. The
detector of the ac voltage phase must be fast to assure that a
synchronization frame is always in phase with the fundamental
frequency of the network ac voltage. To achieve this objective,
a robust and fast phase detection/synchronization method, together with fundamental frequency generation, must be implemented. Phase and frequency recognition is hard to obtain from
the ac network voltages when sags or interruptions occur. Synchronization should use the network ac waveforms, which can
have amplitude and frequency variations, voltage sags/swells,
short interruptions, and distortion. The synchronization method
must rapidly capture the phase of the network ac voltage after a
short interruption, must be robust to amplitude variations, and
must handle unbalanced amplitude ac voltages. To provide an
optimal solution to phase detection and fundamental frequency
generation, a predictive phase detection and a fundamental
frequency generation, based on dq Park transformation, are here
briefly introduced [35], [36].
The application of the ClarkeConcordia and the Park transformations to ideally balanced network ac voltages with synchronous frame can provide a nil quadrature Uq component
[35], [36]. The synchronous frame can be obtained by finding
its optimal value that results in a nil quadrature Uq ac voltage
component.

2753

Fig. 6. Predictive synchronous frame vectors.

Applying the ClarkeConcordia to the network ac voltages,

supposing constant amplitude U , and Park transformations
with phase error (ts ), the direct component Ud (ts ) and the
quadrature component Uq (ts ) computed at the present sampling
time (ts = kT ) are [35], [36]

3
U cos (ts )
(28)
Ud (ts ) =
2

3
U sin (ts ).
Uq (ts ) =
(29)
2
The phase error (ts ) can be computed from the direct
Ud (ts ) and the quadrature Uq (ts ) ac voltage components. At
the next sampling time ts+1 = (k + 1)T , the fundamental
frequency has a phase variation of T . Thus, the prediction
of the phase error (ts+1 ) is
(ts+1 ) = (ts ) T.

(30)

The prediction of the synchronous frame at the next sampling

time (ts+1 ) is obtained by subtracting the predicted phase
error (ts+1 ) to the actual synchronous frame (ts )
(ts+1 ) = (ts ) (ts+1 ).

(31)

Fig. 6 shows the predicted vector (ts+1 ) obtained from the

phase error (ts ) and the actual synchronous frame (ts )
vectors.
The feedback control loop to obtain a synchronous frame
(ts+1 ) (Fig. 7) computes the ClarkeConcordia and Park
transformations to obtain a quadrature voltage component
Uq (ts ), which is compared to its reference value UqRef = 0.
The Uq (ts ) and Ud (ts ) ac voltage component values feed an
optimal predictive phase quadrature [35], [36] compensator that
computes the phase error (ts ) using (28) and (29), generating the synchronous phase (ts+1 ), to obtain a quadrature
voltage component Uq following its reference UqRef = 0.
Using the values of the voltage components Ud (ts ) and
Uq (ts ), the optimal predictive phase quadrature compensator
is designed [35], [36] to predict the optimal value of (ts+1 )
(cos[(ts+1 )] and sin[(ts+1 )]) that minimizes the quadrature

2754

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

TABLE I
S YSTEM PARAMETERS

Fig. 7. Basic principle of optimal predictive phase and frequency detection

based on dq Park transformation.

voltage component Uq of the network ac voltage at the next

sampling time ts+1 = (k + 1)T
cos [(ts+1 )] = cos [(ts )] cos [(ts+1 )]
+ sin [(ts )] sin [(ts+1 )]

(32)

sin [(ts+1 )] = sin [(ts )] cos [(ts+1 )]

cos [(ts )] sin [(ts+1 )]

(33)

where the phase error (ts+1 ) (30) at the next sampling time
(cos[(ts+1 )] and sin[(ts+1 )]) depends on the actual phase
shift error (ts ) (cos[(ts )] and sin[(ts )]). The actual
phase shift error (ts ) is related to the direct voltage component Ud (ts ) (28), the quadrature voltage component Uq (ts )
(29), and the fundamental frequency phase variation T
[35], [36]
cos [(ts+1 )] = cos (ts ) cos(T )
+ sin (ts ) sin(T )

(34)

The quadrature Uq (ts ) component has second harmonic

terms U2q (ts ). The dc term U0q (ts ) is nil and can be obtained by subtracting the second harmonics term U2q (ts ) to the
quadrature component ac network voltage
U0q (ts ) = Uq (ts ) U2q (ts )

 

1
3
3

U2 +
U3 cos 2(ts )
= Uq (ts )
6
2
2
 

U3
1
U2
+

U1 +
sin 2(ts )
6
2
2
= 0.

(38)

sin [(ts+1 )] = sin (ts ) cos(T )

cos (ts ) sin(T ).

(35)

To handle temporary total failures on the network ac voltage,

the synchronization frame must be generated in a self-running
mode at a constant frequency (50 Hz) [35], [36]. The prediction
of the self-running synchronous frame at the next sampling time
(ts+1 ) is
(ts+1 ) = (ts ) + T.

(36)

The predictive optimal phase quadrature compensator can

be designed for unbalanced ac voltages, which is particularly
useful in detecting the phase and frequency during unbalanced sags [35], [36]. Considering the U1 , U2 , and U3 magnitudes of the unbalanced network ac voltage and applying the
ClarkeConcordia and the Park transformations with synchronous frame , the quadrature Uq (ts ) component [35], [36], is

 

1
3
3
U2 +
U3 cos 2(ts )
Uq (ts ) =

6
2
2
 

U3
1
U2
+
+
U1 +
sin 2(ts ). (37)
6
2
2

The optimal predictive phase quadrature compensator for

unbalanced ac network voltage is designed to obtain the synchronous frame , which results in a nil dc quadrature U0q ac
voltage component, similar to the balanced ac network voltage
fundamental frequency synchronization.
IV. S IMULATION AND E XPERIMENTAL R ESULTS
The DVR was first studied by simulation using MATLAB/
SIMULINK to test the theoretical concepts presented here. The
ac voltages were generated and controlled through a synchronous machine and a hydraulic turbine governor, available in
the SimPowerSystems Simulink blockset. The dynamic equations of the NPC converter (22), the currents i1 (t), i2 (t), and
i3 (t), and the capacitor voltages UC1 (t) and UC2 (t) were
implemented with standard Simulink blocks. Ideal switches
were considered. All the optimal predictive controllers (Fig. 2)
of the NPC converter were implemented using MATLAB
S-Functions [28].
To experimentally validate the theoretical concepts, a lowpower (3 kW) laboratorial prototype was built in Fig. 4,
with IGBTs (MG50Q2YS40); diodes (STTA5012TV1); capacitors; inductors; resistors (Table I); IR2110 IGBT drivers with

BARROS AND SILVA: MULTILEVEL OPTIMAL PREDICTIVE DYNAMIC VOLTAGE RESTORER

2755

Fig. 8. Sensitive load ac voltage at sensitive loads UL1 + 740 V, UL2 , and UL3 740 V in steady-state operation (vertical: 370 V/div and horizontal:
10 ms/div). (a) Predictive controller. (b) Classical PI controller. (c) P+resonant controller.

optical isolation (optocouplers HCPL-2200); Hall effect LEM

LA25NP sensors to read the ac currents i1 (t), i2 (t), iL1 (t),
and iL2 (t); isolation amplifiers AD210AN to read the capacitor voltages difference UC1 (t) UC2 (t); and low distortion
isolation amplifiers AD215BY to read the ac voltages U1 (t)
and U2 (t) and the sensitive load ac voltage UL1 (t) and UL2 (t).
The algorithms that are used to control the sensitive load ac
voltage (Section II), the phase quadrature optimal predictive
synchronizer (Section III-B), and the optimal predictive current control loop (Section III-A) were programmed in the
C language and implemented in a digital signal processor,
PowerPC-based board (DS1103). The DVR system parameters
used in the analysis and experiments are described in Table I.
The first experimental results enable the comparison of the
behavior of the output ac voltage controllers in steady-state
operation. Next, the effects of unbalanced and nonlinear loads
on the output ac voltages are experimentally studied. The last
experiments evaluate the sensitive load ac voltage rejection to
the network disturbances.
A. Performance of the Output AC Voltage Controllers in
Steady-State Operation
Experimental results of the ac voltages at the sensitive loads
UL1 , UL2 , and UL3 in steady-state operation (Fig. 8) show that
they track their references, showing a nearly perfect sinusoidal
waveform, when using the output ac voltage optimal predictive
controller [Fig. 8(a)], the output ac voltage PI controller with
synchronous dq frame [Fig. 8(b)], and the P+resonant controller [Fig. 8(c)].
The DVR experiments were done with the laboratory ac
network voltages having a THD of 6.3% to study the performance of the output ac controllers and the filtering topology
in steady-state operation. The results show that, with the filter
capacitor on the ac side [Fig. 1(b)], using the predictive optimal
controller, the THD of the output ac voltage is approximately
0.3%; using the PI dq synchronous frame controller, it is 0.4%
and using the P+resonant controller, it is 0.4%. These results
show that the DVR is able to reduce the output ac voltage
THD, improving power quality. Oppositely, placing the filtering
capacitor on the NPC converter side [Fig. 1(a)], the THD of the
load ac voltage is nearly 5.2% (optimal predictive controller),
5.6% (PI controller), and 6.5% (P+resonant controller). These
results confirm that placing the filtering capacitor on the ac

Fig. 9. Magnitude bode diagram of sensitive load voltage ULi as function of

the multilevel control voltage (UKi ) and ac network voltages (Ui ).

side improves the load ac voltage power quality, compared to

the filtering capacitor in the NPC converter side, when the ac
network ac voltage presents significant THD distortion.
The obtained results also show that the optimal predictive
controller presents the lowest THD levels of the output ac
voltage, independent of the filtering capacitor topology. Experiments closely reproduce the theoretically expected and
simulation results, showing enough insensitivity to parameter
mismatches, as in [28].
As seen, the position of the filtering capacitor can change
significantly the DVR performance. As expected, the topology
with the filtering capacitor on the ac side [Fig. 1(b)] is the
most suitable topology in improving power quality of the output
voltage, in comparison with the topology with the filtering
capacitor on the NPC converter side [Fig. 1(a)]. Fig. 9 shows
the bode diagram magnitude of the sensitive voltage ULi (UL1 ,
UL2 , and UL3 ) as function of the multilevel voltage control
(Fig. 4) UKi (UK1 , UK2 , and UK3 ) and the ac network ac
voltage Ui (U1 , U 2, and U3 ) for both topologies.
The ULi /UKi bode diagram magnitude (Fig. 9) is the same
for both topologies and
has a cutoff frequency given by the filter
parameters LCL (1/ LCL ).
The DVR filtering topology with the capacitor on the ac
side [Fig. 1(b)] reduces the
network ac voltage harmonics with
frequency higher than 1/ LCL , having a slope of 40 dB/dec
(ULi /Ui in Fig. 9), which is the same as the cutoff frequency

2756

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

Fig. 10. Sensitive load ac voltage UL1 , UL2 , and UL3 and the output ac currents iL1 , iL2 , and iL3 when an unbalanced load is connected. iL1 has a displacement
of 2 divisions, and iL3 has a displacement of 2 divisions (vertical: 370 V/div and 2.4 A/div and horizontal: 10 ms/div). (a) UL123 with predictive controller.
(b) UL123 with PI controller. (c) UL123 with P+resonant controller. (d) iL123 with predictive controller. (e) iL123 with PI controller. (f) iL123 with P+resonant
controller.

Fig. 11. AC voltage at the sensitive loads UL1 , UL2 , and UL3 when an additional sensitive load is plugged (vertical: 185 V/div and horizontal: 10 ms/div).
(a) AC voltage (predictive controller). (b) AC voltage (PI controller). (c) AC voltage (P+resonant controller).

of the control voltage UKi . However, the DVR with a capacitor

on the NPC converter side
only reduces disturbances around
a resonant frequency of 1/ LCL (ULi /Ui transfer function
in Fig. 9). The control voltage of the DVR with the filtering
capacitor on the converter side has a small capacitance that
will mitigate perturbations on the output ac voltage,from the
ac network ac voltage, for frequencies higher than 1/ LCL .
B. Performance of the Output AC Voltage Controllers in
Transient and Nonlinear Operations
To analyze the influence of load disturbances on the output
ac voltage, the load resistive component was changed from
the nominal values RL to the unbalanced values of RL /2,
RL , and 2RL in phases 1, 2, and 3, respectively (changes
occur at the fifth horizontal division in Fig. 10). The results
show [Fig. 10(a)] that, using the optimal predictive output

ac voltage controller, the output voltages track their references, being almost insensitive to the unbalanced load step
variation. The output load current references for the optimal
predictive controller [Fig. 10(d)] change accordingly with load
variation.
Experimental results [Fig. 10(b)] show that the output ac
voltage PI controller is not able to control the individual voltage
amplitude of the three phases supplying unbalanced loads.
This controller tries to balance the load currents [Fig. 10(e)],
unbalancing the sensitive load ac voltages [Fig. 10(b)]. The
output ac voltages [Fig. 10(c)] controlled with the P+resonant
are balanced, and the currents iL1 , iL2 , and iL3 [Fig. 10(f)] are
dependent on the unbalance load. However, when the unbalanced loads are established (at the fifth horizontal division in
Fig. 10), the output ac voltage presents a slowly recovering distortion [Fig. 10(c)], which is not present in Fig. 10(a) (optimal
predictive controller result).

BARROS AND SILVA: MULTILEVEL OPTIMAL PREDICTIVE DYNAMIC VOLTAGE RESTORER

2757

Fig. 12. Influence of nonlinear loads (six pulse diode rectifier with inductive filter) on the output ac voltage UL1 , UL2 , and UL3 (vertical: 185 V/div and
horizontal: 10 ms/div). (a) UL123 with predictive controller (experiments). (b) UL123 with PI controller (experiments). (c) UL123 with P+resonant controller
(experiments). (d) UL123 with predictive controller (simulations). (e) UL123 with PI controller (simulations). (f) UL123 with P+resonant controller (simulations).

Fig. 13. Simulation showing the influence of nonlinear loads (six pulse diode rectifier with capacitive filter) on the output ac voltage UL1 , UL2 , and UL3
(vertical: 185 V/div and horizontal: 10 ms/div). (a) AC voltage (predictive controller). (b) AC voltage (PI controller). (c) AC voltage (P+resonant controller).

Fig. 11 shows the experimental results of the sensitive load ac

voltage when an additional load is plugged in (fifth horizontal
division), increasing power consumption by 50% relative to the
nominal. The results show that the optimal predictive controller
avoids transient disturbances [Fig. 11(a)] on the load ac voltages. Using the synchronous PI or the P+resonant controllers, a
transient sag appears in the load ac voltages (Fig. 11(b) and (c),
respectively). The sag is deeper when using the synchronous PI
controller [Fig. 11(b)].
By unplugging the additional load, experiments show that
the optimal predictive controller is able to track the output ac
voltage references. However, a transient voltage swell appears,
with height similar to the sag depth shown in Fig. 11(b) and (c),
respectively, when using the synchronous PI or the P+resonant
controllers.
A nonlinear load (six pulse diode rectifier with an inductive
filter), with 50% of the nominal load power, was plugged in the

ac load voltage. The THD of the nonlinear load ac currents is

approximately 31.3%. Due to the line impedance (RLine and
LLine ), it originates an ac output voltage THD of 4.6% when
using the optimal predictive controller, 5.8% when using the
PI controller, and 7.5% when using the P+resonant controller
(Fig. 12).
Fig. 13 shows the simulation results of the output ac voltage
when a six pulse diode rectifier with capacitive filter, having
50% of the nominal load power, is plugged in the ac load
voltage. The THD of the ac output voltage is 4.7%, 5.8%, and
7.6% when using the optimal predictive, PI, and P+resonant
controllers, respectively. This shows that the optimal predictive
controller is also better in decreasing the ac output THD; like
all the controllers, it was designed to maintain precise ac load
voltages.
The experimental tests in Figs. 12 and 13 were repeated, connecting the filter capacitor on the NPC converter side and using

2758

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

Fig. 14. Experimental results of the ac voltage sag U1 , U2 , and U3 ; the injected voltages of the DVR UL1 U1 , UL2 U2 , and UL3 U3 ; and the load ac voltage
at the sensitive load UL1 , UL2 , and UL3 using the optimal predictive controller, with the filtering capacitor (a)(c) placed on the line side and (d)(f) placed on
the NPC converter side (vertical: 370 V/div and horizontal: 20 ms/div). (a) AC voltage (line-side C filter). (b) Injected voltages (line-side C filter). (c) Output ac
voltage (line-side C filter). (d) AC voltages (converter-side filter). (e) Injected voltages (converter-side filter). (f) Load ac voltages (converter-side filter).

Fig. 15. Experimental results of the unbalanced ac voltage sag U1 , U2 , and U3 ; the injected voltages of the DVR UL1 U1 , UL2 U2 , and UL3 U3 ; and the
output ac voltage at the sensitive load UL1 , UL2 , and UL3 using the optimal predictive controller (vertical: 370 V/div and horizontal: 20 ms/div). (a) AC voltage
with unbalanced sag. (b) Injected voltages. (c) Load ac voltages.

the predictive equations (7) and (8). As expected, the obtained

results did not show any improvements over the obtained results
when using the capacitor on the ac line side.
C. DVR Mitigation of Balanced or Unbalanced Sags and
AC Power Short Interruptions
The output ac voltage controllers (Section II) and the two
filtering topologies (Fig. 1) were tested to evaluate the performance of the sensitive load ac voltage when sags happened in
the ac network voltages. Control predictive equations (7) and
(8) were used to evaluate the results when the filter capacitor
is placed on the converter side. Fig. 14(a) and (d) shows the
balanced voltage sag, which reduces the ac voltages to 50% in
approximately 120 ms.
During the sag occurrence [between horizontal divisions 2
and 8 in Fig. 14(a) and (d)], the NPC converter injects voltages

[Fig. 14(b) and (e)] to mitigate the sag, whose references

are calculated using the output ac voltage optimal predictive
controller applied to the line-side capacitor filtering topology
[Fig. 14(b)] or to the NPC converter-side capacitor [Fig. 14(e)].
The NPC converter, with the filtering capacitor on the
NPC converter side, causes transient notches or overshoots
[Fig. 14(f)] at the beginning or at the end of the sag, respectively. Oppositely, the line-side capacitor filtering topology
enables sensitive load voltages with constant amplitude and no
notches or overshoots [Fig. 14(c)]. As expected, this topology
improves power quality and protects sensitive loads from network ac voltage sags, without notches or overshoots. Similar
results were obtained when using the PI and the P+resonant
controllers.
The experimental results in Fig. 15(a) show an unbalanced
50% voltage sag, occurring in phase 1, U1 , [between horizontal
divisions 2 and 8 in Fig. 15(a)]. The predictive controller of

BARROS AND SILVA: MULTILEVEL OPTIMAL PREDICTIVE DYNAMIC VOLTAGE RESTORER

2759

Fig. 16. Experimental results of the ac voltages U1 + 740 V, the output ac voltage UL1 , and the injected voltage UL1 U1 740 V during a short interruption
followed by restoring the network ac voltages (vertical: 370 V/div and horizontal: 100 ms/div). (a) U1 , UL1 , and UL1 U1 (short interruption transient). (b) U1 ,
UL1 , and UL1 U1 (ac voltage restoring transient).

the NPC converter-based DVR injects unbalanced voltages in

series with the ac voltages to dynamically regulate the output
ac voltage [Fig. 15(b)]. The output ac voltages at the sensitive
load show balanced and constant voltage amplitude [Fig. 15(c)].
Similar experiments using the PI or the P+resonant controllers
show a slight unbalanced load voltage for the P+resonant
controller.
The DVR behavior was tested using laboratory-produced
short interruptions in the ac network voltages. Fig. 16(a) shows
U1 , the network ac voltage UL1 , the injected voltage of the optimal predictive controlled DVR, and UL1 U1 during the beginning of the short interruption transient. The results [Fig. 16(a)]
indicate that the multilevel NPC converter-based DVR injects a
voltage to maintain the amplitude of the load voltage constant,
in spite of the network voltage falling to zero. There is no load
interruption, neither noticeable power quality issues.
After the ac network short interruption, the ac voltages were
restored [Fig. 16(b)]. The experimental results show that, as
the ac U1 voltage increases, the voltage injected by the DVR
decreases to keep the ac load voltage constant [Fig. 16(b)].
Synchronous PI and P+resonant controllers present similar
performance during the short interruption, provided that correct
fundamental frequency and phase generation are maintained.
By placing the filtering capacitor in the NPC converter
side, the DVR is still able to dynamically mitigate the short
interruption at the expense of a higher distortion due to their
comparatively lower bandwidth.
V. C ONCLUSION
This research paper has proposed an optimized multilevel
DVR to improve power quality at sensitive loads. The feedback
system is based on optimal predictive controllers applied to
NPC multilevel converters: 1) optimal predictive controller to
generate the DVR reference voltages to inject; 2) an optimal
predictive phase quadrature synchronizer to detect the phase
and fundamental frequency of the ac network; and 3) optimal
predictive multilevel current control to enforce the voltage
references.
The performance of the optimal predictive controller generating the reference voltages to inject was compared to the
synchronous dq frame PI controller and to the P+resonant
controller. The results show that predictive controllers present

the lowest THD levels in the load ac voltages, are able to

regulate unbalanced load ac voltages, allow plug in and out of
extra loads without causing swells, sags, notches, or overshoots,
and reduce the distortion of nonlinear load ac voltages.
The LC filter capacitor should be connected in the line side
since this topology allows a relatively faster dynamic response,
enabling the elimination of voltage notches or spikes in the
beginning and in the end of sags and strong load voltage THD
reduction.
The proposed optimal predictive controllers optimize the
overall DVR feedback control system, being able to mitigate
balanced and unbalanced sags and short interruptions with
balanced or unbalanced loads. Using a multilevel converter and
choosing the line-side connected filter capacitor, the ac sensitive
load voltage THD is reduced to values lower than 1%, with the
DVR behaving also as a series APF for the ac load voltages.
Thus, the optimal predictive DVR improves twofold the power
quality of sensitive loads.
R EFERENCES
[1] M. F. McGranaghan, D. R. Mueller, and M. J. Samotyj, Voltage sags in
industrial systems, IEEE Trans. Ind. Appl., vol. 29, no. 2, pp. 397403,
Mar./Apr. 1993.
[2] D.-M. Lee, T. G. Habetler, R. G. Harley, T. L. Keister, and J. R. Rostron,
A voltage sag supporter utilizing a PWM-switched autotransformer,
IEEE Trans. Power Electron., vol. 22, no. 2, pp. 626635, Mar. 2007.
[3] C. Fitzer, M. Barnes, and P. Green, Voltage sag detection technique for a
dynamic voltage restorer, IEEE Trans. Ind. Appl., vol. 40, no. 1, pp. 203
212, Jan./Feb. 2004.
[4] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, A multilevel converterbased universal power conditioner, IEEE Trans. Ind. Appl., vol. 36, no. 2,
pp. 596603, Mar./Apr. 2000.
[5] J. G. Nielsen, M. Newman, H. Nielsen, and F. Blaabjerg, Control and
testing of a dynamic voltage restorer (DVR) at medium voltage level,
IEEE Trans. Power Electron., vol. 19, no. 3, pp. 806813, May 2004.
[6] P. Anish, K. Neha, and D. Deepak, Zero energy storage voltage sag
correctors for industrial applications, in Proc. 38th Annu. IEEE Power
Electron. Spec. Conf., Jun. 2007, pp. 30863091.
[7] J. G. Nielsen and F. Blaabjerg, A detailed comparison of system topologies for dynamic voltage restorers, IEEE Trans. Ind. Appl., vol. 41, no. 5,
pp. 12721280, Sep./Oct. 2005.
[8] E.-C. Nho, I.-D. Kim, T.-W. Chun, and H.-G. Kim, Cost-effective power
quality disturbance generator for the performance test of custom power
devices, in Proc. 30th IEEE IECON, Nov. 2004, vol. 2, pp. 16061610.
[9] S. S. Choi, B. H. Li, and D. M. Vilathgamuwa, Design and analysis of
the inverter-side filter used in the dynamic voltage restorer, IEEE Trans.
Power Del., vol. 17, no. 3, pp. 857864, Jul. 2002.
[10] H. Kim and S.-K. Sul, Compensation voltage control in dynamic voltage
restorers by use of feed forward and state feedback scheme, IEEE Trans.
Power Electron., vol. 20, no. 5, pp. 11691177, Sep. 2005.

2760

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

[11] Y. W. Li, F. Blaabjerg, D. M. Vilathgamuwa, and P. C. Loh, Design and

comparison of high performance stationary-frame controllers for DVR
implementation, IEEE Trans. Power Electron., vol. 22, no. 2, pp. 602
612, Mar. 2007.
[12] M. J. Newman, D. G. Holmes, J. G. Nielson, and F. Blaabjerg, A dynamic
voltage restorer (DVR) with selective harmonic compensation at medium
voltage level, IEEE Trans. Ind. Appl., vol. 41, no. 6, pp. 17441753,
Nov./Dec. 2005.
[13] C. Meyer, R. W. De Doncker, Y. W. Li, and F. Blaabjerg, Optimized
control strategy for a medium-voltage DVRTheoretical investigations
and experimental results, IEEE Trans. Power Electron., vol. 23, no. 6,
pp. 27462754, Nov. 2008.
[14] T. Jimichi, H. Fujita, and H. Akagi, Design and experimentation of a
dynamic voltage restorer capable of significantly reducing an energystorage element, IEEE Trans. Ind. Appl., vol. 44, no. 3, pp. 817825,
May/Jun. 2008.
[15] L. G. Franquelo, J. Rodrguez, J. I. Leon, S. Kouro, R. Portillo, and
M. A. M. Prats, The age of multilevel converters arrives, IEEE Ind.
Electron. Mag., vol. 2, no. 2, pp. 2839, Jun. 2008.
[16] A. Nabae and I. Takahashi, A new neutral-point-clamped PWM inverter,
IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523, Sep./Oct. 1981.
[17] T. A. Meynard and H. Foch, Multi-level choppers for high voltage applications, EPE J., vol. 2, no. 1, pp. 4550, Mar. 1992.
[18] P. Lezana, R. Aguilera, and D. E. Quevedo, Model predictive control
of an asymmetric flying capacitor converter, IEEE Trans. Ind. Electron.,
vol. 56, no. 6, pp. 18391846, Jun. 2009.
[19] M. Marchesoni, M. Mazzucchelli, and S. Tenconi, A non conventional
power converter for plasma stabilization, in Proc. IEEE Power Electron.
Spec. Conf., Apr. 1988, pp. 122129.
[20] B. Wang, G. Venkataramanan, and M. Illindala, Operation and control
of a dynamic voltage restorer using transformer coupled H-bridge converters, IEEE Trans. Power Electron., vol. 21, no. 4, pp. 10531061,
Jul. 2006.
[21] J. I. Leon, S. Vazquez, S. Kouro, L. G. Franquelo, J. M. Carrasco, and
J. Rodrguez, Unidimensional modulation technique for cascaded multilevel converters, IEEE Trans. Ind. Electron., vol. 56, no. 8, pp. 2981
2986, Aug. 2009.
[22] B. P. McGrath, D. G. Holmes, and T. Lipo, Optimized space vector
switching sequences for multilevel inverters, IEEE Trans. Power Electron., vol. 18, no. 6, pp. 12931301, Nov. 2003.
[23] D. G. Holmes and T. A. Lipo, Pulse Width Modulation for Power Converters. Hoboken, NJ: Wiley, 2003.
[24] M. H. Rashid, J. F. Silva, and S. F. Pinto, Power Electronics Handbook,
2nd ed. New York: Academic, 2006, ch. 34.
[25] X. Yu and O. Kaynak, Sliding-mode control with soft computing: A
survey, IEEE Trans. Ind. Electron., vol. 56, no. 9, pp. 32753285,
Sep. 2009.
[26] M. P. Kazmierkowski and L. Malesani, Current control techniques for
three-phase voltage-source PWM converters: A survey, IEEE Trans. Ind.
Electron., vol. 45, no. 5, pp. 691703, Oct. 1998.
[27] P. Correa, M. Pacas, and J. Rodrguez, Predictive torque control for
inverter-fed induction machines, IEEE Trans. Ind. Electron., vol. 54,
no. 2, pp. 10731079, Apr. 2007.
[28] J. D. Barros and J. F. Silva, Optimal predictive control of three-phase
NPC multilevel converter for power quality applications, IEEE Trans.
Ind. Electron., vol. 55, no. 10, pp. 36703681, Oct. 2008.
[29] J. Rodrguez, J. Pontt, C. A. Silva, P. Correa, P. Lezana, P. Corts, and
U. Ammann, Predictive current control of voltage source inverter, IEEE
Trans. Ind. Electron., vol. 54, no. 1, pp. 495503, Feb. 2007.
[30] J. D. Barros and J. F. Silva, Optimal predictive control of three-phase
NPC multilevel inverter: Comparison to robust sliding mode controller,
in Proc. 38th Annu. IEEE Power Electron. Spec. Conf., Orlando, FL,
Jun. 1721, 2007, pp. 20612067.
[31] R. Vargas, P. Corts, U. Ammann, J. Rodrguez, and J. Pontt, Predictive
control of a three-phase neutral-point-clamped inverter, IEEE Trans. Ind.
Electron., vol. 54, no. 5, pp. 26972705, Oct. 2007.

[32] P. Corts, M. P. Kazmierkowski, R. M. Kennel, D. E. Quevedo, and

J. Rodrguez, Predictive control in power electronics and drives, IEEE
Trans. Ind. Electron., vol. 55, no. 12, pp. 43124324, Dec. 2008.
[33] S. Kouro, P. Corts, R. Vargas, U. Ammann, and J. Rodrguez, Model
predictive controlA simple and powerful method to control power
converters, IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 18261838,
Jun. 2009.
[34] P. Rodrguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and
D. Boroyevich, Decoupled double synchronous reference frame PLL for
power converters control, IEEE Trans. Power Electron., vol. 22, no. 2,
pp. 584592, Mar. 2007.
[35] J. D. Barros and J. F. Silva, Optimal predictive phase quadrature synchronization controller, Portuguese Patent PT-104141, Jul. 2008.
[36] J. D. Barros, Converso Electrnica Multinvel: Optimizao para Aplicaes em Qualidade de Energia Elctrica, Ph.D. dissertation, Tech.
Univ. Lisbon, IST, Lisbon, Portugal, 2008.
[37] Y. W. Li, D. M. Vilathgamuwa, P. C. Loh, and F. Blaabjerg, A dualfunctional medium voltage level DVR to limit downstream fault currents,
IEEE Trans. Power Electron., vol. 22, no. 4, pp. 13301340, Jul. 2007.
[38] C. V. Jones, The Unified Theory of Electrical Machines. New York:
Plenum, 1967.
[39] K. Ogata, Modern Control Engineering, 4th ed. Englewood Cliffs, NJ:
Prentice-Hall, 2002.
[40] D. N. Zmood, D. G. Holmes, and G. H. Bode, Frequency-domain analysis of three-phase linear current regulators, IEEE Trans. Ind. Appl.,
vol. 37, no. 2, pp. 601610, Mar./Apr. 2001.

J. Dionsio Barros (S04M09) was born in

Madeira Island, Portugal, in 1974. He received the
Dipl.Ing. degree in systems and computer engineering from the University of Madeira, Funchal,
Portugal, in 1998 and the M.Sc. and Ph.D. degrees in electrical and computer engineering from
the Instituto Superior Tcnico, Technical University of Lisbon, Lisbon, Portugal, in 2002 and 2008,
respectively.
He is currently an Assistant Professor with the
Exact Sciences and Engineering Competence Center,
University of Madeira, and a Researcher with the Center for Innovation
in Electrical and Energy Engineering, Instituto Superior Tcnico, Technical
University of Lisbon. His main interests are modeling, simulation, and control
of multilevel converters applied to power quality.
Dr. Barros is a member of the Ordem dos Engenheiros, Portugal.
J. Fernando Silva (M92SM00) was born in
Mono, Portugal, in 1956. He received the Dipl.Ing.
degree in electrical engineering and the Ph.D. and
Habilitation degrees in electrical and computer engineering from the Instituto Superior Tcnico, Technical University of Lisbon, Lisbon, Portugal, in 1980,
1990, and 2002, respectively.
He is currently an Associate Professor of power
electronics with the Energy Group, Department
of Electrical and Computer Engineering, Technical
University of Lisbon. He teaches power electronics,
control of switching power converter systems, and power quality. As the leader
of the group Power Electronics and Power Quality, Center for Innovation
in Electrical and Energy Engineering, Instituto Superior Tcnico, Technical
University of Lisbon, his main research interests include modeling, simulation,
topologies, and advanced control of power electronics systems and power
quality. He has supervised seven Ph.D. theses and is currently cosupervising
four Ph.D. students. He has published two books (in Portuguese) and more than
200 papers in international journals, books, and conferences with reviewers.
Dr. Silva is a member of the Ordem dos Engenheiros, Portugal.