Design-for-Test (DFT) using RTL

Compiler

Agenda
Basic DFT Flow
Defining Scan Setup & Running DFT Rules Check
Mapping Design to Scan & Shift-register Identification
Configuring & Connecting Scan Chains
Hierarchical Scan Insertion
Inserting Compression Structures
Interface to other Tools

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Encounter DFT Flow

Read design information
Define full scan control signals
Define full scan chains
Define compression signals
Synthesize to generic logic
Run DFT Rule Checker
Fix DFT Violations

Shift Enable & Test Mode Signals

Prevent scan mapping of flops
Internal clocks as Test Clocks
DFT controllable constraints
Abstract Scan Segments

Add Testability Logic

Insert Boundary Scan Logic

Denotes an optional step

Synthesize and map to scan

Test point insertion
Configure & Connect Scan Chains
Insert compression logic
Netlist, SDC, ScanDEF, ATPG,
Abstraction Model

Export to Encounter Test

Export to P&R Tool

Verify test structures & Generate

Test Patterns

Reorder scan chains

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Export to Encounter Conformal

Verify Netlist

Encounter RC DFT: Input and Output

Synthesis
Libraries

SDC
File

RTL
Files

Constraint
Files
(SDC, CTL,
Scan Abstract)

Encounter RTL Compiler (RC)

Gate-Level
Netlist
File

Scan
Abstract
Model
Scan DEF
File

Logic
Abstract
File

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Testability
Analysis
File

ATPG
Interface
Files

Setting Scan Style

The muxed scan style (muxed_scan) is the most commonly
used and is the default scan style used in RC-DFT
To set the scan style, enter the following root-level attribute:
set_attr dft_scan_style {muxed_scan | clocked_lssd_scan} /

Scan enable

System out/
Scan out

System Data
data_in

data_out

clk

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Scan In
System Clock

Non-scan Flip-Flop

clk

Multiplexer Scan Flip-Flop

Defining Test Mode Signals

Define the test mode signals (often, already coded in the RTL) to control
and use the existing test logic, and to enable the fixing of DFT violations:
define_dft test_mode [-name object_name]
-active {low | high} [-scan_shift] [-no_ideal]
[ [-hookup_pin pin [-hookup_polarity string]]
[-configure_pad {tm_signal}] [-create_port | -shared_in]]
{pin|port} [-design design]
No DFT violation after adding test_mode
control logic shown in RED
top_mod

div_clk

sub_mod

clk1

D
clk2
clk

enable
test_mode

test_mode
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clk3
Gated_clk

Defining Shift Enable Signal

Specify a pin or port that drives the shift_enable pin of the
scan flip-flops. Use the define_dft shift_enable constraint:
define_dft shift_enable [-name object_name]
-active {low|high} [-default] [-no_ideal]
[ [-hookup_pin pin [-hookup_polarity string]]
[-configure_pad {tm_signal|se_signal}] | -create_port ]
{pin|port} [-design design]

The muxed scan style uses shift-enable signals to switch scan flipflops from system mode to scan-shift mode. Define these signals
before running the DFT rule checker.
You can associate a shift enable with each scan chain; default is to
use the first shift-enable signal that is defined (default) as the scan
enable for all the scan chains.

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Auto Identification of Test Signals

For the muxed scan style - unless previously defined - the
DFT rule checker will
create a test clock for each top-level clock pin that is traceable from
the clock pin of a flip-flop to the primary input pin.
creates a test mode signal(s) of type scan shift that is traceable from
the async set and reset pins of a flip-flop to the primary input pin.
To turn off this feature, set the following attributes:
set_attribute dft_identify_top_level_test_clocks false /
set_attribute dft_identify_test_signals false /

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Internal Test Clocks

Define the internal clock branches
as separate test clocks when it is an
unbalanced clock-tree.
define_dft test_clock
-name test_clock
-domain test_clock_domain
-period integer
[-divide_period integer]
[-rise integer]
[-divide_rise integer]
[-fall integer]
[-divide_fall integer]
[-controllable]
{ pin_name [pin_name] ...}

With same test clock domain, RC uses lockup latch to join the chains.

Chain1

Lockup
latch

clk1a

clk1b

With separate clock domains, RC puts them

on separate chains.

chain1

If you use the same test clock

domain for both test clocks, you
allow all flip-flops to be mixed in one
scan chain. RC automatically adds
a lock-up latch for all clocks in the
same
domain.
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clk1a
chain2
clk1b

Defining DFT Controllable Constraints

To enable propagation of the test signal across the specified
pins of a black-box module, such as a PLL, use this
command:
set_attr dft_controllable "instance/fromPin
[non_inverting|inverting]" instance/toPin
PLL
A

clk
cki
n

ckp
ll

Example
set_attr dft_controllable PLLA/ckin inverting" PLLA/clkpll

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Splitting Clock Branches

U1
CLK

CK

CK

CK

CK

B1

U2
A

B2

By default, B1 and B2 can be treated as one clock (clk) and all flops can
be put on the same chain
Possibly for skew reasons, you might want to keep them as separate test
clocks, but in the same domain.
define_dft test_clock name SCKA domain SCK_D U1/Y
define_dft test_clock name SCKB domain SCK_D U2/Y
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Combining Equivalent Clock Inputs

CK

CK

CK

CK

CK_A

CK_B

To tell the DFT engine to treat above as the same clock for
scan chain hook-up purposes, use the following command:

define_dft test_clock -name SCK -domain SCK_D CK_A CK_B

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Defining Scan Segments

You can define a set of elements as a scan segment for inclusion into a
scan chain. Such elements may have been previously stitched to create
a scan segment (abstract, boundary_scan, preserved) , or are specified
as a list of elements to be stitched into a scan segment (fixed, floating).
Scan segments are defined using
define_dft { abstract_segment | fixed_segment |
boundary_scan_segment | floating_segment |
dft_configuration_mode | preserved_segment |
shift_register_segment }

The different type of segments are described as followed:

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abstract_segment defines an abstract scan-chain segment object

fixed_segment defines a fixed scan-chain segment object
boundary_scan_segment defines a boundary-scan segment object
floating_segment defines a floating scan-chain segment object
preserved_segment defines a preserved scan-chain segment object
shift_register_segment defines a shift register scan-chain segment object

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Defining Configuration Mode

You can use scan modes to build the top-level scan chains with specific
elements in different modes of operation (multimode)
define_dft dft_configuration_mode
[-name scan_mode_name]
[-mode_enable_high test_signal]
[-mode_enable_low test_signal]
[-jtag_instruction jtag_instruction]
[design]
Example
The following example defines scan mode scanModeA whose pin1 is
specified to have an active high logic value and pin2 is specified to have
an active low-logic value in this mode of operation:
define_dft dft_configuration_mode -name scanModeA design \
-mode_enable_high pin1 -mode_enable_low pin2
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Defining Scan Chains

The chain-specific constraints instruct the scan configuration engine to
bind the scan flops configured into the top-level chains to a specific set of
scan data input and output signals for the specified test-clock domain and
edge. To define a top-level scan chain, use:
define_dft scan_chain [-name name]
{-sdi sdi_name -sdo sdo_name [create_ports] { [-shared_output]
[-shared_select test_signal]| -non_shared_output}
[-shift_enable test_signal]
[-head segment_name] [-tail segment_name][-body segment_name]
[-complete | -max_length integer]
[-domain test_clock_domain [-edge {rise|fall}]]
[-terminal_lockup {level_sensitive | edge_sensitive}]
[-configure_pad {tm_signal | se_signal} ] [analyze]

To control the prefix used to name user-defined scan chains, set the
following root attribute:
set_attr dft_prefix SCAN_ /
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RTL Top-down Design-for-Testability (DFT) Flow

Read Target Libraries
Read HDL files
Elaborate Design
Set Timing & Design Constraints
Apply Optimization Directives
Setup for DFT Rule Checker
Run DFT Rule Checker and
Report Registers
Fix DFT Violations
Add Testability Logic
Synthesize Design + Map to Scan
Test Point Insertion
Configure Scan Chains
Connect Scan Chains
Run Incremental Optimization
Analyze Design
Netlist, SDC,
ScanDEF, ATPG, Abstraction
Model
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Check DFT Rules

DFT Information Hierarchy

/ (root)

/designs

/libraries

/hdl_libraries

dft

design_name
dft

reports

actual_scan_chains

scan_chains

actual_scan_segments

scan_segments

violations

test_clock_domains
test_signals

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/messages

boundary_scan

jtag_ir

dft_configuration
_modes

jtag_instructions

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Basic DFT Rule Checks

Following are the some of the supported rule checks:
Uncontrollable clock nets

Internally generated clocks (such as a clock divider)

Gated clocks
Tied constant clock nets
Undriven clock nets

Uncontrollable asynchronous set/reset nets

Internally generated asynchronous set/reset signals

Gated asynchronous set/reset nets
Tied active asynchronous set/reset pins
Undriven asynchronous set/reset pins

Conflicting clock and asynchronous set/reset nets

Shift Register Rules
Set/Reset are controlled OFF during scan shift
Clocks are turned ON
Shift register data pins connected properly to pass the data.

Abstract Segment Rules

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Advanced DFT Rule Checks

The following are some of the advanced DFT rule checks:

Tristate contention for internal and external nets

Same asynchronous set or reset data race conditions
Clock and data race conditions
Floating nets violations
X-source violations

This feature needs Encounter Test Architect advanced

license in order to be executed

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Checking for DFT Rules

To check for any DFT violations, use the following
command:
check_dft_rules [design] [-advanced]
[-max_print_violations integer | > file]
[-max_print_registers integer]
[-max_print_fanin integer]
[-dft_configuration_mode dft_config_mode_name]

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Checking DFT Rules Report

On executing check_dft_rules, DFT engine indicates the violations and the
probable cause of those violations
Users can refer to these messages to assess the DFT violations
Warning : DFT Clock Rule Violation. [DFT-301]
: # 0: internal or gated clock signal in module top, net: Iclk, pin g1/z
Effective fanin cone: clk, en
Warning : DFT Async Rule Violation. [DFT-302]
: # 1: async signal driven by a sequential element in module top, net:
Iset, pin Iset_reg/q
Effective fanin cone: Iset_reg/q
Violation # 0 affects 4 registers
Violation # 1 affects 4 registers
Note - a register may be violating multiple DFT rules
Total number of Test Clock Domains: 1
DFT Test Clock Domain: clk
Test Clock clk (Positive edge) has 1 registers
Test Clock clk (Negative edge) has 0 registers
Number of user specified nonscan registers: 0
Number of registers that fail DFT rules: 4
Number of registers that pass DFT rules: 1
Percentage of total registers that are scanable: 20%

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Reporting Scan Flops

To report the scanable status of the flip-flops after running the DFT rule
checker, use:
report dft_registers

This example shows the report for a design with an internally driven
clock signal and an asynchronous set signal
Reporting registers that pass DFT rules
Iset_reg PASS; Test clock: clk/rise
Reporting registers that fail DFT rules
out_reg_0 FAIL; violations: clock #(0 ) async set #(1 )
out_reg_1 FAIL; violations: clock #(0 ) async set #(1 )
out_reg_2 FAIL; violations: clock #(0 ) async set #(1 )
out_reg_3 FAIL; violations: clock #(0 ) async set #(1 )
Total registers that pass DFT rules: 1
Total registers that fail DFT rules: 47

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Testability Analysis
In RTL Compiler (RC), user can run different sets of testability analysis starting
as early as elaborating the design
check_dft_rules
Propagates the tied constants, shift-enable and test mode signal values to prune
the circuit and identify the test paths
Identifies constructs in the design that prevent the flops from being included into
the scan chains
RC can provide feedback on the source or cause of the DFT violation back to the
HDL whenever possible

check_atpg_rules
Generate scripts to run Encounter Test ATPG rule checker to ensure that the
design is ATPG ready

check_design
General design rule checker that identifies problems in the circuit, such as
unconnected nets and multidriven nets that impact the DFT coverage

analyze_testability
This command runs Encounter Test ATPG to do a quick estimation of the fault
coverage
Can be used on an unmapped design in an assume scan mode. Accuracy
improves as design goes through mapping such as redundancy removal, and scan
chain hookup
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RTL Top-down Design-for-Testability (DFT) Flow

Read Target Libraries
Read HDL files
Elaborate Design
Set Timing & Design Constraints
Apply Optimization Directives
Setup for DFT Rule Checker
Run DFT Rule Checker and
Report Registers
Fix DFT Violations
Add Testability Logic
Synthesize Design + Map to Scan
Test Point Insertion
Configure Scan Chains
Connect Scan Chains
Run Incremental Optimization
Analyze Design
Netlist, SDC,
ScanDEF, ATPG, Abstraction
Model
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Fix DFT Violations

Fixing DFT Violations

To automatically fix the DFT violations, use the fix_dft_violations command:
fix_dft_violations
{ -clock -test_control test_signal -test_clock_pin {pin|port}
[-rise | -fall] | {-async_set | -async_reset | -async_set
-async_reset} -test_control test_signal [-async_control
test_signal] [-insert_observe_scan [-test_clock_pin {pin|port}
[-rise | -fall]]] }
[-violations violation_object_id_list -test_control test_signal]
[-tristate_net] [-xsource [-exclude_xsource instance]...]
[-preview] [dont_map] [-dont_check_dft_rules] [-design design]
This command allows the user to:

Control the type of violation to fix, either -async_set, -async_reset, or -clock

Specify the test clock to use through the -test_clock option
Specify a test-mode signal to control the added logic through the test_control option
Display the modifications before making the fixes using -preview option
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Fixing Specific Violations

Report of the DFT Violations
rc:/> report dft_violations
Total 2 violations (muxed_scan)
Async. set/reset Rule Violations
================================
Reporting 1 async set/reset violations
Violation #1:
Object name: vid_1_async
Type: async violation
Description: [ASYNC-05] async signal driven by a sequential element
Source: Iset_reg/q (test3.v:13)
Number of registers affected: 4
Affected registers:
out_reg[0]
...

The following command fixes violation vid_1 if the violation is of type async_set:
fix_dft_violations -violations {vid_1_async} -async_set test_control tm
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Example of Asynchronous Violations

2:1

rst_b

TM A

2:1

rst

TM B

2:1

rst

TM

reset
logic

Solution 1: Add a 2:1 mux to select

reset port during test_mode.
ERROR : Cannot control all resets to same value
due to pos/neg resets and inversion of reset signal,
and modification of other logic

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D
other
logic

Solution 2: Add muxing logic to

each branch as required

define_dft test_mode -name TM1 -active high TM

fix_dft_violations -async_set -async_reset test_mode TM1
Successfully inserted common test-point at node
C/aclr. It covers 2 nodes:
C/aclr, D/aclr
Successfully inserted test-point at node A/aclr.
Successfully inserted test-point at node B/aclr.
Total number of violation points: 4
Total number of test points inserted: 3

Example: Internally Generated Clock

CK

Clock
Divider

div_ck

2:1

TM
Problem: div_ck is not controllable from the top-level port.
Sol: Add 2:1 MUX to bypass Clock Divider Circuit controlled by TM signal
define_dft test_mode -name tm -active high TM
fix_dft_violations -clock -test_mode tm -test_clock_pin
CK
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Debugging DFT Violations

In case of suspect DFT violations, to query the test mode
logic values propagated along the test path due to tied
constants, shift-enable, and test mode signals values, use
the following command :
dft_trace_back

This command is usually applied on a pin and will return

the propagated logic value (if found), or no_value.
Following example traces back on the requested pin and in
this case a constant logic 1 value is reported:
dft_trace_back /designs/top/instances_hier/g121/pins_in/CME

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RTL Top-down Design-for-Testability (DFT) Flow

Read Target Libraries
Read HDL files
Elaborate Design
Set Timing & Design Constraints
Apply Optimization Directives
Setup for DFT Rule Checker
Run DFT Rule Checker and
Report Registers
Fix DFT Violations
Add Testability Logic
Synthesize Design + Map to Scan
Test Point Insertion
Configure Scan Chains
Connect Scan Chains
Run Incremental Optimization
Analyze Design
Netlist, SDC,
ScanDEF, ATPG, Abstraction
Model
30

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Scan Synthesis

Preserving Non-scan Flops During Synthesis

Use the following attribute to prevent conversion of a flop to
a scan-flop
set_attr dft_dont_scan true flip-flop_object

To preserve a complete subdesign that was previously

mapped to gates, use
set_attr dft_scan_map_mode preserve
/top/subdesign_name

Run the DFT rule checker to update the DFT status of all
flip-flops in the lower-level blocks attributed with preserve
check_dft_rules
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Identifying Shift Registers in the Design

To allow RC to identify the shift-registers during mapping, user can
specify following command. User has to ensure that check_dft_rules is
clean before invoking this command:
synthesize to_mapped auto_identify_shift_register

If the design has a large number of shift registers, user can use the twopass flow also to automatically identify the shift-register segments in the
design (post synthesis):
identify_shift_register_scan_segments
-min_length 2 -max_length 2000 [-preview]
replace_scan to_non_scan

To manually identify the shift registers in the design, user can use the
following command:
define_dft shift_register_segment -name shiftReg \
-start_flop tmp_reg[0] -end_flop tmp_reg[7]
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Controlling Connection of Scan Signals

To leave the scan data pins floating or to connect them to
ground, set the following attribute (default: loopback):
set_attr dft_connect_scan_data_pins_during_mapping
{floating|ground|loopback} /designs/top_design

To leave the shift-enable pins floating, set the following

attribute (default: tieoff):
set_attr dft_connect_shift_enable_during_mapping
{floating|tieoff} /designs/top_design

Specify the scan flip-flop output pin to use for the scan data
path connection (default: auto):
set_attr dft_scan_output_preference
{auto|non_inverted|inverted} top

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Synthesize and Map the Scan Flops

Use the following attribute to select the approach to
mapping the registers. To map to scan flops for DFT, use
either the force_all (does not require the DFT rule checks to
be run) or tdrc_pass (mapped to scan for flops that pass
the DFT rule checks) (default: tdrc_pass) :
set_attr dft_scan_map_mode {tdrc_pass|force_all|preserve}

All registers that pass the DFT rule checks that are not
attributed with a dft_dont_scan or a preserve (if non-scan
flops) are mapped to scan flops during synthesis.
synthesize to_mapped [-auto_identify_shift_register]

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Fixing DFT Violations on a Scan-Mapped Design

Following initial synthesis, you can still fix the DFT rule
violations in the mapped netlist by running the
fix_dft_violations command. To convert the remaining flipflops that now pass the DFT rule checks to scan flip-flops,
run this command:
replace_scan

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2013 Cadence Design Systems, Inc. All rights reserved.

RTL Top-down Design-for-Testability (DFT) Flow

Read Target Libraries
Read HDL files
Elaborate Design
Set Timing & Design Constraints
Apply Optimization Directives
Setup for DFT Rule Checker
Run DFT Rule Checker and
Report Registers
Fix DFT Violations
Add Testability Logic
Synthesize Design + Map to Scan
Test Point Insertion
Configure Scan Chains
Connect Scan Chains
Run Incremental Optimization
Analyze Design
Netlist, SDC,
ScanDEF, ATPG, Abstraction
Model
36

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Configure & Connect

Scan Chains

Setting Minimum Number of Scan Chains

By default, the scan configuration engine inserts one scan chain per
active edge (rising and falling) of each test clock domain
By default, there is no limit for the scan chain length. User can control
the scan configuration by specifying the maximum length of a scan
chain in the design
To specify the minimum number of scan chains to create, set the
following design attribute:
set_attribute dft_min_number_of_scan_chains integer
/designs/top

To specify the maximum length of any scan chain, set the following
design attribute:
set_attribute dft_max_length_of_scan_chains integer
/designs/top

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Example of a Minimum Number of Scan Chains

RTL
300 rising-edge scan flip-flops in test clock domain: clk1
100 falling-edge scan flip-flops in test clock domain: clk2

Constraint
set_attr dft_min_number_of_scan_chains 5 /designs/top

What Is the Configuration Output?

The scan configuration engine creates 5 scan chains, whose
lengths are balanced across the test-clock domains:
4 scan chains of 75 scan flops each in test-clock domain: clk1
1 scan chain of 100 scan flops each in test-clock domain: clk2

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Example of a Maximum Length of Scan Chains

RTL
Test-clock domain clk1 rising edge clk1 has 16 scan flip-flops.
falling edge clk1 has 8 scan flip-flops.
Test-clock domain clk2 rising edge clk2 has 32 scan flip-flops.

Constraint
set_attr dft_max_length_of_scan_chains 8 /designs/top
set_attr dft_mix_clock_edges_in_scan_chain false /designs/top

Configuration Output
Because the dft_mix_clock_edges_in_scan_chains attribute is set to false, the scan configuration
engine creates at least one scan chain for each active (rising and falling) edge of test clock, clk1.

2 chains with 8 scan flip-flops of rising edge of test clock clk1 &1 chain with 8 scan
flip-flops of falling edge of test clock clk1
4 chains with 8 scan flip-flops of rising edge of test clock clk2
If the dft_mix_clock_edges_in_scan_chains attribute is set to true, then the configuration output is 3
scan chains of 8 flops with test clock clk1 and 4 with 8 scan flops of test clock clk2 as the edges do not
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Controlling Data Lockup Elements

If multiple test clocks are defined in the same test clock
domain, and mixing of clock edges is allowed, then RTL
Compiler inserts data lockup elements accordingly between
the scan-chain segments triggered by the different test clocks
and triggering edges on the same scan chain
Scan1

Lockup
Flop

clk1a
Lockup
flop

clk1b
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Connecting Scan Chains

The connect_scan_chains command configures and
connects scan flip-flops (which pass the DFT rule checks)
into scan chains. The command works at the current level of
the hierarchy and all lower hierarchies instantiated in that
module. The design must be mapped to the target library
before connecting scan chains in a design
connect_scan_chains [auto_create_chains]
preview [design] [-incremental] [-chains chain_list] [dft_configuration_mode dft_config_mode_name]
[elements element_list] [-pack | -create_empty_chains] [physical] [-power_domain power_domain_list]

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Hierarchical Scan Flow

For implementing hierarchical scan flow, block-level test synthesis should

include:
Test clock domain analysis
DFT rule fixing
Map to scan flops for DFT
Creation of the block-level chains
Write the logic abstract model
Write the scan abstract model

Now the pre-processed blocks can be integrated at the next level using
following set of commands:
Read logic abstract model (optional)

Read scan abstract model

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This is primarily used when memory capacity at chip level is a concern.

Defines the scan architecture.

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Logic Abstract Model

The logic abstract model defines the pre-processed blocks
(sub-modules) in terms of its module port list, I/O
declarations & bit-widths
No additional logic or hierarchical instances are written to
the module description.
User can create a logic abstract model with the following
command:
write_hdl -abstract

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Example of Logic Abstract Model

Logic abstract model
module core(in1, out1, clk1, clk2, se, si, so);
input [3:0] in1;
input [1:0] si;
input clk1, clk2, se, si, so;
output [3:0] out1;
output [1:0] so;
endmodule //core

Block core definition includes the testrelated ports such as se, si, and so.

Top-level netlist
module test (inl. in2, m3. clk1, cIk2. out1, out2. out3. se, si. so);
input [3:0] inl. in2. in3:
input clkl, clk2, se. si;
output [3:0] out1. out2, out3:
output so;
reg [3:0] out1, out2;
always (posedge clk1)
out1 <= in1;
always (posedge clk2)
out2 <= in2;
core u_core (.clk1 (clk1), .clk2(clk2). .in1 (in3). .out1(out3)):
endmodule //test

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Block core instantiation lists its

functional ports. The test-related
ports are created and linked from
its logic abstract definition above.

Scan Abstract Model

A scan abstract model defines the scan chain architecture
for the design
Basically the scan abstract model does the following:
Defines the block-level chains as segments
Captures the test clocks (and their active edges)
Captures the block-level test mode setup signals

A scan abstract model can be applied to:

Logic abstract model

Blackbox instance
Timing model represented using LIBERTY description
White box, or gate-level representation of the block

Created using: write_dft_abstract_model

Read using: read_dft_abstract_model
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[-ctl]

Example of Scan Abstract Model

CTL Abstract Model
STIL 1.0 {
// CTL PXXXX.Y
// Design PXXXX.Y
}
Header {
...}
Signals {
...}
SignalGroups {
...}
SignalGroups Internal_scan {
"_si" = "in1[0]" + "in2[0]"; // #signals=2
"_so" = "out1[0]" + "out2[0]"; // #signals=2
}
ScanStructures Internal_scan {
ScanChain "chain1" {
ScanLength 10;
ScanIn "in1[0]";
ScanOut "out1[0]";
ScanEnable "se1";
}
ScanChain "chain2" {
ScanLength 10;
ScanIn "in2[0]";
ScanOut "out2[0]";
ScanEnable "se1";
}
}
Timing {
...}
//PatternBurst "__burst__" {
//...}
//PatternExec {
//...}
Procedures Internal_scan {
"load_unload" {
W "_default_WFT_";
V {"clk1"=0; "clk2"=0; "clk3"=0;
"se1"=1; "_so"=##;}
// (continued on the right)
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//
MacroDefs Internal_scan {
"test_setup" {
W "_default_WFT_";
V { "clk1"=0; "clk2"=0; "clk3"=0; }
V { "clk1"=0; "clk2"=0; "clk3"=0;
"SE"=#; }
}
}
Environment "test" {
CTLMode Internal_scan {
TestMode InternalTest;
DomainReferences {
SignalGroups Internal_scan;
ScanStructures Internal_scan;
Procedures Internal_scan;
MacroDefs Internal_scan;
}
Internal {
"clk1" {
Datatype MasterClock ScanMasterClock;
}
"clk2" {
Datatype MasterClock ScanMasterClock;
}
"clk3" {
Datatype MasterClock ScanMasterClock;
}
"se1" {
Datatype ScanEnable {
ActiveState ForceUp;
}
}
"rst" {
Datatype TestMode {
ActiveState ForceUp;
}
}
}
//

Scan Compression Architectures

XOR Compression
De-compressor uses broadcast scan
(default) or xor spreader network.
Compressor uses XOR compression.

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MISR Compression
De-compressor uses broadcast scan
(default) or xor spreader network.
Compressor uses MISR.

Inserting XOR Scan Compression Architecture

To insert XOR-based compression logic, user can make use
of the following command:
compress_scan_chains -compressor xor
[-channel_length | -ratio integer]
[-chains actual_scan_chain...]
[-decompressor {broadcast | xor [-spread_enable
test_signal]}]
[-master_control test_signal]
[-compression_enable test_signal]
[-mask {wide1|wide2}]

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Inserting MISR Scan Compression Architecture

To insert MISR-based compression logic, user should use
the following command:
compress_scan_chains -compressor misr
-ratio integer
[-chains actual_scan_chain...]
[-auto_create]
[-decompressor {broadcast | xor [-spread_enable
test_signal]}]
[-master_control test_signal]
[-compression_enable test_signal]
[-mask {wide0 | wide1 | wide2}

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Compression Control Signals

User needs to use the define_dft test_mode command to
define compression control signals
Use -shared_in option when shared with an existing functional pin.
Test control signals are identified using the dft_compression_signal
attribute
master_control
compression_enable
spread_enable
Masking Control Pins:
mask_clock, mask_enable,
mask_load
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Dedicated pin for compression test purposes.

When specified, this signal is ANDed- with the
compression_enable test signal.
Provides a single pin constraint for LEC verification.
Signal that enables test compression.
Can be shared with an existing functional pin provided its
specified with master_control.
Signal that selects the XOR de-compressor spreader network.
Used with the decompressor xor option
Can be shared with an existing functional pin.
All can be shared with an existing functional pin. However,
should not use an existing fullscan test clock pin as the mask
clock because the fullscan test clock pins are not gated with
~CMLE (mask_load) signal.

Example of XOR Spreader Compression

Mentioned below is an example script that shows the
insertion of an XOR spreader and mask logic
compress_scan_chains ratio 2 \
-compression_enable CE -spread_enable SPRD \
-decompressor xor \
-mask wide1 \
-mask_enable MASK_E \
-mask_load MASK_L \
-mask_clock mask_clock_pin \
-mask_or_misr_sdi in3[3] -mask_or_misr_sdo out3[3]
-shared_output

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Compression Example Script

Following example shows compression being inserted without masking and

using a broadcast de-compressor:

Define two Top-Level Full Scan Chains:
define_dft scan_chain -name chain1 -sdi in1[0] -sdo out1[0] shared_out -shift_enable se1
define_dft scan_chain -name chain2 -sdi in2[0] -sdo out2[0]
-shared_out -shift_enable se2
Build and Report the Full Scan Chains
connect_scan_chains
report dft_chains
Define the Compression Test Signals
define_dft test_mode -active high -name CE in1[1] shared_in
define_dft test_mode active high name TM test_mode_pin
Compress the scan chains
compress_scan_chains ratio 2 compressor xor decompressor xor
-compression_enable CE -master_control TM
Shared compression_enable pin will be gated with dedicated master_control test pin.

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RTL Top-down Design-for-Testability (DFT) Flow

Read Target Libraries
Read HDL files
Elaborate Design
Set Timing & Design Constraints
Apply Optimization Directives
Setup for DFT Rule Checker
Run DFT Rule Checker and
Report Registers
Fix DFT Violations
Add Testability Logic
Synthesize Design + Map to Scan
Test Point Insertion
Configure Scan Chains
Connect Scan Chains
Run Incremental Optimization
Analyze Design
Netlist, SDC,
ScanDEF, ATPG, Abstraction
Model
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Interface to other Tools

Reporting DFT
To analyze the scan chains, run the following command:
report dft_chains

To report the DFT setup, run the following command:

report dft_setup > [filename]

To report the DFT registers, run the following command:

report dft_registers > [filename]

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Interface to ATPG Tool

write_atpg {-cadence [> file]| -mentor [> file]
| -stil [-dft_configuration_mode dft_config_mode_name]
[> file]}
[-decimals_ok] [-picoseconds] [-test_clock_waveform
test_clock]...
[-apply_inputs_at integer] [-apply_bidirs_at integer]
[-strobe_outputs_at integer] [-strobe_width integer]
apply_bidirs_at specifies when in the test clock cycle to apply the bidirectional
signals
apply_inputs_at specifies when in the test clock cycle to apply the input signals
strobe_outputs_at specifies when in the test clock cycle to strobe the outputs
strobe_width specifies how long the outputs are valid during the test clock cycle
decimals_ok writes out decimal numbers
test_clock_waveform specifies to use the clock waveform of the specified test clock
dft_configuration_mode specifies the object name of the scan mode for which to
write ATPG data

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Interface to Back-end Tool

To create a scanDEF interface file for scan chain reordering
in the P&R tool, user may want to use the following
command:
write_scandef [-partition partition -chains chain
[chain]...]...
[-version {5.4|5.5}]
[-end_chains_before_lockups]
[-dft_configuration_mode dft_config_mode_name]
[-dont_split_by_library_domains]
[-dont_split_by_power_domains]
[-dont_use_timing_model_pins] [design] [ > file]

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Exporting the Design to Encounter Test

Use the following commands to generate the corresponding
data:
write_et_atpg

to perform static stuck-at-fault (ATPG)

write_et_bsv

to perform boundary scan verification

write_et_dfa

to perform deterministic fault analysis and test-point selection

write_et_mbist

to generation MBIST tests

write_et_rrfa

to perform random resistant fault analysis and test-point selection

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