DEE6113: CMOS INTEGRATED

CIRCUIT DESIGN

CHAPTER OUTLINE
3.1: Know NMOS and PMOS transistor
3.2: Understand static CMOS inverter

3.3: Apply knowledge of inverter

characteristics
operation

in

CMOS

inverter

KNOW NMOS & PMOS TRANSISTOR

MOS transistor known as MOSFET (metal oxide

semiconductor field effect transistor).

MOSFET comprise of PMOS and NMOS. The

combination of these two devices form CMOS

technology. What is CMOS?

MOSFET is widely used nowadays in electronic

equipment,

e.g.

mobile

phone,

medical electronic equipment, etc.

computer,

KNOW NMOS & PMOS TRANSISTOR

NMOS

Symbol
Thin oxide

Cross section

KNOW NMOS & PMOS TRANSISTOR

PMOS

Symbol
Thin oxide

Cross section

KNOW NMOS & PMOS TRANSISTOR

Operations of MOS transistor under static condition:

Cut-off
Linear / Resistive
Saturation

In this section, we concentrate on NMOS device.

KNOW NMOS & PMOS TRANSISTOR

Cut-off

KNOW NMOS & PMOS TRANSISTOR

Channel existence

KNOW NMOS & PMOS TRANSISTOR

KNOW NMOS & PMOS TRANSISTOR

Linear / Resistive

KNOW NMOS & PMOS TRANSISTOR

Saturation

KNOW NMOS & PMOS TRANSISTOR

I-V

characteristics
of NMOS
transistor

KNOW NMOS & PMOS TRANSISTOR

I-V characteristics of NMOS vs. PMOS

NMOS

PMOS

CMOS

NMOS AS SWITCH
Vout

NMOS transistor switch model

Vout

PMOS AS SWITCH

Vout
a)

PMOS transistor switch model

Vout
b)

MOS TRANSISTOR AS SWITCHES

Function of MOS transistor as switch
PMOS

ON
Direct path exist
between Vout
and VDD
OFF

NMOS

OFF

ON
Direct path exist
between Vout and
ground node

UNDERSTAND STATIC CMOS

INVERTER
Why do we choose PMOS switch as Pull-up Network
(PUN) which is tied to VDD and NMOS switch as Pulldown Network (PDN) which tied to ground?

The answer is: VOLTAGE

DROP

UNDERSTAND STATIC CMOS

INVERTER

UNDERSTAND STATIC CMOS

INVERTER

UNDERSTAND STATIC CMOS

INVERTER
MOS TRANSISTOR AS PASS-TRANSISTOR
Widely used as an alternative to CMOS technology.
Pass transistor reduces the number of transistor required to

implement a logic.
Allow primary inputs to drive gate terminal as well as

source/drain terminals.
MOS transistor as pass-transistor

NMOS is called a degraded 1

PMOS is called a degraded 0

UNDERSTAND STATIC CMOS

INVERTER

UNDERSTAND STATIC CMOS

INVERTER
Transistors can be used as switches
g=0

g
s

Input g = 1 Output
0
strong 0

g=1
NMOS

d
g=0

g
s
s

g=1

Input
d

d
g=1
PMOS

degraded 1
g=0

Output
degraded 0

g=0

strong 1

CMOS INVERTER
Inverter is the most basic logic gate in Boolean

operation on a single input variable.

Symbol, circuit diagram and truth table of CMOS inverter

OPERATION

PMOS

NMOS

INVERTER SWITCH MODEL

Circuit diagram of inverter

CMOS INVERTER

When Vin is high and equal to VDD, the NMOS transistor is ON, while the
PMOS is OFF. A direct path exists between Vout and the ground node,
resulting in a steady-state value of 0V.
When the input voltage is low (0V), NMOS transistor is OFF, while PMOS
transistors in ON. A direct path exists between VDD and Vout, resulting in a
steady-state value of VDD.

VOLTAGE TRANSFER
CHARACTERISTICS (VTC)
Combining the IV characteristics of PMOS and NMOS

VOLTAGE TRANSFER CHARACTERISTICS (VTC)

NMOS off
PMOS res

NMOS sat
PMOS res
NMOS sat
PMOS sat

NMOS res
PMOS sat

NMOS res
PMOS off

CMOS inverter VTC is produced from IV curve of both NMOS and PMOS.

CHARACTERISTIC PARAMETERS
OF CMOS INVERTER

NOISE MARGIN
Noise margin is a measure of sensitivity of a gate to noise.
Represents the level of noise that can be sustained when

gates are cascaded.

Ability of a circuit to overpower a noise source.
VOH , VIH - nominal high voltage
VOL, VIL - nominal low voltage
VM gate or switching threshold voltage

VM

can

be

found

graphically

at

the

intersection of the VTC curve and the line

given by Vout = Vin.
The gate threshold voltage presents the
midpoint of the switching characteristics.

CMOS INVERTER IDEAL VTC

Ideally, VTC appears as
an inverted step-function.
We can see the precise
switching
and OFF.
Logic 1

Logic 0

between

ON

NOISE MARGIN
How much noise can a gate input see before it does not recognize the input?

PROPAGATION DELAY

PROPAGATION DELAY
Propagation delay of a gate defines how quickly it

responds to a change at its inputs and expresses

the delay experienced by a signal when passing
through a gate.
It is measured between 50% transition point of input

to output waveform.

PROPAGATION DELAY

 Static power reduction

Subthreshold current can be reduced by increasing

the Vt.

Selective application of multiple threshold

Control Vt through the body voltage.

 Static power reduction

Turn

OFF

power

supply

entirely.

MTCMOS circuit use low Vt transistor

for computation and high Vt transistor
as switch to disconnect the power
supply during ide mode.

Leakage

stack

effect

leakage

through 2 series OFF transistor is

much lower than a single transistor.

FAN-IN AND FAN-OUT

Fan-in:

Number of inputs.
The number of inputs to the gate.

gates with large fan-in are bigger

and slower

Fan-out:

Maximum number of similar gates

that a gate can drive.
Number of load gates connected
to the output of the driving gate.

gates with large fan-out are slower

 Dynamic power reduction

Decrease activity factor

Selective clock gating

Drawback: if the system in transition rapidly from an idle mode to a fully

active mode, a large i/t spike will occur.

Decrease switching capacitance

Small transistors

Careful floor planning to reduce interconnect

Decrease power supply

Adjust voltage depending on the operating mode

Decrease operating frequency

WHY CMOS INVERTER DISSIPATES LESS

POWER THAN BIPOLAR INVERTER?
CMOS

BJT

PMOS and NMOs never conducting TTL cannot function without some
at the same time. So, there is little
current drawn at all the time due to
or no current drawn by the circuit
the biasing condition.
from power supply except for what
is necessary to source current to
load.
In static (unchanging) condition, it
BJT is current-controlled device.
dissipates zero power (ideally)Current is drawn all the time and
static power dissipation.
contribute to power dissipation.
CMOS gate draw transient current
during switching- dynamic power
dissipation.
CMOS is voltage-controlled device.
So, it draw less current compared to
BJT.

VOLTAGE TRANSFER
CHARACTERISTIC (VTC)
Recap

Typical VTC

Ideal VTC

TRANSISTOR SIZING
(W/L RATIO)
Minimum length permitted by the technology is usually used as

the length for all channels.

When designing static CMOS circuits, it is advisable to

balance the driving strength of the transistor by making the

width of PMOS two or three times than the width of NMOS.

Ideally:

TRANSISTOR SIZING
(W/L RATIO)

TRANSISTOR SIZING
(W/L RATIO)
Impact of process variation on VTC curve
The good transistor has:
smaller oxide thickness
smaller length
higher width
smaller threshold voltage
The bad transistor has:
larger oxide thickness
larger length
lower width
larger threshold voltage
Conclusion:
The variations cause a small shift in the
switching threshold, but that the operation
of the gate is not affected.
Process variations (mostly) cause a shift in
the switching threshold.

TRANSISTOR SIZING
(W/L RATIO)

IMPACT OF SUPPLY
VOLTAGE SCALING
o The

inverter

characteristic

can

still

be

obtained although the supply voltage is small

(not even large enough to turn the transistors
on.)
o How does this happen?
o Because of sub-threshold operation of
the transistors.
o The sub-threshold currents are sufficient
to switch the gate between low and high
levels, and provide enough gain to
produce acceptable VTCs.
o However, the very low value of the switching
currents will slow down the operation of the

VTC of CMOS inverter for different

supply voltages

transistor.