AN1462

APPLICATION NOTE
Connecting the MPC555 32-bit
Microcontroller to the M616Z08 SRAM

INTRODUCTION
This application note describes a method of connecting the M616Z08 SRAM to the MPC555 Microcontrol-
ler. The M616Z08 is an advanced, 128 Kbit SRAM memory from ST Microelectronics, Inc., which is con-
figured with an 8 Kbit x 16 bus width. The MPC555 is a member of Motorola’s PowerPC family of
integrated microprocessors. It is a general-purpose, 32-bit microcontroller with a wide variety of applica-
tion areas, but it is particularly targeted toward automotive applications.

ADVANTAGES OF SRAM
The M616Z08 is a 128 Kbit (131,072 bits) CMOS SRAM, organized by 16 bits. It has an access time of
20ns and it will operate in the temperature range of –40 to 125°C. The device features fully static operation
requiring no external clocks or timing strobes, with equal address access and cycle times. It requires a
single 2.6V ± 10% or 3.3V ± 1-% supply, and all inputs and outputs are TTL compatible. Two WRITE en-
able pins allow writing to upper and lower bytes. The M616Z08 is available in a 44-lead SOIC package.

MPC555 BUS ARCHITECTURE

The MPC555’s Bus architecture can be daunting on first appearance. There are many control lines to al-
low for 8-bit accesses, 16-bit accesses, 32-bit accesses, bus arbitration, and so forth. Many applications
do not need to make use of these features. Only a simple connections is considered here. The MPC555
can be configured as Big-Endian or Little-Endian, with the normal configuration being Big-Endian. The
M616Z08 part is Big-Endian insofar as the hexadecimal data used to control the command interface uses
D0 to equate to the LSB.
The MPC555’s memory controller includes control lines that are suitable for connecting to the M616Z08
without the need for glue logic. The MPC555 is a 3.3V processor and will connect to the M616Z08 directly,
without the need for any transceivers. Software must set up the MPC555 registers to make the control
signals compatible with the M616Z08. How the registers are programmed is beyond the scope of this ap-
plication note. However, the M616Z08 can only operate in the asynchronous mode.

June 2004 1/7

AN1462 - APPLICATION NOTE

TABLE OF CONTENTS

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

ADVANTAGES OF SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

MPC555 BUS ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

M616Z08 BUS ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 1. M616Z08 Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 1. M616Z08 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
“Operational” Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. WE (0,1) States During Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DC Characteristics Comparison Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Input/Output DC Characteristics Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

MPC555 to M616Z08 CONNECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. MPC555 to M616Z08 Interface (Hardware Hookup) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

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 AN1462 - APPLICATION NOTE

M616Z08 BUS ARCHITECTURE

Figure 1 and Table 1 show the control, address, and data pins of the M616Z08.

Figure 1. M616Z08 Logic Diagram

VCC

13 16
A0-A12 DQ0-DQ15

WE0
M616Z08
WE1

CE

OE

VSS
AI04213

Table 1. M616Z08 Signal Names

A0-A12 Address Inputs

DQ0-DQ15 Data Input/Output

CE Chip Enable

OE Output Enable

WE0 WRITE Enable DQ 0-7

WE1 WRITE Enable DQ 8-15

VCC Supply Voltage

VSS Ground

READ Mode
The M616Z08 is in the READ Mode whenever WRITE Enable (WE0 or WE1) is High with Output Enable
(OE) Low, and the Chip Enable (CE) is asserted. This provides access to data from sixteen of the 131,072
locations (bits) in the static memory array, specified by the 13 address inputs. Valid data will be available
at the sixteen output pins within 20ns after the last stable address, providing OE is Low and CE is Low.

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AN1462 - APPLICATION NOTE

WRITE Mode
The M616Z08 is in the WRITE Mode whenever the WE0 (low memory addresses) or WE1 (high memory
addresses) and the CE pin are low. Either the Chip Enable input (CE) or the WRITE Enable input (WE0
or WE1) must be de-asserted during address transitions for subsequent WRITE cycles. WRITE begins
with the concurrence of Chip Enable being active with WE0 or WE1 low. The WRITE cycle can be termi-
nated by the earlier rising edge of CE, or WE0/WE1. If the Output is enabled (CE = Low and OE = Low),
then WE0 or WE1 will return the outputs to high impedance within 10ns of its falling edge. Care must be
taken to avoid bus contention in this type of operation. Data input must be valid for 10ns before the rising
edge of WRITE Enable, or for 10ns before the rising edge of CE, whichever occurs first, and remain valid
for 0ns.
“Operational” Mode
The M616Z08 has a Chip Enable power down feature which invokes an automatic standby mode when-
ever Chip Enable is de-asserted (CE = High). An Output Enable (OE) signal provides a high speed tri-state
control, allowing fast READ/WRITE cycles to be achieved with the common I/O data bus. Operational
modes are determined by device control inputs WE0 or WE1 and CE as summarized in “Operating Modes”
(below).

Table 2. WE (0,1) States During Access

WRITE Enable Used during 16-bit Port Access
WE0 WRITE Enable for DQ (0-7)
WE1 WRITE Enable for DQ (8-15)

Table 3. Operating Modes

Operation CE OE WE0 WE1 DQ0–DQ7 DQ8–15

Deselect 1 X(1) X(1) X(1) Hi-Z Hi-Z

Word WRITE 0 1 0 0 Hi-Z Hi-Z

Byte 0 WRITE 0 1 0 1 Hi-Z Hi-Z
Byte 1 WRITE 0 1 1 0 Hi-Z Hi-Z
Byte 1 WRITE, Byte 1 READ 0 0 0 1 Hi-Z Data
Byte 1 WRITE, Byte 0 READ 0 0 1 0 Data Hi-Z
Word READ 0 0 1 1 Data Data
DC Characteristics Comparison Table
Table 4 gives a summary of the Input/Output DC Characteristics on the high and low voltage levels and
shows that they are compatible.

Table 4. Input/Output DC Characteristics Comparison

Comment MPC555 M616Z08
MPC555 Low Input from M616Z08 VIL3 0.8V max VOL 0.2V max

MPC555 High Input from M616Z08 VIH3 2.0V min VOH VCC – 0.2V min

M616Z08 Low Input from MPC555 VOL3 0.5V max VIL 0.3 * VCC max

M616Z08 High Input from MPC555 VOH3 2.4V min VIH 0.7 * VCC min

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 AN1462 - APPLICATION NOTE

MPC555 TO M616Z08 CONNECTION

Figure 2 shows a connection scheme for the MPC555 to M616Z08 interface. This scheme creates an
8 Kbit x 32 bit wide data bus using two M616Z08 SRAMs.

Figure 2. MPC555 to M616Z08 Interface (Hardware Hookup)

MPC555/565 M616Z08

Address [12:0]
Address [12:0]
Data [15:0]
Data [15:0] WE#BE#0
WE0#
WE#BE#[3:0] WE#BE#1
WE1#
OE#
OE# CS#[1]
CE#
CS#[3:0]

M616Z08

Address [12:0]
Data [31:16]
WE#BE#2
WE0#
WE#BE#3
WE1#
OE#
CS#[1]
CE#

AI05649

CONCLUSION
The M616Z08 can be connected to the MPC555 in a “glueless” configuration. This SRAM will operate from
2.34 to 3.6V. It is configured as an 8 Kbit x 16 memory. The SRAM has equal cycle and access times of
20ns. It also has a tri-state common I/O and two WRITE Enable pins to allow writing to upper and lower
bytes. It is the responsibility of the software to initialize the memory controller interface of the MPC555
Microcontroller to access the SRAM.

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AN1462 - APPLICATION NOTE

REVISION HISTORY

Table 5. Document Revision History

Date Version Revision Details
August 3, 2002 1.0 First Issue

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 AN1462 - APPLICATION NOTE

If you have any questions or suggestions concerning the matters raised in this document, please send them to
the following electronic mail addresses:
ask.memory@st.com (for general enquiries)

Please remember to include your name, company, location, telephone number and fax number.

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

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