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Branch Instructions

The document describes various branch instructions for ARM processors: 1. B - Unconditional branch that jumps within ±252 to +258 bytes for conditional branches and ±2KBytes for unconditional branches. 2. BL - Branch with link that copies the return address to R14 and jumps within ±4MB. Used to call subroutines. 3. BLX - Performs a branch with link. For ARM9E, it jumps to the address in a register. For other processors, it changes to the ARM instruction set before jumping.

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569 views3 pages

Branch Instructions

The document describes various branch instructions for ARM processors: 1. B - Unconditional branch that jumps within ±252 to +258 bytes for conditional branches and ±2KBytes for unconditional branches. 2. BL - Branch with link that copies the return address to R14 and jumps within ±4MB. Used to call subroutines. 3. BLX - Performs a branch with link. For ARM9E, it jumps to the address in a register. For other processors, it changes to the ARM instruction set before jumping.

Uploaded by

Darshan Iyer N
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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B

Branch to label. Used to jump to a specific program location.

Syntax B{cond} label


The jump distance must be within -252 to +258 bytes for conditional
Description
and 2 KBytes for unconditional branch.
Condition
not modified.
Flags
CMP R1,#10 // compare R10 with #10
BEQ val_ok // jump to label val_ok

Example val_ok:

val_err:
B val_err // jump to itself (loop forever)
BL
Branch with Link. Use to call subroutines.

Syntax BL{cond} label

Description Copy address of next instruction to R14 and jump to label. The jump
distance must be within 4Mb of the current instruction. Note that this
mnemonic is generated as two 16-bit Thumb instructions.

Condition not modified.


Flags

Example BL sub+ROM //Call subroutine at computed address


ADDS R1,#1 //Add 1 to register 1, setting CPSR flags
on the result then call subroutine if the C flag is
clear, wich will be the case
//unless R1 held 0xFFFFFFFF

BLX
Performs a branch with link.

Syntax BLX{cond} Rm
BLX label

CPU ARM9E only

Description BLX{cond} Rm
Copy address of next instruction to R14 and jump to address in Rm.

BLX label
Copy address of next instruction to R14, change to ARM instruction set and
jump to label. The jump distance must be within 4MByte of the current
instruction. Note that this mnemonic is generated as two 16-bit Thumb
instructions.

Condition not modified.


Flags

Example BLX armfunc // call ARM function

LDR R6,=function
BLX R6 // call function

BX
Branch indirect and switch CPU mode (Thumb / ARM) as required.

Syntax BX{cond} Rm

Description Branch to address in Rm. Change to ARM mode if bit 0 of Rm is clear.

Condition Flags not modified.

Example BX R5 // branch indirect to address function

Condition Code
Most ARM instructions and the Thumb Branch instruction include a condition code field.
This field is marked in the CPU instructions with {cond}.A conditional instruction is only
executed on match of the condition flags in the Program Status Register. For example, the
BEQ (B instruction with EQ condition) branches only if the Z flag is set. If the {cond} field is
empty the instruction is always executed.

{cond} Suffix Tested Status Flags Description


EQ Z set equal
NE Z clear not equal
CS/HS C set unsigned higher or same
CC/LO C clear unsigned lower
MI N set negative
PL N clear positive or zero
VS V set overflow
VC V clear no overflow
HI C set and Z clear unsigned higher
LS C clear or Z set unsigned lower or same
GE N equals V signed greater or equal
LT N not equal to V signed less than
GT Z clear AND (N equals V) signed greater than
LE Z set OR (N not equal to V) signed less than or equal
AL (ignored) always (usually omitted)
Examples:

CMP R5,#10 // compare R5 with 10


BHI lab1 // branch to lab1 if value in R5 is higher than 10
:
lab1:
TST R5,#10 // test content of R5 against 10
ADDEQ R6,#40 // add 40 to R6 if R5 contains 10

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