CMOS Technology and Logic Gates

Only 15,432,758 more

mosfets to do...

meta
l ndiff
pdiff
poly

6.884 Spring 2005 2/07/2005 L03 CMOS Technology 1

 Quality of Design

Quality of a hardware design primarily judged by:

Price
Performance
Power and/or Energy
Other important metrics can include:
Operating range
Temperature, voltage, background radiation
Reliability
Mean-time between failures (MTBF)
Form factor
Size, weight
Flexibility
Tolerance to changes in specification

Need to understand implementation technology to understand

tradeoffs among these attributes.

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 System-Level Impacts

Chips do not exist in a vacuum, e.g.,

2/2.5G cell phone contains:
RISC Application Processor (ARM)
Digital Signal Processor
SRAM/DRAM Chips
Flash Memory Chips
Image removed due to copyright restrictions. Analog Chips
E.g. headphone amplifier
Radio Chips
Power Management Subsystem
Passive components
resistors, capacitors and
inductors
Digital IC in Need to consider quality of a design
in context of target system.
Package
E.g., design alternative might
have twice the performance but
require 10x off-chip memory
bandwidth.
[Buss, ISSCC 2002]

6.884 Spring 2005 2/07/2005 L03 CMOS Technology 3

 Digital Technology Generations

Electromechanical Relays
Vacuum Tubes
Bipolar Transistors
CMOS/FET Transistors
~10,000nm gates originally, now down to 90nm in production
scaling will stop somewhere below 30nm (over 100 billion

trans./chip)

Future:
3D CMOS (10 trillion transistors/system?)
Carbon Nanotubes?
Molecular Electronics?

CMOS VLSI is the digital implementation technology of choice for

the foreseeable future (next 10-20 years)
Excellent energy versus delay characteristics
High density of wires and transistors
Monolithic manufacturing of devices and interconnect, cheap!

6.884 Spring 2005 2/07/2005 L03 CMOS Technology 4

 Abstraction Levels in Design

Application

Gap too large to

bridge in one step
but there are exceptions,
e.g. magnetic compass

Physics

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 Hardware Design Abstraction Levels

Application
Algorithm
Unit-Transaction Level (UTL) Model
Guarded Atomic Actions (Bluespec)
Register-Transfer Level (Verilog RTL)
Gates
Circuits Todays

Lecture

Devices
Physics

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 CMOS Fabrication

One chip

[6 wafer of T0 chips, 1.0m, 2 Al layers,

1995]
Starting wafer is pure silicon crystal.
Multiple process steps deposit new materials and etch existing layers
using photolithography (light focused through masks).
Modern logic chips fabricated on 20cm (8) wafers, ~100s
chips/wafer.
Wafer sawed into separate chips after fabrication.
Chips then placed into packages (see packaging lecture later in course)

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 Basic CMOS Fabrication Steps

Growing silicon dioxide to serve as an

insulator between layers deposited on the

surface of the silicon wafer.

Doping the silicon substrate with acceptor

and donor atoms to create p- and n-type

diffusions that form isolating PN junctions

and one plate of the MOS capacitor.

Depositing material on the wafer to

create masks, wires and the other plate

of the MOS capacitor.

Etching deposited materials to create the

appropriate geometric patterns.

Figures by MIT OCW.

Adapted from Maly, W.

Atlas of IC Technologies: An Introduction to VLSI Processes.

(Ignore dimensions in figures)

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 UV Light ETCHING
Photoresist
Photomask

Photoresist

SiO2

SiO2
Develop to remove exposed resist.
Photoresist is spun onto wafer then exposed with UV light
or X-rays through mask (or written with electron beam, no mask).

Performance Note: minimum feature size often

determined by photoresist and etching process.
Photoresist Wet Etching
SiO2
Photoresist

SiO2

Isotropic
Remove Photoresist Mask
Dry Etching
Anisotropic

Photoresist

SiO2

SiO2

6.884 Spring 2005 Figure by MIT OCW. 2/07/2005 L03 CMOS Technology 9
 FET = Field-Effect Transistor

The four terminals of a fet (gate, source, drain and bulk)

connect to conducting surfaces that generate a complicated set
of electric fields in the channel region which depend on the
relative voltages of each terminal.

gate
inversion
Surface of wafer happens here
Source Eh Drain
diffusion diffusion
Ev

bulk
Reverse side of wafer
INVERSION:

A sufficiently strong vertical field CONDUCTION:

will attract enough electrons to the If a channel exists, a horizontal

surface to create a conducting n- field will cause a drift current

type channel between the source from the drain to the source.

and drain.

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 Multiple Levels of Interconnect

IBM photomicrograph (Si has been removed!)

Metal 2

M1/M2 Via

Metal 1
Polysilicon

Mosfet
Diffusion (under polysilicon gate)

Figure by MIT OCW.

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 Design Rules

Exclusion rule
Surround rule Extension
rules

Width
rules

Spacing rules

Design rules are an abstraction of the fabrication process that specify

various geometric constraints on how different masks can be drawn.
Design rules can be absolute measurements (e.g. in nm) or scaled to an
abstract unit, the lambda. Lambda-based designs are scaled to the
appropriate absolute units depending on the manufacturing process
finally used.

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 Lambda-based Design Rules

One lambda ()= one half of the minimum mask dimension.

Typically the length of a transistor channel is 2. Usually all edges
must be on grid, e.g., in the MOSIS scalable rules, all edges must be
on a lambda grid.
2x2
The length of the
3 transistor channel is
1 usually the feature
2
that sets the process
2 technology name
2 2 (e.g., 0.18m has
0.18m transistor
length)

3 3 2
1
1
3
diffusion (active)
2x2 3
poly
metal1
contact

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 Static CMOS Gates

F = (A+B).(C+D)

Figure by MIT OCW.

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 Simplified FET Model

Binary logic values represented by voltages:

High = Supply Voltage, Low = Ground Voltage

Supply Voltage = VDD

S
PFET connects
G S and D when PFET only good
G
D G=low=0V at pulling up

D
NFET connects
G G NFET only good
D and S when
at pulling down
S G=high=VDD
Ground = GND = 0V

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 Generic Static CMOS Gate

VDD

Pullup network,
connects output to
VDD, contains only
PMOS
IN1
VOUT
IN2

INn

Pulldown network,

connects output to

GND,

contains only NMOS

For every set of input logic values, either pullup or pulldown network
makes connection to VDD or GND
If both connected, power rails would be shorted together
If neither connected, output would float (tristate logic)

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 NAND Gate

A (A.B)
(A.B) B
B

When both A and B are high, output is low

When either A or B is low, output is high

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 NOR Gate

B
A
(A+B) (A+B)
B

When both A and B are low, output is high

When either A or B is high, output is low

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 NAND Gate Layout

Parallel PMOS Transistors

P-Diffusion
VDD (in N-well)
(A.B)
B

Poly wire connects (A.B)

PMOS & NMOS gates
Output on
Metal 1-Diffusion Metal-1
Contact
A B N-Diffusion
GND
Series NMOS Transistors
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 Methodical Gate Building

Goal is to create a logic function f(x1, x2, ...)

must be inverting for single level of CMOS logic

Pull up network should connect output to VDD when
f(x1, x2, ...) = 1
Pull down network should connect output to GND
when f(x1, x2, ...) = 1
Because PMOS is conducting with low inputs, useful
to write pullup as function of inverted inputs
p(x1, x2, ...) = f(x1, x2, ...)

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 Pullup is Dual of Pulldown Network

For NAND gate, f=(A.B) For NOR gate, f=(A+B)

Pulldown f = A.B Pulldown f = A+B

Pullup p = f = A.B Pullup p = f = A+B

= A+B
= A.B

(De Morgans Laws)

parallel
switches series
form OR A switches
form
(A.B) AND
B
B (A+B)
series
switches
A form parallel
AND switches
form OR

6.884 Spring 2005 2/07/2005 L03 CMOS Technology 21

 More Complex Example

f = (A+B).C

A
pullup p = (A+B).C

B
= (A+B)+C
(A+B).C = (A.B)+C
C

pulldown f = (A+B).C

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 Transistor R and C

Simple Equivalent RC
G
Model of Transistor

Nearly all transistors in digital CMOS circuits have minimum L

but might use slightly longer L to cut leakage in parts of modern circuits
Can scale transistor R and C parameters by width W
L

Effective R scales linearly with 1/W

~4km NMOS, ~9km PMOS, in 0.25m technology
Gate capacitance scales linearly with W
~2fF/m
Diffusion capacitance scales linearly with W W

sum contributions from perimeter and area, ~2fF/m

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 Transistor Delay

When one gate drives another, all capacitance on the node must be
charged or discharged to change voltage to new state. Delay is
proportional to driving resistance and connected capacitance.

CgateP CgateP

RonP CdrainP RonP CdrainP

01

RonN CdrainN RonN CdrainN

CgateN CgateN

Delay ~ RonN(CdrainN+CdrainP+CgateP+CgateN)

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 Gate Layout Tricks

L
Fold transistor to reduce
perimeter diffusion cap
Long transistors

dont lay out well,

and have a lot of

parasitic diffusion

capacitance

W
W/2

Diffusion
has high Use multiple contacts
resistance to diffusion to reduce
resistance

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 More Layout Tricks

Fold whole stack,

not individual

transistors

Pack series transistors as

close as possible to minimize
diffusion R&C parasitics

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 Even More Complex Gates?

Can build arbitrarily complex logic function into one gate,

e.g.

??
F = (A+B).(C+D).E.G+H.(J+K)

But dont want to:

Usually less total delay using a few

smaller logic gates rather than one large

complex gate
Only want to design and characterize a
small library of gates

Figure by MIT OCW. Whats the best way to implement a

given logic function?

Figure by MIT OCW.

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 Method of Logical Effort

(Sutherland and Sproul)

Figure by MIT OCW.

Easy way to estimate delays in CMOS process.

Indicates correct number of logic stages and transistor sizes.
Based on simple RC approximations.
Useful for back-of-the-envelope circuit design and to give
insight into results of synthesis.

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 Technology Speed Parameter:

Characterize process speed with single delay parameter:

is delay of inverter driving same-sized inverter, with no

parasitics other than gate

~16-20ps for 0.25m process

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 Gate Delay Components

Delay = Logical Effort x Electrical Effort + Parasitic Delay

Cin

Logic Gate Cout

Logical Effort
Complexity of logic function (Invert, NAND, NOR, etc)
Define inverter has logical effort = 1
Depends only on topology not transistor sizing
Electrical Effort
Ratio of output capacitance to input capacitance Cout/Cin
Parasitic Delay
Intrinsic self-loading of gate
Independent of transistor sizes and output load

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 Logical Effort for Simple Gates

Define Logical Effort of Inverter = 1

For other gates, Logical Effort is ratio of logic gates input
cap. to inverters input cap., when gate sized to give same
current drive as inverter

Relative
Transistor 2 2 4
Widths
2 4
2
1 1 1
2

Inverter NAND NOR

Input Cap = 3 units Input Cap = 4 units Input Cap = 5 units
L.E.=1 (definition) L.E.=4/3 L.E.=5/3
6.884 Spring 2005 2/07/2005 L03 CMOS Technology 31
 Electrical Effort

Cin

Logic Gate Cout

Ratio of output load capacitance over input capacitance:

Electrical Effort = Cout/Cin
Usually, transistors have minimum length
Input and output capacitances can be measured in units of
transistor gate widths

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 Parasitic Delay

CgateP Main cause is drain diffusion

capacitances.
These scale with transistor
width so P.D. independent
CdrainP
RonP of transistor sizes.
Useful approximation:

Cgate ~= Cdrain
For inverter:
RonN CdrainN
Parasitic Delay ~= 1.0

CgateN

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 Inverter Chain Delay

For each stage:

Delay = Logical Effort x Electrical Effort + Parasitic Delay
= 1.0 (definition) x 1.0 (in = out) + 1.0 (drain C)
= 2.0 units

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 Optimizing Circuit Paths

Cin

Cout

Path logical effort, G = gi (gi = L.E. stage i)

Path electrical effort, H = Cout/Cin (hi = E.E. stage i)
Parasitic delay, P = pi (pi = P.D. stage i)
Path effort, F = GH
Minimum delay when each of N stages has equal effort
Min. D = NF1/N + P
i.e. gi hi = F1/N

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 Optimal Number of Stages

Cin
Cout
Minimum delay when:
stage effort = logical effort x electrical effort ~= 3.4-3.8

Some derivations have e = 2.718.. as best stage effort this ignores

parasitics
Broad optimum, stage efforts of 2.4-6.0 within 15-20% of minimum

Fan-out-of-four (FO4) is convenient design size (~5 )

FO4 delay: Delay of

inverter driving four

copies of itself

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 Using Logical Effort in Design

For given function, pick candidate gate topology

Determine optimal stage effort
equal for all stages
Starting at last gate
output load is known
logical effort is known (from gate topology)
calculate transistor size to give required stage effort
gives output load for preceding stage
lather, rinse, repeat...
Can modify stage efforts up or down to reduce area, power,
or to fit fixed set of library cells
optimal sizing has broad optimum
In 6.884, well just let synthesis tool handle gate sizing, but
its useful to know why the tool makes certain decisions.

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