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Asynchronous Up Counter (Verilog)

This document describes asynchronous up and down counter modules in Verilog. The up counter module increments its internal register tmp by 1 on each clock pulse unless a clear signal is asserted, in which case tmp is set to 0. The down counter module decrements tmp by 1 on each clock pulse unless cleared, where it is set to the maximum value. Both modules assign their output Q to track the internal tmp register.

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2K views1 page

Asynchronous Up Counter (Verilog)

This document describes asynchronous up and down counter modules in Verilog. The up counter module increments its internal register tmp by 1 on each clock pulse unless a clear signal is asserted, in which case tmp is set to 0. The down counter module decrements tmp by 1 on each clock pulse unless cleared, where it is set to the maximum value. Both modules assign their output Q to track the internal tmp register.

Uploaded by

sindhura
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ASYNCHRONOUS UP COUNTER(Verilog):

module counter (C, CLR, Q);


input C, CLR;
output [3:0] Q;
reg [3:0] tmp;

always @(posedge C or posedge CLR)


begin
if (CLR)
tmp = 4'b0000;
else
tmp = tmp + 1'b1;
end
assign Q = tmp;
endmodule

ASYNCHRONOUS DOWN COUNTER(Verilog):


module counter (C, CLR, Q);
input C, CLR;
output [3:0] Q;
reg [3:0] tmp;

always @(posedge C or posedge CLR)


begin
if (CLR)
tmp = 4'b1111;
else
tmp = tmp - 1'b1;
end
assign Q = tmp;
endmodule

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