26th IEEE VLSI Test Symposium

On the Detectability of Scan Chain Internal Faults An Industrial Case Study*

F. Yang1, S. Chakravarty2, N. Devta-Prasanna2, S.M. Reddy1 and I. Pomeranz3
1. University of Iowa, Iowa City, Iowa City, IA
2. LSI Corporation, Milpitas, CA
3. Purdue University, West Lafayette, IN

ABSTRACT The goal of our work is to investigate the use of standard

Scan chains contain approximately 50% of the logic scan cells and existing methods of generation and application
transistors in large industrial designs. Yet, faults in the scan of scan based tests to detect scan cell internal faults. In this
cells are not directly targeted by scan tests and assumed paper we present results of the first step in this direction. The
detected by flush tests. Reported results of targeting the scan main contributions of the work presented are:
cell internal faults using checking sequences show such tests (1) Defining the notion of half-speed flush test and
to be about 4.5 times longer than scan stuck-at test sets and demonstrating that half-speed flush tests increase
require a sequential test generator, even for full scan circuits. coverage of internal faults in scan cells,
We present the first step in developing an alternative test (2) Demonstrating that existing test generation and test
methodology for scan cell internal faults. Fault detection application methods together with the half-speed flush
capability of existing tests (flush tests, stuck-at tests and test cover cell internal faults to similar degree as the
transition delay fault tests) are quantified. Existing tests are checking sequence based tests,
shown to have similar coverage as checking sequences. A new Showing that IDDQ testing of 90nm and beyond designs
flush test, viz. half-speed flush test, is defined. This new test is may not be feasible for a significant portion of the faults
shown to add 2.3% and 8.8% to the stuck-at and stuck-on fault leaves coverage holes which, in addition to the issue of quality
coverage, respectively. of shipped products, could result in a serious reliability risk.
We will quantify the above using a 90nm commercial
I. INTRODUCTION product which consists of approximately 4.3 million cells and
Scan [1, 2] is universally used to cost effectively generate 54 million transistors.
and apply tests and aid defect diagnosis for large designs. As The remainder of the paper is organized as follows. In
discussed in Section II, in a large industrial design nearly 44% Section 2 we discuss related earlier works on the detection of
of the transistors in the logic part of the design reside within scan cell internal faults [5-10]. In Section 3 we describe the
scan cells. Thus, it is important to determine the coverage of scan cell used in the study, the faults targeted and the tests
faults internal to scan cells and if necessary investigate cost simulated. In Section 4, we present the HSPICE simulation
effective methods to augment tests generated by standard results on scan cell internal faults and discuss the conclusions
automatic test pattern generation (ATPG) procedures to from the simulation results. Section 5 concludes the paper.
improve coverage of scan cell internal faults. In this paper we
report the results of a case study on an industrial design. We II. PRELIMINARIES
report fault coverage using standard test patterns and flush In Table 1 we give the gate and transistor counts of an
tests. The study exposes test coverage holes that need to be industrial design. Combinational gate, latch and scan flip-flop
addressed. We also propose a new flush test called half-speed counts in the design are shown in the second row, and the
flush test that closes some of the coverage holes. third row shows the number of transistors residing in each
It has been noted that many faults internal to latches and type of cells. From the table, it can be noted that about 14.4%
flip-flops may not be detected [3-11] by standard scan based of the total number of cells are scan cells but they contain
tests. Makar and McCluskey proposed generation of checking 43.6% transistors of the logic part of the design.
sequences based tests [6-9] to detect scan cell internal faults. Existing ATPG tools model scan flip-flops as black boxes
Generation of these tests requires use of sequential ATPG as shown in Figure 1(a) and generate tests for faults at inputs
procedures. The average size of the resulting tests, for ISCAS and outputs of the scan flip-flop. Thus faults in the circuit
circuits, is 4.5 times the size of a single stuck-at test set [8], [9] elements internal to the scan cells are not directly targeted.
which is a barrier to its use in practice. Earlier works, for example [3-10], showed that tests for stuck-
Noting that some of the transistor stuck-on faults cannot be at faults (SAFs) at flip-flop inputs and output miss many
detected by voltage based tests, a testable design of latches internal faults.
was proposed by Aissi and Olaniyan [11]. Use of this design Internal Faults On is an option often found in commercial
increases the area of scan cells and requires two additional ATPG tools. If this option is used, the tool uses an ATPG
primary inputs to control internal nodes of scan. library model to include faults at internal nodes in complex
gates and flip-flops. This command may lead to the generation
_______________________________________ of additional tests in the case of some complex gates. If the
Internal Faults On command is used for the scan cell shown
*Work of Fan Yang and S.M. Reddy was supported in part by SRC Grant in Figure 1(a) the ATPG library model for the scan flip-flop
No. 2004-TJ-1583 and the work of I. Pomeranz was supported in part by used will be the one shown in Figure 1(b). However, if tests
SRC Grant No. 2004-TJ-1244.

1093-0167/08 $25.00 2008 IEEE 79

DOI 10.1109/VTS.2008.13
are generated for stuck-at faults (SAFs) and transition delay SAF and 5 additional SONs are detected, thus making SAF
faults (TDFs) using Internal Faults On command the same coverage 100% and SON coverage 88.5%.
patterns as those generated using the gate level model of
Figure 1(a) are obtained.
Tests called flush tests are used to test for faults in the scan
chains. Typically used tests are 000, 111, and
0011000110. The flush tests are scanned in and out of the
scan chains with scan enable active (TE = 1) throughout the
application of flush tests.
Table 1: Gate and transistor data of an industrial design
Comb. Gate Latch Scan flip-flop
3678245 3256 614159
# of Cells
(85.6%) (0.08%) (14.3%)
# of 30634354 53588 23670019
Transistors (56.4%) (0.1%) (43.5%)
33174648 19536 27022996 Figure 2: Scan cell used in [8].
# of SAFs
(55.1%) (0.03%) (44.9%)
III. BACKGROUND ON THE CASE STUDY

3.1 SCAN CELL STUDIED

The scan cell used in the design described in Table 1 is a
positive edge triggered Muxed input D flip-flop (MD flip-
flop). There are many MD flip-flop implementations. Figure 3
shows the flip-flop implementation we studied. The circuit in
the dashed rectangle is the multiplexer used for selecting
between data_in (D) and scan_in (TI). Circuit between nodes
Din and MD is the master stage of the flip-flop. The slave
Figure 1: Gate Level and ATPG library models for a Scan stage is the circuit between nodes MD and output (Q).
cell
In the simulations we report, we use only the ATPG tests
obtained using the gate level model of scan cells and the flush
test 0011000110 to determine coverage of scan cell internal
faults. We implicitly use the other flush tests to determine
what we refer to as probabilistically detected faults.

2.1 PRIOR WORK

In order to cover scan cell internal faults checking sequence
based tests were proposed in [6-9]. The advantage of these
tests is that tests can be generated using a black box model of
a scan cell by assuming how the inputs to a scan cell are
allowed to change. These assumptions allow developing a
flow table for the scan cells for which checking sequences to
verify all allowed state transitions can be derived. A
sequential ATPG can then be used to generate circuit level test
sequences to apply the checking sequences to all scan cells
and scan out test responses. Results reported in [9] show that
for ISCAS circuits the number of tests increases by 4.5X
relative to the standard scan test sets. A sequential ATPG is
required even for full-scan circuits. The complexity of the
sequential test generation process restricts its use to small Figure 3: Scan Flip-flop Implementation Studied with N19
circuits. Stuck-at-1
Applying checking sequences based tests to muxed-input
scan cell shown in Figure 2, the following fault coverage was 3.2 FAULTS AND TESTS CONSIDERED
obtained in [8]: 31 out of a total of 32 (96.9%) SAFs and 18 In this case study, we consider SAFs and SONs within the
out of a total of 26 (69.2%) stuck-on faults (SONs) are MD flip-flop. For a SAF, the faulty node directly connects to
detected without using IDDQ. With IDDQ testing, one more power (Vdd) for stuck-at-1 or to ground (Vss) for stuck-at-0.

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A SON fault always turns on the faulty transistor. There are For example, Figure 4 shows line CP1 stuck-at-0 (highlighted
22 nodes and 34 transistors in the scan cell. Thus, 44 SAFs by arrows on the fan-out branches of CP1). This fault makes
and 34 SONs are considered in our study. Note that when transistors MP02 and MP07 to be always on and transistors
counting nodes, we have not considered fan-out branches. For MN03 and MN06 to be always off. We refer to Figure 4 and
example, although node N4 has two branches we consider Figure 5 in the following discussion of this fault.
only two stuck-at faults. N4 stuck-at-0 makes transistors
MP08 stuck-on and MN08 stuck-off. This is different from the
gates of MP08 and MN08 stuck-at-0 independently.
Scan cell boundary SAF tests are test patterns generated by
existing ATPG targeting SAFs on scan cell inputs and outputs
considering the scan cell as a black box. Table 2 shows the
boundary SAF list and the corresponding values in test
patterns generated by an ATPG for MD flip-flop input D and
output Q.
Table 2: Boundary SAF list and tests of scan flip-flop
Stuck-at Fault Test Pattern
D stuck-at-0 D = 1, TE = 0, TI = X, Q = 1
D stuck-at-1 D = 0, TE = 0, TI = X, Q = 0
Q stuck-at-0 D = 1, TE = 0, TI = X, Q = 1
Q stuck-at-1 D = 0, TE = 0, TI= X, Q = 0

3.3 PROBABILISTIC DETECTION OF FAULTS

Probabilistically detected faults are faults that are not
proved to be detected but have a high probability of detection.
Consider node N19 stuck-at-1 highlighted by an arrow in
Figure 3. The detection condition for this fault is D = 0, TE =
1, TI = 1, Q = 1. Since TE = 1, it cannot be detected by a scan
cell boundary SAF test. Assume that initially the scan chain Figure 4: Fault CP1 stuck-at-0
has random bits and the length of the scan chain is L.
Consider the case when the flush test 0011000110 is
applied to the scan chain. Data input D, which is driven by the
combinational logic, can be either 0 or 1. If we assume that D
= 0 or D = 1 with equal probability, then the probability that
N19 stuck-at-1 is not detected by the flush test is (4/5)L. When
the flush test of all ones is applied, the probability that the
fault is not detected, under the same assumptions on D, is
(1/2)L. In typical industrial designs L can be about 1000. Thus
the fault can be assumed to have been detected by the flush
test. In this work we say that the fault is assumed
probabilistically detected. We perform such probability
analyses to identify faults which can be classified as
probabilistically detected.

3.4 HALF-SPEED FLUSH TEST

Scan input TI (cf. Figure 3) of a single flip-flop in a scan
chain gets its value from the output of the previous flip-flop
Figure 5: Detection of the fault CP1 stuck-at-0
which changes value at shift clock rising edge. There is a path
delay between the two stages. Thus TI can change value either To detect CP1 stuck-at-0 fault, we can first set Q to 0 in
within the half cycle where CP = 1 if the path delay is less clock cycle i by setting TI to 0 when CP = 0. After that we set
than half shift clock period or the half cycle where CP = 0 TI to 1 in clock cycle i+1 when CP = 1. In the fault-free
when the path delay is greater than half of the shift clock circuit, this change of TI in shift clock cycle i+1 will not
period. In the fault-free circuit a new value can propagate to propagate to Q, since MP02 and MN02 are turned off when
the output of a flip-flop only when it arrives within CP = 0. CP = 1. However, in the faulty circuit, this change in TI,
However, we found that detection of some cell internal faults during clock cycle i+1, will propagate to Q in clock cycle i+1,
require that scan input TI change when CP = 1. To detect such since MP02 is on due to the fault and MP06 is on since CP = 1.
faults we define a new type of test called half-speed flush test. This is shown in Figure 5(a), where solid lines are signals

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from fault-free circuit and dashed lines show faulty
waveforms. By a similar argument, as shown in Figure 5(b),
we note that if instead of changing TI when CP = 1 in clock
cycle i+1 we change TI when CP = 0, then the fault will not
be detected.
Detection of faults by changing TI when CP = 1 poses a
problem. During test application we will not be able to change
TI directly, but indirectly through the output of the previous
flip-flop in the scan chain. We next discuss a method to
accomplish this.

Figure 7: Detection of CP1 stuck-at-0 with S = T

Figure 6: Logic diagram of a scan chain with length 3

In Figure 6 three MD flip-flops are cascaded to form a
segment of a scan chain. Assume the fault discussed above
occurs in the second scan flip-flop of Figure 6. TI1 gets its
value from the previous scan flip-flop output (Q0) in the scan
chain. There is a path delay between Q0 and TI1. Assume that
the shift mode of the scan chain has been closed during timing
closure for f mega hertz (i.e. the maximum delay between Q0
and TI1 is T = 1/f). Then the propagation delay (d) from Q0 to
TI1 lies between 0 and T. Let us assume that the shift clock Figure 8: Detection of CP1 stuck-at-0 with S = 2T
period is S. Q0 = 00110 (a segment of flush test), is produced In [8], the authors discussed slow speed application of the
at the shift clock rising edge. Therefore, TI1 changes within checking sequences. The motivation for that was to detect
CP = 1 if d is smaller than S/2. As discussed previously, if the additional SOPs. In [8], the above mechanism of detecting
path delay results in TI1 transition within CP = 1, then this such scan cell internal faults using flush tests was not
fault can be detected by the flush test. Whereas the fault considered. Furthermore, the frequency for the test we are
cannot be detected if d is greater than S/2, causing TI1 to proposing is related to the timing closure frequency of the
change within CP = 0. Figure 7 shows the waveforms when scan chains of the design.
the shift cycle time S = T. The path delay between Q0 and TI1
is greater than S/2 causing TI1 to transition within CP = 0. By IV. SIMULATION RESULTS
observing outputs of scan flip-flops Q1 and Q2, as discussed We first describe the HSPICE based simulation we did. In
above, the fault is not detected. But, we can expand the clock our simulation we used the segment of a scan chain shown in
until TI1 transitions within the half cycle with CP = 1. This Figure 6. A target fault is injected into the second scan cell by
can be accomplished by slowing down the scan shift speed modifying its circuit description.
during the application of the flush test 00110. Figure 8 shows As we described in Section 3.4 the timing of TI1,
that the fault is detected by applying the flush test with scan depending on the path delay between Q0 and TI1, is not
shift cycle period S = 2T. The dashed lines show faulty controllable. To simulate the effect of the flush test 00110
waveforms and the solid lines are fault-free waveforms. our simulation uses the stimulus sequence 001100110 applied
Starting from rising edge R3, faulty value (00110/11100) of at TI1. As shown in Figure 9, the first 5 bits 00110 change
Q2 is generated. This flush test with shift clock period S no within CP = 0 emulating the path delay between Q0 and TI1
less than 2T detects the fault with path delay both greater and greater than half shift clock period. The last 5 bits 00110
smaller than T/2. S = 2T is preferred in order to maximize the change within CP = 1 emulating the effect of path delay less
flush test shifting speed. than half shift clock period. The output Q2 of the third scan
This motivated our definition of half-speed flush test. flip-flop is observed at the clock rising edge to determine fault
Assume that we have timing closure of scan chain at detection. If a fault is detected by both the first 5 bits and the
frequency f, then the shift speed for half-speed flush test will last 5 bits, we deduce normal speed flush test will detect the
be at frequency f/2 or less. For example, if timing is closed at fault. If a fault is only detected by the last 5 bits, the flush test
10MHz (200 MHz) half-speed flush test runs at 5 MHz (100 can only detect the fault if the path delay is less than half the
MHz) or less. Note that we only slow down the flush test shift clock period. Half-speed flush test is needed since it
00110... guarantees the path delay to be squeezed within half shift

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clock period. The method described above to simulate the Table 3: Simulation Summary
flush test 00110 allows us to determine detection of a fault
either by applying the flush test at normal shift frequency or at Normal 1/2 Bound. Prob IDDQ
half-speed in one simulation run. flush speed SAF Det. /Undet
34 1 5 4 0
SAF
77.3% 2.3% 11.3% 9.1% 0%
11 3 1 3 16
SON
32.4% 8.8% 2.9% 8.8% 47.1%

4.1 STUCK-AT FAULTS

To simulate SAFs, we connect the faulty node to Vdd
(stuck-at-1) or to Vss (stuck-at-0). From Table 3 we observe
Figure 9: Waveform of applied comprehensive flush test that 34 (77.3%) out of 44 SAFs are detected by flush test, and
another 1 (2.3%) fault is detected only by the half-speed flush
For simulating the scan cell boundary SAF tests we use the
test. Third column shows that boundary SAF tests detect 5
tests shown in Table 2 and observe output Q1 of the second
(11.3%) additional SAFs that are not detected by the two flush
scan cell.
tests. Four faults (9.1%), N19 stuck-at-1, N20 stuck-at-1, TE
Figure 10 shows the waveforms from the stimulus sequence
stuck-at-1and TE stuck-at-0, are probabilistically detected.
simulation for the fault CP1 stuck-at-0 discussed in Section
We compare this result with D flip-flop results from [8].
3.4. The dashed lines are faulty waveforms and solid lines are
Out of a total of 24 SAFs one fault was not detected by the
waveforms from fault-free circuit. From the waveform of Q2,
checking experiments and required IDDQ testing. In our case,
we note that the fault is detected at the seventh clock rising
all SAFs are detected without IDDQ, assuming that the
edge. This implies that only half-speed flush test will detect
probabilistically detected faults are indeed detected. Given the
this fault.
uncertainty of using IDDQ for future technologies, removal of
this dependency on IDDQ tests is a significant step forward.
Half-speed flush test also increases SAF coverage by 2.3%
for a cell and by 1.03% for the full-chip using the data for the
industrial design in Table 1. Given that todays designs
attempt to achieve over 99% coverage this increase is quite
significant.

4.2 STUCK-ON FAULTS

A SON fault is modeled by connecting the gate of a faulty
nMOS transistor to Vdd and the gate of a faulty pMOS
transistor to Vss. There are a total of 34 SONs. From Table 3
we note that the flush test detects 11 (32.4%) and another 3
(8.8%) SONs are covered by half-speed flush test. Scan cell
boundary SAF tests detect 1 (2.9%) additional fault. The
faults MN01B, MP01A and MN01E stuck-on faults are
probabilistically detected. The remaining 16 (47.1%) SONs
Figure 10: Flush test simulation for CP1 stuck-at-0 are not detected by Boolean tests. However, 12 (35.3%) of
Table 3 summarizes the simulation results. The number of these faults can be detected by IDDQ testing if such
faults detected by normal speed flush test, with the measurements are feasible.
corresponding percentage is shown in column 2. The Comparing with the results from [8], 4 out of a total 20
additional number of faults detected by half-speed flush test is SONs in the D flip-flop considered in [8] were not detected by
shown in column 3. It is important to note that even though the checking experiment based tests. If we restrict ourselves to
we do not explicitly show this in Table 3 all faults detected by the two latches of the MD flip-flop used in our design, we get
the flush test 00110... applied at normal shift frequency are the same coverage as [8] but without using the long checking
also detected by the half-speed flush test. Thus one only needs sequences. Once again note the importance of the half-speed
to apply the flush test at half-speed to detect all the faults flush test. It added about 8.8% SON coverage per cell.
reported detected by the flush test. Column 4 shows the
number of faults not detected by flush test and detected by 4.3 GAPS IDENTIFIED
scan cell boundary SAF tests. Fifth column shows the number We have seen that by adding a simple half-speed flush test
of probabilistically detected faults. The last column gives the we can increase coverage of SAF and SON by 2.3% and 8.8%
total number of undetected and IDDQ only detectable faults. for a cell. In full chip, it increases SAF and SON coverage by
The second row is the results for SAFs. Results for SONs are 1.03% and 3.83%. However, we note that fault coverage gaps
presented in the row 3, respectively. In the next few sections still exist. They are identified below.
we discuss each of these rows in details.

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A. IDDQ detection B. Probabilistic detection
By simulating a scan cell using HSPICE we determined We performed probabilistic analysis using simple
that for all the IDDQ only detectable faults, the IDDQ through assumptions and found that 9.1% and 8.8% of SAF and SON
the transistor affected by a fault is within 1A when the fault of the cell faults are probabilistically detected. Translated
is not present and the IDDQ is in the range of 47.71A to using the data from Table 1, this implies full-chip coverage of
365A in the presence of the fault. For the 90nm product 4.08% SAF and 3.83% of SON faults. Considering desired
under study the faulty IDDQ is less than 0.005% of the SAF target coverage in the high nineties this is very large. It is
nominal total chip IDDQ. Hence, we believe that full chip therefore important to determine what percentage of the
IDDQ based measurements will not detect such defects. probabilistically detected faults is actually detected.
We note that many of the defects that require IDDQ testing Additional tests may be required to cover any coverage gaps
will be activated during the functional mode of operation. found.
Consider the example in Figure 11 where MN01C SON is
highlighted by a dashed circle. For MN01C SON the test V. CONCLUSIONS
condition is D = 0, TE = 0, TI = 1, Q = 0. A Vdd to Vss path The detection of scan flip-flop internal faults is important
is formed in the multiplexer. IDDQ for fault-free circuit as it may result in functional failure. Nearly 50% of the SAFs
remains as low as 1A, whereas it is 47.8A for this faulty reside in the scan chains and are currently not directly targeted
circuit. Note that this condition will be satisfied during the for test generation. The earlier proposed method of using
functional mode of operation. Whenever this condition is checking experiment [8] to detect these faults is not practical
satisfied MP01A and MP01B sink about 47 times more because of its large size and the difficulty of deriving the tests.
current. This current surge is a major reliability issue for these An analysis of SAFs and SONs in a MD flip-flop using flush
transistors. tests and boundary stuck-at tests was presented in this paper.
Using the data in Table 1, we estimate that the percentage We proposed a new flush test called half-speed flush test and
of IDDQ only detectable SONs is approximately 35.3% of the showed that it improves fault coverage by a couple of
transistors in the logic. This poses a potential reliability risk if percentage. We also identified that a large proportion of faults
not addressed. are probabilistically detected. It is important to verify with
An alternative to detecting such defects could be low product data if these faults are actually detected by the ATPG
voltage testing. For the fault in Figure 11, we performed a and flush tests. We showed that there is also a large class of
simulation and the results are given in Table 4. In order to IDDQ only detectable faults that poses a serious reliability
detect the fault, the supply voltage was progressively lowered. risk. Given these gaps, we believe, alternative tests to detect
Note that only when the supply voltage was reduced by more these faults are required.
than 50% the output showed a faulty value. However,
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