SNS COLLEGE OF TECHNOLOGY

(An Autonomous Institution)

Approved by AICTE and Affiliated to Anna University
Accredited By NBA-AICTE & NAAC with A Grade
Sathy Main Road (NH 407), VazhiyampalayamPirivu, Coimbatore-35

Department of Electronics and Communication

Engineering

EC212 LINEAR INTEGRATED CIRCUITS LAB

PRACTICAL OBSERVATION

Name _______________
Reg. No. _______________
Class _______________
Semester _______________
 SNS COLLEGE OF TECHNOLOGY
(An Autonomous Institution)
Approved by AICTE and Affiliated to Anna University
Accredited By NBA-AICTE & NAAC with A Grade
Sathy Main Road (NH 407), VazhiyampalayamPirivu, Coimbatore-35

LABORATORY POLICIES AND REPORT FORMAT

Lab reports should be submitted on Record Note Book. Your report is

a professional presentation of your work in the lab. Neatness, organization and
completeness will be rewarded. Marks will be deducted for any part that is not
clear.
LEFT SIDE RIGHT SIDE
PIN DIAGRAM AIM
CIRCUIT DIAGRAM APPARATUS REQUIRED
DESIGN PROCEDURE
TABULATION INFERENCE
RESULT

Your work must be original and prepared independently. However, if you

need any guidance or have any questions or problems, please do not hesitate to
approach your staff in charge during lab hours/office hours. The students should
follow the dress code in the Lab session.
Reports Due Dates: Reports should be submitted on or before the following
lab session. A late lab report will result in 10 mark deduction for being one day
late. If a report is 3 days late, mark of 0 will be assigned.

STUDENTS MUST
Be in time to the laboratory utilize the time effectively.
Carry the observations and record with them by updating their pre lab and post
Lab experiments.
Sit only in their assigned work counters.
Keep the lab clean.
 INDEX

Sl. Page
Date Experiment Name Mark Signature
NO. No.

Inverting, Non inverting and differential

1
amplifiers.

2 Integrator and Differentiator.

3 Instrumentation amplifier

Active low pass, high pass and band pass

4
filters.
Astable & Monostable multivibrators
5
and Schmitt Trigger using op-amp.
Phase shift and Wien bridge oscillators
6
using op-amp.
Astable and monostable multivibrators
7
using NE555 Timer.
PLL characteristics and its use as
8
Frequency Multiplier.
DC power supply using LM317 and
9
LM723.

10 Study of SMPS.

11 Simulation Experiments

ADDITIONAL EXPERIMENTS

12 Summing amplifier using IC741

13 Log-Antilog amplifier

Average
EXP.No:1
DESIGN AND TESTING OF INVERTING, NON-INVERTING AND

DATE: DIFFERENTIAL AMPLIFIERS USING OP-AMP

AIM:

To design an Inverting, Non-inverting and differential amplifiers using Operational

amplifier and test its performance.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. Operational Amplifier IC 741 1

2. Dual Power supply 12Volts 1

2 MHz
3. Function Generator 2

4. Resistors

5. DSO 70 MHz 1

6. Multimeter 1

7. Connecting Wires - As required

8. Bread Board - 1

9. Probes - As required

THEORY:

Inverting Amplifier

The input signal Vin is applied to the inverting terminal of op amp through Rin and
non-inverting terminal of op-amp is grounded. The output signal is fed back to the inverting
terminal (- sign in op amp) through the Rf of an op amp. Amplifier which produces output with
180 phase shift is known as Inverting amplifier.
PIN DIAGRAM FOR IC 741:

CIRCUIT DIAGRAM:

A) Inverting amplifier

B) Non-Inverting amplifier
Non Inverting Amplifier
The input signal Vin is applied to the Non inverting terminal of op-amp and
inverting terminal of op-amp is grounded. Amplifier which produces output without any phase
shift is known as Non-Inverting amplifier.

Differential Amplifier

Differential amplifier amplifies the difference between two input signals. Phase of
the output is same as that of input.

DESIGN:

A) Inverting Amplifier

Gain= Vo/Vin = - Rf/ Rin

Rf = ; Rin =
Gain- Rf/ Rin =
Gain =
Vo = Gain* Vin

B) Non Inverting Amplifier

Gain = Vo / Vin = 1 + Rf/ Rin;

Rf = ; Rin =

Gain =

Vo = Gain* Vin

C) Differential amplifier

Vout=Rf/R1(V2-V1)

Gain= Vo/(V2-V1)=Rf/R1

Rf= ; R1=

Gain Rf/R1=

Vo=Gain* Vin
C) Differential Amplifier

MODEL GRAPH:

A) Inverting Amplifier

B) Non Inverting amplifier

PROCEDURE:

Inverting Amplifier

1. Connections are given as per the circuit diagram.

2. Input is given to inverting terminal (Pin No 2) through Rin from function generator.

3. Non Inverting terminal (Pin No 3) is grounded.

4. Output will be obtained from Pin No 6 and it is displayed in DSO.

5. Note down the readings from DSO.

6. Plot the waveform on the graph.

PROCEDURE:

Non-Inverting Amplifier

1. Connections are given as per the circuit diagram.

2. Input is given to Non-inverting terminal (Pin No 3) from function generator.

3. Inverting terminal (Pin No 2) is grounded.

4. Output will be obtained from Pin No 6 and it is displayed in DSO.

5. Note down the readings from DSO.

6. Plot the waveform on the graph.

PROCEDURE:

Differential Amplifier

1. Connections are given as per the circuit diagram.

2. Input is given to both inverting (Pin No 2) and Non- inverting (Pin No 3) terminals from
function generators.
3. Output will be obtained from Pin No 6 and it is displayed in DSO.

4. Note down the readings from DSO.

5. Plot the waveform on the graph

 C)Differential amplifier

TABULATION

A) Inverting Amplifier.

Input Voltage(Vin) Output Voltage(Vout) Time Period Frequency(Hz)

(V) (V) (ms)

B) Non Inverting Amplifier.

Input Voltage(Vin) Output Voltage(Vout) Time Period Frequency(Hz)

(V) (V) (ms)

C) Differential Amplifier

Input Input Output Time Frequency(Hz)

Voltage(V1) Voltage(V2) Voltage(vout) Period
(mV) (mV) (mV) (ms)
RESULT:

Thus the Inverting, Non-inverting and Differential amplifier using Operational amplifier
were designed and tested.
EXP.No: 2
DESIGN AND TESTING OF INTEGRATOR & DIFFERENTIATOR USING

DATE: OP-AMP.

AIM:

To design Integrator and Differentiator using operational amplifier and test its
performance.

APPARATUS REQUIRED:

S.No COMPONENTS RANGE QUANTITY

1. Op-amp IC 741 1

2. Power supply 12 V 1
2MHz
3. Function Generator 1

4. Resistors

5. Capacitors

6 DSO 70 MHz 1

7 Probes -- As required

8 Bread Board -- 1

9 Connecting Wires -- As required

THEORY:

DIFFERENTIATOR

The circuit that performs mathematical operation of differentiation is known as

differentiator or differentiating amplifier. The output waveform is the derivative of input
waveform.
PIN DIAGRAM FOR IC 741:

CIRCUIT DIAGRAM :

DIFFERENTIATOR

MODEL GRAPH:

DIFFERENTIATOR
SQUARE WAVE INPUT

Input

Output
DESIGN:

DIFFERENTIATOR
C1= ; C2= ; fa=

1. [ ]=

2. Rf =

3. R1 =

THEORY:

INTEGRATOR

The circuit that performs mathematical operation of integration is known as integrator or

integrating amplifier. The output waveform is integration of input waveform. This circuit is
obtained by changing the resistor and capacitor of the differentiator.

DESIGN:
INTEGRATOR
1. fa (lower frequency limit for integration) = 1/ 2Rf Cf

fa = ; Cf = ; Rf =

NOTE : 1 For 99% accuracy input frequency should be at least 10 times fa.

2. Upper frequency limit fb=1/2R1Cf

fb = ; Cf = ; R1 =

When input frequency is increased output amplitude reduces as gain falls at 6dB/octaves

 SINE WAVE INPUT

Input

Output

CIRCUIT DIAGRAM :

INTEGRATOR

MODEL GRAPH:

INTEGRATOR
OBSERVATION

DIFFERENTIATOR

For sine wave input:

Peak to peak amplitude of the input = volts.
Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz
For square wave input:
Peak to peak amplitude of the input = volts.
Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz

INTEGRATOR

For sine wave input:

Peak to peak amplitude of the input = volts.

Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz

For square wave input:

Peak to peak amplitude of the input = volts.

Frequency of the input = Hz
Peak to peak amplitude of the output = volts.
Frequency of the output = Hz
PROCEDURE:

1. Connections are given as per the circuit diagram.

2. Input is given to inverting terminal (Pin No 2) through Rin from function generator.

3. Non Inverting terminal (Pin No 3) is grounded.

4. Output will be obtained from Pin No 6 and it is displayed in DSO.

5. Note down the readings from DSO.

6. Plot the waveform on the graph.

RESULT:

Thus the Differentiator and Integrator using operational amplifier were designed and
tested.
EXP.No: 3
DESIGN AND TESTING OF INSTRUMENTATION AMPLIFIER USING
DATE: OP-AMP.

AIM:

To design Instrumentation amplifier using operational amplifier and test its performance.

APPARATUS REQUIRED:

S.No COMPONENTS RANGE QUANTITY

1. Operational Amplifier A 741 3

2. Dual Power supply 12 Volts 1

2 MHz
3. Function Generator 2
6.2K 2
4. Resistors 24 K 4
51 1
5. DSO 70 MHz 1

6. Multimeter _ 1

7. Bread Board _ 1

Connecting Wires,
8. _ As required
Probe

THEORY:

Instrumentation amplifier is an amplifier that realizes high input impedance and very low
offset and drift voltage values. This configuration is better than inverting or non-inverting
amplifier because it has minimum non-linearity, stable voltage gain and high CMRR (> 100 dB).
This type of amplifier is used at output side of thermocouples, strain gauges and biomedical
probes.
PIN DIAGRAM FOR IC 741:

CIRCUIT DIAGRAM:
DESIGN:

FOR GAIN=250

(V1 - V2)

R2 = R1=24K

R = 6.2 K; R = 51

[ ] 250

TABULATION:

S. No V1 V2
PROCEDURE:

(i) Connections are given as per the circuit diagram.

(ii) Limitation: Keep input voltage difference from 10mv to 50mv because the output
voltage should not exceed saturation voltage.(Vsat = +24V)
(iii) For various input voltage V1 and V2 measure and record the output voltage and
tabulate.

RESULT

Thus the instrumentation amplifier is designed, constructed and tested successfully.

EXP.No: 4
DESIGN AND CONSTRUCT ACTIVE LOWPASS, HIGHPASS AND
BANDPASS FILTERS USING OPERATIONAL AMPLIFIER
DATE:

AIM:

To design, construct and test the frequency responses of Low Pass Filter, High Pass
Filter and Band Pass Filter using operational amplifier.

APPARATUS REQUIRED:

S.NO COMPONENTS RANGE QUANTITY

1. Operational Amplifier IC A 741 3
2. Dual Power supply 12 Volts 1
3. Function Generator 2 MHz 1

4. Resistors

5. Capacitor
6. DSO 70 MHz 1
7. Bread Board - 1
8. Probe - 2
9. Connecting Wires As required
THEORY :

LOW PASS FILTER:

A low-pass filter is a filter that passes low-frequency signals and attenuates (reduces the
amplitude of) signals with frequencies higher than the cut-off frequency. The actual amount of
attenuation for each frequency varies depending on specific filter design. It is sometimes called a
high-cut filter, or treble cut filter in audio applications. A low-pass filter is the opposite of a
high-pass filter.
Low-pass filters (LPF) exist in many different forms, including electronic circuits, anti-
aliasing filters for conditioning signals prior to analog-to-digital conversion, digital filters for
smoothing sets of data, acoustic barriers, blurring of images, and so on. The moving average
operation used in fields such as finance is a particular kind of low-pass filter, and can be
analyzed with the same signal processing techniques as are used for other low-pass filters. Low-
pass filters provide a smoother form of a signal, removing the short-term fluctuations, and
leaving the longer-term trend.
PIN DIAGRAM FOR IC 741:

CRCUIT DIAGRAM:

LOW PASS FILTER

MODAL GRAPH:

LOW PASS FILTER

A LPF allows only low frequency signals up to a certain break-point fH to pass through, while
suppressing high frequency components. The range of frequency from 0 to higher cut off
frequency fH is called pass band and the range of frequencies beyond fH is called stop band.

DESIGN:

LOW PASS FILTER

The following steps are used for the design of active LPF.

1. The value of high cut off frequency fH is chosen.

2. The value of capacitor C is selected such that its value is 1F.
3. By knowing the values of fH and C, the value of R can be calculated using
1
f
H 2RC
4. Finally the values of R1 and Rf are selected depending on the designed pass band
R
f
gain by using A 1
R1

Design of First order LPF:-

Given frequency,
fH =
C=
R= 1/(2 fHC) =
R=
R
f
A 1
R1

So, Rf =R1

PROCEDURE:

LOW PASS FILTER

1. Connections are given as per the circuit diagram.

2. Input signal is connected to the circuit from the signal generator.
3. The input and output signals of the filter are connected to channel 1 and 2 of the DSO.
4. Suitable voltage sensitivity and time-base have selected on DSO.
5. Input voltage is kept as some constant value.
6. By varying the frequency, output voltage is measured by using DSO.
TABULATION :

LOW PASS FILTER:

Vin=1V

Output voltage
S.No Frequency (Hz) Gain=Vo/Vin Gain=20log(Vo/Vin)
Vo (mV)
(dB)
THEORY:

SECOND ORDER HIGH-PASS FILTER:

A high-pass filter (HPF) is an electronic filter that passes high-frequency signals but
attenuates (reduces the amplitude of) signals with frequencies lower than the cutoff frequency.
The actual amount of attenuation for each frequency varies from filter to filter. High-pass filters
have many uses, such as blocking DC from circuitry sensitive to non-zero average voltages or
RF devices. They can also be used in conjunction with a low-pass filter to make a band pass
filter
The high pass filter is the complement of the low pass filter. Thus the high pass filter can
be obtained by interchanging R and C in the circuit of low pass configuration. A high pass filter
allows only frequencies above a certain bread point to pass through and at terminates the low
frequency components. The range of frequencies beyond its lower cut off frequency f L is called
stop band.

An improved filter response can be obtained by using a second order active filter. A
second order filter consists of two RC pairs and has a roll-off rate of -40dB/decade.

DESIGN:

The following steps are used for the design of active HPF.
1. The value of low cut off frequency fL is chosen.
2. The value of capacitor C is selected such that its value is 1F.
3. By knowing the values of fL and C, the value of R can be calculated using
1
f
L 2RC

Second order High Pass Filter:-

Given fL =
C=
fL=1/2RC; Let R1=R2=R; C1 = C2=C
R=1/2 fL C =
Rf =R=

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Input signal is connected to the circuit from the signal generator.
3. The input and output signals of the filter are connected to channel 1 and 2 of the DSO.
4. Suitable voltage sensitivity and time-base on DSO is selected.
5. Input voltage is kept as some constant value.
6. By varying the frequency, output voltage is measured by using DSO.
CIRCUIT DIAGRAM:

SECOND ORDER HIGH-PASS FILTER:

MODEL GRAPH:

SECOND ORDER HIGH-PASS FILTER:

THEORY:

BAND-PASS FILTER:

A band-pass filter is a device that passes frequencies within a certain range and rejects
(attenuates) frequencies outside that range. The BPF is the combination of high and low pass
filters and this allows a specified range of frequencies to pass through. It has two stop bands in
range of frequencies between 0 to fL and beyond fH. The band between fL and fH is called pass
band. Hence its bandwidth is (fH-fL). This filter has a maximum gain at the resonant frequency
(fr) which is defined as

fr fH fL
The figure of merit (or) quality factor Q is given by

fr f
Q r
f H f L BW
DESIGN:

fL = fH =

fr fH fL =

fr f
Q r
f H f L BW

Q=
TABULATION:

SECOND ORDER HIGH-PASS FILTER:

Vin=1V
S.No Frequency (Hz) Output voltage Gain=Vo/Vin Gain=20log(Vo/Vin)
Vo (mV) (dB)

CIRCUIT DIAGRAM:

BAND-PASS FILTER:
MODEL GRAPH:

BAND-PASS FILTER:

TABULATION:-

BAND-PASS FILTER:
Vin=1V
Output voltage Gain=20log(Vo/Vin)
S.No Frequency (Hz) Vo (mV)
Gain=Vo/Vin
(dB)
PROCEDURE:

BAND-PASS FILTER

1. Connections are given as per the circuit diagram.

2. Input signal is connected to the circuit from the signal generator.
3. The input and output signals of the filter are connected to channel 1 and 2 of the DSO.
4. Suitable voltage sensitivity and time-base on DSO is selected.
5. Input voltage is kept as some constant value.
6. By varying the frequency, output voltage is measured by using DSO.

RESULT:

Thus the Low pass filter, High pass filter and Band pass filters were designed using
Op-amp and its cut off frequency was determined.
EXP.No: 5
DESIGN AND TESTING OF ASTABLE, MONOSTABLE MULTIVIBRATORS

DATE: AND SCHMITT TRIGGER CIRCUITS USING OP-AMP

AIM:
To design an Astable, Monostable Multivibrators & Schmitt Trigger using Op-amp and
plot its waveform.

APPARATUS REQUIRED:

S.NO COMPONENT RANGE QUANTITY

1. Op-amp IC A 741 1

2. Dual Power Supply 12Volts 1

3. DSO 70MHz 1

4. Function Generator 2MHz 1

4. Resistors

5. Capacitors
6. Diode 1N4007 2
7. Probes As Required
8. Bread Board _ 1
9. Connecting Wires _ As Required

THEORY:
Astable Multivibrator:
A multivibrator is an electronic circuit used to implement a variety of simple two-
state systems such as oscillators, timers and flip-flops. It is characterized by two amplifying
devices (transistors, electron tubes or other devices) cross coupled by resistors or capacitors. The
name "multivibrator" was initially applied to the free-running oscillator version of the circuit
because its output waveform was rich in harmonics. In Astable multivibrator the circuit is not
stable in either state. It continually switches from one state to the other. It functions as a
relaxation oscillator
PIN DIAGRAM FOR IC 741:

CIRCUIT DIAGRAM:
ASTABLE MULTIVIBRATOR:

MODEL GRAPH:

ASTABLE MULTIVIBRATOR:
DESIGN:
Astable Multivibrator:

Vc(t) = vf + (v i- vf) e-t/RC

Vf = + Vsat & Vi= -Vsat
Now
Vc(t) = vsat- vsat (1+ ) e-t/RC
At t = T1
Vc(t)=vsat - vsat (1+ ) e e-t/RC
T1 = RC ln(1+/1-)
T = 2 T1
T = 2RC ln(1+/1-)
Vcc=12V ;Vsat = 0.9 Vcc = 12*0.9 = 10.8V

R1= ; R2= ; R= ; C=
= R2/(R1+R2) =
T=
fo =1\2RC=
Vo(p-p) = Vsat =

PROCEDURE:

Astable Multivibrator:
1. Make the connections as shown in the circuit diagram
2. Keep the DSO channel switch in ground and adjust the horizontal line on the x axis so
that it coincides with the central line.
3. Select the suitable voltage sensitivity and time base on the DSO
4. Check for the correct polarity of the supply voltage to op-amp and switch on power
supply to the circuit.
5. Observe the waveform at the output and across the capacitor. Measure the frequency of
oscillation and the amplitude. Compare with the designed value.
6. Plot the Waveform on the graph.
CIRCUIT DIAGRAM:

MONOSTABLE MULTIVIBRATOR

MODEL GRAPH:
MONOSTABLE MULTIVIBRATOR
THEORY:

MONOSTABLE MULTIVIBRATOR:
A Monostable Multivibrator (MMV) has one stable state and one quasi-stable
state. The circuit remains in its stable state till an external triggering pulse causes a transition to
the quasi -stable state. The circuit comes back to its stable state after a time period T. Thus it
generates a single output pulse in response to an input pulse and is referred to as a one-shot or
single shot. An external trigger signal generated due to charging and discharging of the
capacitor produces the transition to the original stable state. So, mono stable multi vibrator is
one which generates a single pulse of specified duration in response to each external trigger
signal.

DESIGN:
MONOSTABLE MULTIVIBRATOR:

V0=vf + (v i- vf) e-t/RC

Vf = -Vsat & Vi = VD (diode forward voltage)
Vc= -Vsat + (VD+Vsat) e-t/RC
/At t=T
Vc = - Vsat
- Vsat = -Vsat+ (VD+Vsat) e-t/RC

T=RC ln( )

If Vsat>>VD & R1=R2

R1= ; R2= ; R= ; C=
Vcc=12V ;Vsat = 0.9Vcc = 10.8V
=R2/(R1+R2) = 0.5
T=0.69RC= 0.69ms

PROCEDURE:
MONOSTABLE MULTIVIBRATOR:
1. Make the connections as shown in circuit diagram.
2. A trigger pulse is given through differentiator circuit through pin No.3
3. Observe the pulse waveform at pin No.6 using DSO and note down the time period.
4. Plot the waveform on the graph.
CIRCUIT DIAGRAM:
Schmitt Trigger

MODEL GRAPH:

Schmitt Trigger
TABULATION:

ASTABLE MULTIVIBRATOR
i Output voltage of Square wave
ii Time period of Square wave

iii Voltage across capacitor

iv Time period for charging & discharging of

capacitor

MONOSTABLE MULTIVIBRATOR
Amplitude of input trigger pulse
i

Time period of trigger pulse

ii

Output voltage of square wave

iii

Time period of square wave

iv

SCHMITT TRIGGER
i Saturation voltage (Vsat)

ii Output voltage (V0)

iii Upper threshold voltage (VUT)

iv Lower threshold voltage (VLT)

THEORY- Schmitt Trigger:
In electronics, a Schmitt trigger is a comparator circuit with hysteresis, implemented by
applying positive feedback to the non-inverting input of a comparator or differential amplifier. It
is an active circuit which converts an analog input signal to a digital output signal. The circuit is
named a "trigger" because the output retains its value until the input changes sufficiently to
trigger a change. In the non-inverting configuration, when the input is higher than a certain
chosen threshold, the output is high. When the input is below a different (lower) chosen
threshold, the output is low, and when the input is between the two levels, the output retains its
value. This dual threshold action is called hysteresis and implies that the Schmitt trigger
possesses memory and can act as a bistable circuit (latch or flip-flop). There is a close relation
between the two kinds of circuits: a Schmitt trigger can be converted into a latch and a latch can
be converted into a Schmitt trigger.
DESIGN-Schmitt Trigger:
VCC = 12 V; VSAT = 0.9 VCC; R1= ; R2 =
VUT = + [VSAT R2] / [R1+R2] =
VLT = - [VSAT R2] / [R1+R2] =
HYSTERSIS [H] = VUT - VLT =

PROCEDURE-Schmitt Trigger:
1 Connect the circuit as shown in the diagram.
2 Set the input voltage as 1 V(p-p) at 1KHz. (Input should be always less than Vcc)
3 Note down the output voltage at DSO
4 To observe the phase difference between the input and the output, set the DSO in dual
Mode and switch the trigger source in DSO to CHI.
5 Plot the input and output waveforms on the graph.

RESULT:
Thus the Astable, Monostable Multivibrators and Schmitt trigger circuit were designed
and implemented using IC741 Operational Amplifier.
 EXP.No: 6
DESIGN AND TESTING OF PHASE SHIFT AND WIEN BRIDGE
OSCILLATORS USING OP-AMP.
DATE:

AIM:
To design the following sine wave oscillators
a) RC Phase shift oscillator with the frequency of Hz.
b) Wien Bridge Oscillator with the frequency of KHz.

APPARATUS REQUIRED:

S.No COMPONENTS RANGE QUANTITY

1. Operational Amplifier IC A 741 1

2. Dual Power supply 12 Volts 1

3. Resistors

4. Capacitors

5. DSO 70MHz 1
6. Probe -- As required
7. Bread Board -- 1
8. Connecting Wires -- As required

THEORY:

PHASE SHIFT OSCILLATOR

A phase-shift oscillator is a linear electronic oscillator circuit that produces a sine wave
output. It consists of an inverting amplifier element such as a transistor or op amp with its
output fed back to its input through a phase-shift network consisting of resistors and
capacitors. The feedback network 'shifts' the phase of the amplifier output by 180 degrees at
the oscillation frequency to give positive feedback. Phase-shift oscillators are often used at
audio frequency as audio oscillators.
The filter produces a phase shift that increases with frequency. It must have a maximum
phase shift of more than 180 degrees at high frequencies so the phase shift at the desired
oscillation frequency can be 180 degrees. The most common phase-shift network cascades
three identical resistor-capacitor stages that produce a phase shift of zero at low frequencies
and 270 at high frequencies
PIN DIAGRAM FOR IC 741:

CIRCUIT DIAGRAM :

PHASE SHIFT OSCILLATOR

MODEL GRAPH :

PHASE SHIFT OSCILLATOR

DESIGN:

PHASE SHIFT OSCILLATOR

C=

R=

Rf 29R

Rf = 29 * = = [Standard Value]

PROCEDURE:

PHASE SHIFT OSCILLATOR

1. Connect the components as shown in the circuit

2. Switch on the power supply and DSO.
3. Note down the output voltage at DSO.
4. Plot the output waveform on the graph.
5. Redesign the circuit to generate the sine wave of frequency 2KHz.
6. Compare the output with the theoretical value of oscillation
THEORY:

WIEN BRIDGE OSCILLATOR

A Wien bridge oscillator is a type of electronic oscillator that generates sine waves. It
can generate a large range of frequencies. The bridge comprises four resistors and two
capacitors. The oscillator can also be viewed as a positive gain amplifier combined with a
bandpass filter that provides positive feedback.

DESIGN:

WIEN BRIDGE OSCILLATOR

C=

R= ; R1 =

R2 = 2R1= = [Standard Value]

CIRCUIT DIAGRAM :

WIEN BRIDGE OSCILLATOR

MODEL GRAPH:

WIEN BRIDGE OSCILLATOR

OBSERVATION

PHASE SHIFT OSCILLATOR

i Peak to peak amplitude of the output Volts.

ii Frequency of oscillation Hz.

WIEN BRIDGE OSCILLATOR

Volts.
i Peak to peak amplitude of the output

KHz
ii Frequency of oscillation
PROCEDURE:

WIEN BRIDGE OSCILLATOR

1. Connect the circuits as shown in the circuit

2. Switch on the power supply.
3. Note down the output voltage on the DSO.
4. Plot the output waveforms on the graph.
5. Redesign the circuit to generate the sine wave of 1 KHz.
6. Plot the output waveform on the graph.
7. Compare the practical value of the frequency with the theoretical value.

RESULT:

Thus the RC Phase shift oscillator and Wien bridge oscillator were designed using
Operational Amplifier and tested.
EXP.No: 7
DESIGN AND TESTING OF ASTABLE AND MONOSTABLE
DATE: MULTIVIBERATORS USING IC 555 TIMER.

AIM:
To design and test an Astable and Monostable Multivibrators using IC555 timer.
APPARATUS REQUIRED:

S.NO COMPONENT RANGE QUANTITY

1. IC 555 NE555 1

2. Power supply +5 V 1

3. Resistors 4.7K,10K,1K Each1

4. Capacitors 0.01F,0.1F Each 2

5. DSO 70MHz 1

6. Connecting Wires, Probes As required

7. Bread Board _ 1

THEORY:
ASTABLE MULTIVIBRATOR
Fig shows the 555 timer connected as an Astable Multivibrator. Initially, when the output
is high, capacitor [C] starts charging towards Vcc through R1 and R2. As soon as the capacitor
voltage equals 2/3 Vcc upper comparator (UC) triggers the flip flop and the output switches low.
Now capacitor C starts discharging through R2 and transistor Q1.
When the voltage across C equals 1/3 Vcc lower comparator (LC), output triggers the flip-
flop and the output go high. Then the cycle repeats.
The capacitor is periodically charged and discharged between 2/3 Vcc and 1/3 Vcc
respectively. The time during which the capacitor charges form 1/3 Vcc to 2/3 Vcc is equal to the
time the output is high and is given by
Tc = 0.69(R1+R2) C (1)
Where R1 and R2 are in Ohms and C is in farads. Similarly the time during which the
capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by
Td = 0.69 R2 C (2)
The total period of the output waveform is
T = T c + T d = 0.69 (R1 + 2R2) C (3)
The frequency of oscillation, fo = 1 / T =1.45 / (R1+2R2)C (4)
PIN DIAGRAM FOR IC 555:

IC NE555 INTERNAL PIN DIAGRAM:

DESIGN:
ASTABLE MULTIVIBRATOR

; If R1 = R2 then =0.5 and T =2RC ln 3

2Vsat = VO (p-p)
C1=C2=C
PROCEDURE:

ASTABLE MULTIVIBRATOR
1. Rig-up the circuit of 555 Astable Multivibrators as shown in fig with the designed value
of components.
2. Connect the DSO probes to pin 3 and 2 to display the output signal and the voltage across
the timing capacitor. Set suitable voltage sensitively and time-base on the DSO.
3. Switch on the power supply to DSO and the circuit.
4. Observe the waveforms on the DSO and draw to scale on a graph sheet. Measure the
voltage levels at which the capacitor starts charging and discharging, output high and low
timings and frequency.

THEORY:

MONOSTABLE MULTIVIBRATOR
Monostable Multivibrator has one stable state and other is a quasi-stable state. The circuit
is useful for generating single output pulse at adjustable time duration in response to a triggering
signal. The width of the output pulse depends only on external components, resistor and a
capacitor.
The stable state is the output low and quasi stable state is the output high. In the stable
state transistor Q1 is on and capacitor C is shorted out to ground. However upon application of
a negative trigger pulse to pin2, Q1 is turned off which releases the short circuit across the
external capacitor C and drives the output high. The capacitor C now starts charging up towards
Vcc through RA. However when the voltage across C equal 2/3 Vcc the upper comparator output
switches form low to high which in turn drives the output to its low state via the output of the flip
flop. At the same time the output of the flip flop turns Q1 on and hence C rapidly discharges
CIRCUIT DIAGRAM:
ASTABLE MULTIVIBRATOR
R1=1k; R2=4.7k; C1=0.01F; C2=0.01F

=5V

MODEL GRAPH
ASTABLE MULTIVIBRATOR

Tc-Capacitor charging time(ms) ; Td-Capacitor discharging time(ms)

CIRCUIT DIAGRAM:

MONOSTABLE MULTIVIBRATOR

MODEL GRAPH

MONOSTABLE MULTIVIBRATOR

TABULATION:

Time period Time period

Capacitor Output (ms)
Ton Toff
Voltage (Vc) Voltage( V0)
(ms) (ms)
Astable
Monostable
Through the transistor. The output remains low until a trigger is again applied. Then the cycle
repeats.

The pulse width of the trigger input must be smaller than the expected pulse width of the
output. The trigger pulse must be of negative going signal with amplitude larger than 1/3 Vcc.
The width of the output pulse is given by,
T = 1.1 RAC
DESIGN:
MONOSTABLE MULTIVIBRATOR
T = 1.1 RAC
For T=1ms;
RA= T/1.1 C = (std value).

PROCEDURE:
MONOSTABLE MULTIVIBRATOR
1. Make the connections as shown in circuit diagram.
2. A trigger pulse is given through pin no.2
3. Observe the pulse output waveform at pin no.3 and capacitor output at Vc point using
DSO and note down the time period.
4. Plot the waveform on the graph.

RESULT:

Thus the Astable and Monostable Multivibrators using IC555 timer were designed and
tested.
 EXP.No: 8
PLL CHARACTERISTICS AND ITS USE AS
FREQUENCY MULTIPLIER.
DATE:

AIM:
To construct and study the operation of frequency multiplier using IC 565.

APPARATUS REQUIRED:

S.No COMPONENTS RANGE QUANTITY

1 IC 565,IC 7490,2N2222 - 1
2 Resistors 20 K, 2k, 1
3 Capacitors 0.001 F
4.7k,10k 1 each

10 F

4 Function Generator (Digital) 1 Hz 2 MHz 1

5 C.R.O - 1
6 Dual Power Supply 0- 30 V 1

THEORY:

In a frequency multiplier using PLL 565, a divided by N network is inserted between the VCO
output and the phase comparator input. Since the output of the comparator is locked to the input
frequency fin the VCO is running at a multiple of the input frequency. Therefore in the locked state
the VCO output frequency is given by,

f0 = Nfin
PIN DIAGRAM FOR IC 565:

CIRCUIT DIAGRAM :

+6v

20kohm
RT C
10Mf
2kohm
0.001Mf

C1
10 8
2 7 Fo=5fin
VCO Output
4
565
vin
3 +6v
5
1 9 1 RT
11 4.7kohm
7490
(%5) 1
2

0.01Mf 2 3 6 7 10
1
10kohm
2N2222
RT
3

-6v
PROCEDURE:
1. The connections are given as per the circuit diagram.
2. The circuit uses a 4- bit binary counter 7490 used as a divide-by-5 circuit.
3. Measure the free running frequency of VCO at pin 4, with the input signal Vi set equal to
zero. Compare it with the calculated value = 0.25 / (RT CT).
4. Now apply the input signal of 1 VPP square wave at 500 Hz to pin 2.
5. Vary the VCO frequency by adjusting the 20k potentiometer till the PLL is
locked.Measure the output frequency.It should be 5 times the input frequency.
6. Repeat steps 4, 5 for input frequency of 1 kHz and 1.5 kHz.

RESULT:

Thus the characteristics and operation of frequency multiplier using IC 565.tested.

EXP.No:9(A)
DC POWER SUPPLY USING LM 317
DATE:

AIM:

To construct a DC power supply using LM317 and test its line and load regulation.

APPARATUS REQUIRED:

S .No COMPONENTS RANGE SPECIFICATION QUANTITY

1 Diodes 1N4007 1000v,1A 6

1000uF 25V,Electrolytic
2 Capacitors Each 1
470uF 35V,Electrolytic
220 W
3 Resistors Each 1
15K W
Pot(Variable
4 10K - 1
Resistor)
5 Rheostat (0-175) 1.5Amps 1

6 Transformer 24V 2A 1

7 IC IC 317 LM317 1

8 Multimeter - - 3

9 Connecting Wires - - As Required

10 Bread Board - - 1

THEORY:

It is ideal to adjust voltage from 1.25V to 30V and currents up to 1A.

The LM317 or LM117 series of adjustable 3-terminal positive voltage regulators is

capable of supplying in excess of 1.5A over a 1.2V to 37V output range,
FRONT VIEW OF LM 317:

LM317 VOLTAGE REGULATOR:

It has special features like:

Output Voltage Tolerance 1%

Line Regulation 0.01%
Load Regulation 0.3%
Short-circuit protection.
Maximum input voltage 40V

CIRCUIT OPERATION:

1. Transformer T1 step down AC 220V to AC 24V.

2. The bridge diode rectifier D1 (1N4007) to D4 (1N4007) converts it into dc voltage.
3. The filter capacitor C1 filter the ripple and output equal to DC35V
4. The capacitor C3 is used for better performance filter of IC1.
5. The output voltage from IC1 depends on the Voltage Adj pin of the IC or value of VR1 (adjust).
6. VR1 control output dc voltage 0V (1.25V) to 30V (32V) or 37V maximum voltage at 1.5 Amax.
7. The diode D5 and D6 (both is 1N4007) is used for protection of IC from reverse voltage.

CALCULATION OF THE LM317 OUTPUT VOLTAGE:

we can calculate output voltage equal to:

Vout = 1.25 x {1+ (Rp/R1)
Vref = 1.25V
Typically R1 is 220 ohms
VR1=10K
R2=15K
Rp = {(VR1 x R2) / (VR1 + R2)}
When VR1is in minimum position (0) Rp = 0 ohms.
Vout = 1.25 x {1+ (0/220)}
= 1.25V
But when VR1 is in maximum resist (10K),
Rp = {(VR1 x R2) / (VR1 + R2)}
Rp = 6K.
Vout = 1.25 x {1+ (6000/220)}
= 35.3V
CIRCUIT DIAGRAM:

MODEL GRAPH:

V0 Line regulation V0 Load regulation

Vin IL
TABULATION:

Line regulation:

% line regulation=[Change in output voltage/Change in input voltage]*100

Vin = IL =
Line Regulation
S.No
Input Voltage(VR1) Load Voltage(VL)

Load regulation:
%load regulation=[Change in Output Voltage/Change in Output Current]*100
Vin = VR1 =
Load Regulation
S.No
Output Current(IL) Load Voltage(VL)
PROCEDURE:

1. Connections are given as per the circuit diagram.

2. Check out the DC voltage in rectifier circuit.
3. Then change the input voltage (VR1) by using variable resistor, kept output current constant
take down the input and output voltages for line regulation.

4. Now kept input voltage (VR1) as a constant. Change the output voltage and output current
take down the readings for Load regulation.
5. Plot the waveforms for both line and load regulation.

RESULT:

Thus we have constructed DC power supply using LM317 and line and load regulation
was obtained.
EXP.No:9(B)
DC POWER SUPPLY USING IC 723
DATE:
AIM :
To design low voltage regulator using LM 723 and test its line and load regulation.
COMPONENTS REQUIRED:

S .No COMPONENTS RANGE SPECIFICATION QUANTITY

1 Diodes 1N4007 1000v,1A 4

2 Capacitors 25V,Electrolytic 1
1000F
430 W
3 Resistors 1K W Each 1
1 w
4 Pot(Variable Resistor) 47K - 1
(0-175) 1.5Amps
5 Rheostat Each1
(0-40) 5Amps
6 Transformer 24V 2A 1

7 Transistors TIP122,2N3055 - Each1

7 IC IC 723 LM723 1

8 Multimeter - - 3

9 Connecting Wires - - As Required

10 Bread Board - - 1

Specifications of IC 723:
Power dissipation : 1W
Input Voltage : 9.5 to 40V
Output Voltage : 2 to 37V
Output Current : 150mA for Vin-Vo = 3V
10mA for Vin-Vo = 38V
Load regulation : 0.6% Vo
Line regulation : 0.5% Vo
LM 723 PIN DIAGRAM:

LM 723 INTERNAL DIAGRAM:

PIN DIAGRAM-TIP122 TRANSISTOR:

PIN DIAGRAM-2N3055 TRANSISTOR:

DESIGN:
Output voltage VO
Reference voltage Vref
Rsc Minimum Resistance to protect the output from short circuit.

LOW VOLTAGE REGULATOR:

Given: Vo=5V, Vref = 7.15 V

To calculate R1, R2 ,R3 and Rsc.

Vo = Vref ( R2 / ( R1 + R2 ) )
5 / 7.15 = ( R2 / ( R1 + R2 ) )
( R1 + R2 ) 0.699 = R2
0.699R1 = 0.301 R2 , R1 = 0.4306 R2
Select R2 = 1 K
R1 = 1 K * 0.4306 = 430
R1 = 430

R3 = R1 * R2 / ( R1 + R2) , R3 = 430.6 *1000 /(430.6+1000 )

R3 = 300
Rsc = Vsense / Ilimit = 0.5 /1A = 0.5 , Rsc = 0.5
CIRCUIT DIAGRAM:

BRIDGE RECTIFIER CIRCUIT

LOW VOLTAGE REGULATOR

Fig. 1.1
PROCEDURE :

LOW VOLTAGE REGULATOR

Line Regulation:

1. Give the circuit connection as per the circuit diagram shown in Fig 1.1.
2. Set the load Resistance to give load current of 1mA.
3. Vary the input voltage from 7V to 18V and note down the corresponding output voltages.

Load Regulation:

1. Set the input voltage to 10V.

2. Vary the load resistance in note down the corresponding output voltage and load current.

Lab Report:

1. Plot the line regulation by taking Input Voltage (Vin) along X-axis and Output Voltage
(VL) along Y-axis for the load current.

2. Plot the load regulation by taking load current (IL) along X-axis and Output Voltage (VL)
along Y-axis for the input voltage.

3. Calculate its % Voltage Regulation using the formula.

TABULATION:

LOW VOLTAGE REGULATOR:

Line Regulation: Line Regulation:

Constant Load current IL = Constant Voltage VR1=

Input Voltage Vin =

Output Voltage Output

S.No Input Voltage Output Voltage
S.No Vo(mV) Current
VR1(mV) VL(mV)
IL(mA)
MODEL GRAPH:

Line Regulation : Load Regulation :

Input Voltage Vs Output Voltage : Output Current Vs Output Voltage

V0 Line regulation V0 Load regulation

Vin IL
RESULT:

Thus the line and load regulation of low voltage dc regulated power supply was designed
using LM 723 and tested.
EXP.No:10
STUDY OF SMPS
DATE:

INTRODUCTION

D.C. to D.C. converters and D.C. to A.C. Converters belong to the category of Switched
Mode Power Supplies (SMPS). The various types of voltage regulators, used in Linear Power
Supplies (LPS), fall in the category of dissipative regulator, as they have a voltage control element
usually transistor or zener diode which dissipates power equal to the voltage difference between an
unregulated input voltage and a fixed supply voltage multiplied by the current flowing through it.
The switching regulator acts as a continuously variable power converter and hence its efficiency is
negligibly affected by the voltage difference. Hence the switching regulator is also known as non -
dissipative regulator. In a SMPS, the active device that provides regulation is always operated in
cut-off or in saturation mode.

Block diagram of SMPS

 Here, the primary power received from AC main is rectified and filtered as high voltage
DC. It is then switched at a huge rate of speed approximately 15 kHz to 50 kHz and fed to the
primary side of the step-down transformer. The step-down transformer is only a fraction of the
size of a comparable 50 Hz unit thus reliving the size and weight problems. The output at the
secondary side of the transformer is rectified and filtered. Then it is sent to the output of the
power supply. A sample of this output is sent back to the switch to control the output voltage.

SMPS rely on PWM to control the average value of the output voltage. The average value
of the repetitive pulse waveform depends on the area under the waveform. As load increases,
output voltage tends to fall. Most switching power supplies regulate their output using the
method called Pulse Width Modulation (PWM). The power switch which feeds the primary of
the step-down transformer is driven by the PWM oscillator. When the duty cycle is at 50%, then
the maximum amount of energy will be passed through the step-down transformer. As the duty
cycle decreases the power transmitted is less hence low power dissipation.

The Pulse Width signal given to the switch is inversely proportional to the output voltage.
The width or the ON time of the oscillator is controlled by the voltage feedback from the
secondary of the rectifier output and forms a closed loop regulator. Since switching regulator is
complex, modern IC packages like Motorola MC 3420/3520 or Silicon General SG 1524 can be
used instead of discrete components.

RESULT:

Thus functioning of SMPS is studied.

EXP.No:11
SIMULATION OF
i. INVERTING, NON INVERTING AND DIFFERENTIAL AMPLIFIERS.
ii. Integrator and Differentiator.
iii. Instrumentation amplifier
iv. Active low pass, high pass and band pass filters.
v. Astable & Monostable multivibrators and Schmitt Trigger using op-amp.
DATE:
vi. Phase shift and Wien bridge oscillators using op-amp.
vii. Astable and monostable multivibrators using NE555 Timer.

AIM:

To simulate opamp and 555 applications using Spice.

TOOLS REQUIRED:

Simulation tool: MULTISIM

PROCEDURE:

Start the simulation by clicking the capture menu.

Click the file option in the main page to create a new project, name the project ,
Select analog or mixed A/D.
Create a blank project and press ok.
The schematic window will be opened to draw the circuit with the help of
pallets.
Open new simulation window and create a simulation profile.
The simulation setting window will be opened to give required datas for the
Output waveforms.
Select run to run the program.
Click Add wave to view the result waveform.
Go to view and select output file to view the net list of the simulation.
INVERTING AMPLIFIER CIRCUIT DIAGRAM:

INVERTING AMPLIFIER OUTPUT WAVEFORM:

NON INVERTING AMPLIFIER CIRCUIT DIAGRAM:

NON INVERTING AMPLIFIER OUTPUT WAVEFORM:

DIFFERENTIAL AMPLIFIER CIRCUIT DIAGRAM:

DIFFERENTIAL AMPLIFIER OUTPUT WAVEFORM:

INTEGRATOR CIRCUIT DIAGRAM:

INTEGRATOR OUTPUT WAVEFORM:

DIFFERENTIRATOR CIRCUIT DIAGRAM:

DIFFERENTIRATOR OUTPUT WAVEFORM:

ASTABLE CIRCUIT DIAGRAM:

ASTABLE OUTPUT WAVEFORM:

MONOSTABLE CIRCUIT DIAGRAM:

MONOSTABLE OUTPUT WAVEFORM:

SCHMITTRIGGER CIRCUIT DIAGRAM:

SCHMITTRIGGER OUTPUT WAVEFORM:

HPF CIRCUIT DIAGRAM:

HPF OUTPUT WAVEFORM:

LPF CIRCUIT DIAGRAM:

LPF OUTPUT WAVEFORM:

BPF CIRCUIT DIAGRAM:

BPF OUTPUT WAVEFORM:

INSTRUMENTATION AMPLIFIER CIRCUIT DIAGRAM:

INSTRUMENTATION AMPLIFIER OUTPUT WAVEFORM:

WIEN BRIDGE OSCILLATOR CIRCUIT DIAGRAM:

WIEN BRIDGE OSCILLATOR OUTPUT WAVEFORM:

RC PHASE SHIFT OSCILLATOR CIRCUIT DIAGRAM:

RC PHASE SHIFT OSCILLATOR OUTPUT WAVEFORM:

MONOSTABLE USING IC555 CIRCUIT DIAGRAM:

MONOSTABLE USING IC555 OUTPUT WAVEFORM:

ASTABLE USING IC555 CIRCUIT DIAGRAM:

ASTABLE USING IC555 OUTPUT WAVEFORM:

RESULT:
 EXP.No:12
SUMMING AMPLIFIER USING OPAMP
DATE:

AIM:
To simulate the summing amplifier and verify it virtually

SOFTWARE REQUIRED:
MULTISIM

THEORY:

The summing amplifier is used to add the input signal applied to the inverting or non inverting
terminals there are two types of summing amplifier they are i)Inverting summing amplifier and non
inverting summing amplifier

i)Inverting summing amplifier:

Inputs:V1,V2,V3

Output:-(V1+V2+V3)

ii)Non Inverting summing amplifier:

Inputs:V1,V2,V3

Output:(V1+V2+V3)
CIRCUIT DIAGRAM :

OUTPUT :
RESULT:

Thus the Summing amplifier is virtually verified using Multisim.

 EXP.No: 13
LOG-ANTILOG AMPLIFIER USING OP AMP

DATE:

AIM:
To simulate the log-antilog amplifier and verify it virtually

SOFTWARE USED:
MULTISIM

THEORY:

Logarithmic amplifier
Logarithmic amplifier gives the output proportional to the logarithm of input
signal.If Vi is the input signal applied to a differentiator then the output is Vo = K*ln(Vi)+l where
K is gain of logarithmic amplifier,l is constant.

It is obvious from the log amp that negative feedback is provided from output to
inverting terminal.Using the concept of virtual short between the input terminals of an opamp the
voltage at inverting terminal will be zero volts.(Since the non inverting terminal of opamp is at
ground potential).

Anti-logarithmic amplifier

Antilogogarithmic amplifier gives the output proportional to the antilogarithm of

input signal.If Vi is the input signal applied to a differentiator then the output is Vo = K*(Vi)+l
where K is gain of antilogarithmic amplifier,l is constant.

Measurements
CIRCUIT DIAGRAM :LOG AMPLIFIER

OUTPUT WAVEFORM :
CIRCUIT DIAGRAM :ANTILOG AMPLIFIER

OUTPUT WAVEFORM :
RESULT:

Thus the Log-antilog amplifier is virtually verified using Multisim.