V e rs io n 2 .

1 , 3 0 A u g 2 01 1

N e v e r s t o p t h i n k i n g .
ICE3BR4765JZ
Revision History: 2011-8-30 Datasheet
Previous Version: V2.0
Page Subjects (major changes since last revision)
27 revised outline dimension for PG-DIP-7

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the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com

CoolMOS, CoolSET are trademarks of Infineon Technologies AG.

Edition 2011-8-30
Published by
Infineon Technologies AG,
81726 Munich, Germany,
2009 Infineon Technologies AG.
All Rights Reserved.

Legal disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.

Information
For further information on technology, delivery terms and conditions and prices, please contact your nearest
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Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-support devices or systems only with the express written
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of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
 ICE3BR4765JZ

Off-Line SMPS Current Mode Controller with

integrated 650V CoolMOS and Startup cell
(frequency jitter Mode) in DIP-7
Product Highlights
Active Burst Mode to reach the lowest Standby Power
Requirements < 50mW
Auto Restart protection for overload, overtemperature, overvoltage
PG-DIP-7
External auto-restart enable function
Built-in soft start and blanking window
Extendable blanking Window for high load jumps
Built-in frequency jitter and soft driving for low EMI
Green Mould Compound
Pb-free lead plating; RoHS compliant
Features Description

650V avalanche rugged CoolMOS with built-in ICE3BR4765JZ is derived from ICE3BR4765J in DIP-7
Startup Cell package. The CoolSET-F3R jitter series (ICE3BRxx65J)
Active Burst Mode for lowest Standby Power is the latest version of CoolSET-F3. It targets for the Off-
Fast load jump response in Active Burst Mode Line battery adapters and low cost SMPS for lower power
65kHz internally fixed switching frequency range such as application for DVD R/W, DVD Combi, Blue
Auto Restart Protection Mode for Overload, Open ray DVD player, set top box, etc. Besides inherited the
Loop, VCC Undervoltage, Overtemperature & outstanding performance of the CoolSET-F3 in the
Overvoltage BiCMOS technology, active burst mode, auto-restart
Built-in Soft Start protection, propagation delay compensation, etc.,
Built-in blanking window with extendable blanking CoolSET-F3R series has some new features such as
time for short duration high current built-in soft start time, built-in blanking window, built-in
External auto-restart enable pin frequency jitter, soft gate driving, etc. In case a longer
Max Duty Cycle 75% blanking time is needed for high load application, a simple
Overall tolerance of Current Limiting < 5% addition of capacitor to BA pin can serve the purpose.
Internal PWM Leading Edge Blanking Furthermore, an external auto-restart enable feature can
BiCMOS technology provide wide VCC range provide extra protection when there is a need of
Built-in Frequency jitter and soft driving for low EMI immediate stop of power switching.

Typical Application
+

Snubber Converter
CBulk DC Output
85 ... 270 VAC
-

CVCC
VCC Drain
Startup Cell
Power Management

PWM Controller
Current Mode
CS
Precise Low Tolerance Peak CoolMOS
Current Limitation
RSense

FB
Active Burst Mode
GND Control
Unit BA
Auto Restart Mode
CoolSET-F3R

(Jitter Mode)

Type Package Marking VDS FOSC RDSon1) 230VAC 15%2) 85-265 VAC2)
ICE3BR4765JZ PG-DIP-7 3BR4765JZ 650V 65kHz 4.70 26W 18W
1)
typ @ Tj=25C
2)
Calculated maximum input power rating at Ta=50C, Ti=125C and without copper area as heat sink. Refer to input power curve for other T a.

Version 2.1 3 30 Aug 2011

 ICE3BR4765JZ

Table of Contents Page

1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1 Pin Configuration with PG-DIP-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3.1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.7.3.1 Auto Restart mode with extended blanking time . . . . . . . . . . . . . . . . .17
3.7.3.2 Auto Restart without extended blanking time . . . . . . . . . . . . . . . . . . .18
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.4 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3.7 CoolMOS Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5 Typical CoolMOS Performance Characteristic . . . . . . . . . . . . . . . . . . .24

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 ICE3BR4765JZ

6 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

7 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .29

Version 2.1 5 30 Aug 2011

 ICE3BR4765JZ
Pin Configuration and Functionality

1 Pin Configuration and Functionality

1.1 Pin Configuration with PG-DIP-7 1.2 Pin Functionality
BA (extended Blanking & Auto-restart)
The BA pin combines the functions of extendable
Pin Symbol Function blanking time for over load protection and the external
auto-restart enable. The extendable blanking time
1 BA extended Blanking & Auto-restart function is to extend the built-in 20 ms blanking time by
2 FB FeedBack adding an external capacitor at BA pin to ground. The
external auto-restart enable function is an external
3 CS Current Sense/ access to stop the gate switching and force the IC enter
650V1) CoolMOS Source auto-restart mode. It is triggered by pulling down the
BA pin to less than 0.33V.
4 n.c. not connected
5 Drain 650V1) CoolMOS Drain FB (Feedback)
6 n.c. Not connected The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
7 VCC Controller Supply Voltage PWM-Comparator to control the duty cycle. The FB-
8 GND Controller GrouND Signal is the only control signal in case of light load at
the Active Burst Mode.
1)
at Tj=110C
CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
integrated CoolMOS If voltage in CS pin reaches the
Package PG-DIP-7 internal threshold of the Current Limit Comparator, the
Driver output is immediately switched off. Furthermore
the current information is provided for the PWM-
Comparator to realize the Current Mode.

BA 1 8 GND
Drain (Drain of integrated CoolMOS)
Drain pin is the connection to the Drain of the
integrated CoolMOS.
FB 2 7 VCC

VCC (Power Supply)

CS 3 VCC pin is the positive supply of the IC. The operating
range is between 10.5V and 25V.

n.c. 4 5 Drain GND (Ground)

GND pin is the ground of the controller.

Figure 1 Pin Configuration PG-DIP-7 (top view)

Version 2.1 6 30 Aug 2011

 ICE3BR4765JZ
Representative Blockdiagram

2 Representative Blockdiagram

Figure 2 Representative Blockdiagram

Version 2.1 7 30 Aug 2011

 ICE3BR4765JZ
Functional Description

3 Functional Description
All values which are used in the functional description concept no further external components are necessary
are typical values. For calculating the worst cases the to adjust the blanking window.
min/max values which can be found in section 4 In order to increase the robustness and safety of the
Electrical Characteristics have to be considered. system, the IC provides Auto Restart protection. The
Auto Restart Mode reduces the average power
3.1 Introduction conversion to a minimum level under unsafe operating
conditions. This is necessary for a prolonged fault
ICE3BR4765JZ is derived from ICE3BR4765J in DIP-7 condition which could otherwise lead to a destruction of
package. CoolSET-F3R jitter series (ICE3BRxx65J) is the SMPS over time. Once the malfunction is removed,
the latest version of the CoolSET-F3 for the lower normal operation is automatically retained after the
power application. The particular enhanced features next Start Up Phase. To make the protection more
are the built-in features for soft start, blanking window flexible, an external auto-restart enable pin is provided.
and frequency jitter. It provides the flexibility to increase When the pin is triggered, the switching pulse at gate
the blanking window by simply addition of a capacitor will stop and the IC enters the auto-restart mode after
in BA pin. In order to further increase the flexibility of the pre-defined spike blanking time.
the protection feature, an external auto-restart enable The internal precise peak current control reduces the
features are added. Moreover, the proven outstanding costs for the transformer and the secondary diode. The
features in CoolSET-F3 are still remained such as the influence of the change in the input voltage on the
active burst mode, propagation delay compensation, maximum power limitation can be avoided together
modulated gate driving, auto-restart protection for Vcc with the integrated Propagation Delay Compensation.
overvoltage, over temperature, over load, open loop, Therefore the maximum power is nearly independent
etc. on the input voltage, which is required for wide range
The intelligent Active Burst Mode can effectively obtain SMPS. Thus there is no need for the over-sizing of the
the lowest Standby Power at light load and no load SMPS, e.g. the transformer and the output diode.
conditions. After entering the burst mode, there is still a Furthermore, this F3R series implements the
full control of the power conversion to the output frequency jitter mode to the switching clock such that
through the optocoupler, that is used for the normal the EMI noise will be effectively reduced.
PWM control. The response on load jumps is optimized
and the voltage ripple on Vout is minimized. The Vout is
on well controlled in this mode. 3.2 Power Management
The usually external connected RC-filter in the Drain VCC
feedback line after the optocoupler is integrated in the
IC to reduce the external part count. Startup Cell
Furthermore a high voltage Startup Cell is integrated
into the IC which is switched off once the Undervoltage
Lockout on-threshold of 18V is exceeded. This Startup
Cell is part of the integrated CoolMOS. The external
Depl. CoolMOS

startup resistor is no longer necessary as this Startup

Cell is connected to the Drain. Power losses are
therefore reduced. This increases the efficiency under Power Management
light load conditions drastically. Undervoltage Lockout
Internal Bias
Adopting the BiCMOS technology, it can increase the 18V

design flexibility as the Vcc voltage range is increased 10.5V

to 25V.
The CoolSET-F3R has a built-in 20ms soft start
function. It can further save external component Power-Down Reset Voltage 5.0V
Reference
counts.
There are 2 modes of blanking time for high load
jumps; the basic mode and the extendable mode. The Auto Restart
blanking time for the basic mode is set at 20ms while Mode

the extendable mode will increase the blanking time by Soft Start block Active Burst
adding an external capacitor at the BA pin in addition to Mode
the basic mode blanking time. During this blanking time
window the overload detection is disabled. With this
Figure 3 Power Management

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 ICE3BR4765JZ
Functional Description

The Undervoltage Lockout monitors the external Current Mode means the duty cycle is controlled by the
supply voltage VVCC. When the SMPS is plugged to the slope of the primary current. This is done by comparing
main line the internal Startup Cell is biased and starts the FB signal with the amplified current sense signal.
to charge the external capacitor CVCC which is
connected to the VCC pin. This VCC charge current is
controlled to 0.9mA by the Startup Cell. When the VVCC Amplified Current Signal
exceeds the on-threshold VCCon=18V the bias circuit
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power FB
losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on, a hysteresis start up voltage is implemented. 0.67V
The switch-off of the controller can only take place
when VVCC falls below 10.5V after normal operation
Driver t
was entered. The maximum current consumption
before the controller is activated is about 150mA.
When VVCC falls below the off-threshold VCCoff=10.5V,
the bias circuit is switched off and the soft start counter
is reset. Thus it is ensured that at every startup cycle
the soft start starts at zero.
ton
The internal bias circuit is switched off if Auto Restart
Mode is entered. The current consumption is then
reduced to 150mA. t
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart Figure 5 Pulse Width Modulation
Mode does not require re-cycling the AC line. In case the amplified current sense signal exceeds the
When Active Burst Mode is entered, the internal Bias is FB signal the on-time Ton of the driver is finished by
switched off most of the time but the Voltage Reference resetting the PWM-Latch (see Figure 5).
is kept alive in order to reduce the current consumption The primary current is sensed by the external series
below 450mA. resistor RSense inserted in the source of the integrated
CoolMOS. By means of Current Mode regulation, the
secondary output voltage is insensitive to the line
3.3 Improved Current Mode
variations. The current waveform slope will change with
Soft-Start Comparator the line variation, which controls the duty cycle.
The external RSense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS.
PWM-Latch To improve the Current Mode during light load
FB
C8 R Q conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
Driver the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every time the oscillator shuts down for
S Q maximum duty cycle limitation the switch T2 is closed
by VOSC. When the oscillator triggers the Gate Driver,
0.67V T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
PWM OP small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
x3.3 CS controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
Improved the inverted VOSC signal, the Gate Driver is switched-off
Current Mode until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing VFB below that
Figure 4 Current Mode threshold.

Version 2.1 9 30 Aug 2011

 ICE3BR4765JZ
Functional Description

3.3.1 PWM-OP
The input of the PWM-OP is applied over the internal
Soft-Start Comparator leading edge blanking to the external sense resistor
PWM Comparator RSense connected to pin CS. RSense converts the source
current into a sense voltage. The sense voltage is
FB amplified with a gain of 3.3 by PWM OP. The output of
C8 the PWM-OP is connected to the voltage source V1.
PWM-Latch The voltage ramp with the superimposed amplified
Oscillator current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
VOSC Figure 6).
time delay
circuit (156ns)
Gate Driver 3.3.2 PWM-Comparator
The PWM-Comparator compares the sensed current
0.67V signal of the integrated CoolMOS with the feedback
10k signal VFB (see Figure 8). VFB is created by an external
X3.3 optocoupler or external transistor in combination with
the internal pull-up resistor RFB and provides the load
T2 R1 information of the feedback circuitry. When the
V1
PWM OP amplified current signal of the integrated CoolMOS
C1 exceeds the signal VFB the PWM-Comparator switches
off the Gate Driver.

Voltage Ramp
5V
Figure 6 Improved Current Mode
RFB Soft-Start Comparator

FB
VOSC PWM-Latch
C8
max.
Duty Cycle
PWM Comparator

0.67V
Voltage Ramp t
Optocoupler
PWM OP
CS
0.67V
X3.3
FB

Improved
Gate Driver t Current Mode
156ns time delay

Figure 8 PWM Controlling

Figure 7 Light Load Conditions

Version 2.1 10 30 Aug 2011

 ICE3BR4765JZ
Functional Description

3.4 Startup Phase When the VVCC exceeds the on-threshold voltage, the
IC starts the Soft Start mode (see Figure 10).
The function is realized by an internal Soft Start
resistor, an current sink and a counter. And the
S o ft S ta r t c o u n te r
amplitude of the current sink is controlled by the
counter (see Figure 11).

S o ftS
Soft Start finish

S o ft S ta r t 5V

S o ft S ta r t R SoftS

S o ft- S ta r t SoftS
C o m p a r a to r
G a te D r iv e r
C7 &

G7

Soft Start 32I 8I 4I 2I I

0 .6 7 V Counter
x 3 .3 CS
PW M OP

Figure 9 Soft Start

In the Startup Phase, the IC provides a Soft Start Figure 11 Soft Start Circuit
period to control the primary current by means of a duty After the IC is switched on, the VSFOFTS voltage is
cycle limitation. The Soft Start function is a built-in controlled such that the voltage is increased step-
function and it is controlled by an internal counter. wisely (32 steps) with the increase of the counts. The
. Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
decrease gradually and the duty ratio of the gate drive
increases gradually. The Soft Start will be finished in
20ms (TSoft-Start) after the IC is switched on. At the end
of the Soft Start period, the current sink is switched off.

VSoftS
TSoft-Start
VSOFTS32

V SoftS

V SoftS2 t
V SoftS1 Gate
Driver

t
Figure 10 Soft Start Phase
Figure 12 Gate drive signal under Soft-Start Phase

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 ICE3BR4765JZ
Functional Description

Within the soft start period, the duty cycle is increasing 3.5 PWM Section
from zero to maximum gradually (see Figure 12).
In addition to Start-Up, Soft-Start is also activated at 0.75
each restart attempt during Auto Restart. PWM Section
Oscillator
VSoftS
Duty Cycle
TSoft-Start max

VSOFTS32
Clock

Frequency
Jitter

VFB t

Soft Start
4.0V Block FF1
S Gate Driver
Soft Start 1
Comparator R &
G8 Q
PWM G9
VOUT t Comparator

Current
VOUT Limiting

TStart-Up CoolMOS
Gate

t
Figure 14 PWM Section Block
Figure 13 Start Up Phase
3.5.1 Oscillator
The Start-Up time TStart-Up before the converter output The oscillator generates a fixed frequency of 65KHz
voltage VOUT is settled, must be shorter than the Soft- with frequency jittering of 4% (which is 2.6KHz) at a
Start Phase TSoft-Start (see Figure 13). jittering period of 4ms.
By means of Soft-Start there is an effective A capacitor, a current source and current sink which
minimization of current and voltage stresses on the determine the frequency are integrated. In order to
integrated CoolMOS, the clamp circuit and the output achieve a very accurate switching frequency, the
overshoot and it helps to prevent saturation of the charging and discharging current of the implemented
transformer during Start-Up. oscillator capacitor are internally trimmed. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switching frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 65KHz 2.6KHz at period of 4ms.

3.5.2 PWM-Latch FF1

The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the
integrated CoolMOS. After the PWM-Latch is set, it is
reset by the PWM comparator, the Soft Start
comparator or the Current -Limit comparator. When it is
in reset mode, the output of the driver is shut down
immediately.

Version 2.1 12 30 Aug 2011

 ICE3BR4765JZ
Functional Description

3.5.3 Gate Driver 3.6 Current Limiting

PWM Latch
VCC FF1
Current Limiting

PWM-Latch
1

Propagation-Delay
Gate Compensation

CoolMOS
Vcsth
C10 Leading
Edge
Blanking
PWM-OP 220ns
Gate Driver
&
G10 C12
Figure 15 Gate Driver 0.34V
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. The switch on speed is
slowed down before it reaches the integrated 10k 1pF
Active Burst
CoolMOS turn on threshold. That is a slope control of Mode D1
the rising edge at the output of the driver (see Figure
16).

CS
(internal)
Figure 17 Current Limiting Block
VGate
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS is sensed
ca. t = 130ns via an external sense resistor RSense. By means of
RSense the source current is transformed to a sense
voltage VSense which is fed into the CS pin. If the voltage
5V VSense exceeds the internal threshold voltage Vcsth, the
comparator C10 immediately turns off the gate drive by
resetting the PWM Latch FF1.
t A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
Figure 16 Gate Rising Slope CoolMOS with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
Thus the leading switch on spike is minimized.
output power can be reduced to minimal.
Furthermore the driver circuit is designed to eliminate
cross conduction of the output stage. In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
During power up, when VCC is below the undervoltage
Blanking is integrated in the current sense path for the
lockout threshold VVCCoff, the output of the Gate Driver
comparators C10, C12 and the PWM-OP.
is set to low in order to disable power transfer to the
secondary side. The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. When it is
activated, the current limiting is reduced to 0.34V. This
voltage level determines the maximum power level in
Active Burst Mode.

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Functional Description

3.6.1 Leading Edge Blanking For example, Ipeak = 0.5A with RSense = 2. The current
sense threshold is set to a static voltage level Vcsth=1V
VSense without Propagation Delay Compensation. A current
ramp of dI/dt = 0.4A/s, or dVSense/dt = 0.8V/s, and a
propagation delay time of tPropagation Delay =180ns leads
Vcsth to an Ipeak overshoot of 14.4%. With the propagation
tLEB = 220ns
delay compensation, the overshoot is only around 2%
(see Figure 20).

with compensation without compensation

V
1,3

t 1,25

1,2
Figure 18 Leading Edge Blanking

VSense
1,15

Whenever the integrated CoolMOS is switched on, a 1,1

leading edge spike is generated due to the primary- 1,05

side capacitances and reverse recovery time of the 1

secondary-side rectifier. This spike can cause the gate 0,95

drive to switch off unintentionally. In order to avoid a 0,9

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2 V
premature termination of the switching pulse, this spike
dVSense s
is blanked out with a time constant of tLEB = 220ns.
dt
3.6.2 Propagation Delay Compensation Figure 20 Overcurrent Shutdown
In case of over-current detection, there is always The Propagation Delay Compensation is realized by
propagation delay to switch off the integrated means of a dynamic threshold voltage Vcsth (see Figure
CoolMOS. An overshoot of the peak current Ipeak is
21). In case of a steeper slope the switch off of the
induced to the delay, which depends on the ratio of dI/ driver is earlier to compensate the delay.
dt of the peak current (see Figure 19).
V OSC max. Duty Cycle
Signal2 Signal1
ISense tPropagation Delay
Ipeak2 IOvershoot2
Ipeak1 off time
ILimit
V Sense Propagation Delay t
IOvershoot1
V csth

t
Figure 19 Current Limiting
The overshoot of Signal2 is larger than of Signal1 due Signal1 Signal2
to the steeper rising waveform. This change in the t
slope depends on the AC input voltage. Propagation Figure 21 Dynamic Voltage Threshold Vcsth
Delay Compensation is integrated to reduce the
overshoot due to dI/dt of the rising primary current.
Thus the propagation delay time between exceeding
the current sense threshold Vcsth and the switching off
of the integrated CoolMOS is compensated over
temperature within a wide range. Current Limiting is
then very accurate.

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Functional Description

3.7 Control Unit After the 30us spike blanking time, the Auto Restart
Mode is activated.
The Control Unit contains the functions for Active Burst For example, if CBK = 0.22uF, IBK = 13uA
Mode and Auto Restart Mode. The Active Burst Mode
and the Auto Restart Mode both have 20ms internal Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 72ms
Blanking Time. For the Auto Restart Mode, a further In order to make the startup properly, the maximum CBK
extendable Blanking Time is achieved by adding capacitor is restricted to less than 0.65uF.
external capacitor at BA pin. By means of this Blanking The Active Burst Mode has basic blanking mode only
Time, the IC avoids entering into these two modes while the Auto Restart Mode has both the basic and the
accidentally. Furthermore those buffer time for the extendable blanking mode.
overload detection is very useful for the application that
works in low current but requires a short duration of 3.7.2 Active Burst Mode
high current occasionally.
The IC enters Active Burst Mode under low load
conditions. With the Active Burst Mode, the efficiency
3.7.1 Basic and Extendable Blanking Mode increases significantly at light load conditions while still
maintaining a low ripple on VOUT and a fast response on
load jumps. During Active Burst Mode, the IC is
BA
5.0V
controlled by the FB signal. Since the IC is always
active, it can be a very fast response to the quick
# CBK IBK
change at the FB signal. The Start up Cell is kept OFF
in order to minimize the power loss.
0.9V
1
S1
G2

Internal Bias

C3 Current
Spike
4.0V
Blanking 20 ms Blanking Limiting
30us Time &
G10
&
4.0V
4.0V 20ms G5 Auto
Blanking Restart C4
C4
Time Mode

Active
FB Burst
C5 & Mode
FB &
20ms Active 1.35V G6
C5 Blanking G6 Burst
1.35V Time Mode

Control Unit C6a

3.5V
&
Figure 22 Basic and Extendable Blanking Mode C6b G11
There are 2 kinds of Blanking mode; basic mode and 3.0V
Control Unit
the extendable mode. The basic mode is just an
internal set 20ms blanking time while the extendable
Figure 23 Active Burst Mode
mode has an extra blanking time by connecting an
external capacitor to the BA pin in addition to the pre-
set 20ms blanking time. For the extendable mode, the The Active Burst Mode is located in the Control Unit.
gate G5 is blocked even though the 20ms blanking time Figure 23 shows the related components.
is reached if an external capacitor CBK is added to BA
pin. While the 20ms blanking time is passed, the switch 3.7.2.1 Entering Active Burst Mode
S1 is opened by G2. Then the 0.9V clamped voltage at The FB signal is kept monitoring by the comparator C5.
BA pin is charged to 4.0V through the internal IBK
During normal operation, the internal blanking time
constant current. G5 is enabled by comparator C3. counter is reset to 0. Once the FB signal falls below
1.35V, it starts to count. When the counter reach 20ms

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Functional Description

and FB signal is still below 1.35V, the system enters

the Active Burst Mode. This time window prevents a
sudden entering into the Active Burst Mode due to VFB Entering Leaving
large load jumps. Active Burst Active Burst
After entering Active Burst Mode, a burst flag is set and Mode Mode
the internal bias is switched off in order to reduce the 4.0V
current consumption of the IC to approx. 450uA. 3.5V
3.0V
It needs the application to enforce the VCC voltage
above the Undervoltage Lockout level of 10.5V such 1.35V
that the Startup Cell will not be switched on
accidentally. Or otherwise the power loss will increase
Blanking Timer t
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the 20ms Blanking Time
application. The lowest VCC level is reached at no load
condition.

3.7.2.2 Working in Active Burst Mode

After entering the Active Burst Mode, the FB voltage
rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors VCS t
the FB signal. If the voltage level is larger than 3.5V, the
internal circuit will be activated; the Internal Bias circuit
resumes and starts to provide switching pulse. In Current limit level
Active Burst Mode the gate G10 is released and the 1.03V
during Active Burst
current limit is reduced to 0.34V, which can reduce the Mode
conduction loss and the audible noise. If the load at
0.34V
VOUT is still kept unchanged, the FB signal will drop to
3.0V. At this level the C6b deactivates the internal
circuit again by switching off the internal Bias. The gate VVCC t
G11 is active again as the burst flag is set after entering
Active Burst Mode. In Active Burst Mode, the FB
voltage is changing like a saw tooth between 3.0V and
3.5V (see figure 24).

3.7.2.3 Leaving Active Burst Mode 10.5V

The FB voltage will increase immediately if there is a
high load jump. This is observed by the comparator C4. IVCC t
Since the current limit is app. 34% during Active Burst
Mode, it needs a certain load jump to rise the FB signal
to exceed 4.0V. At that time the comparator C4 resets 2.5mA
the Active Burst Mode control which in turn blocks the
comparator C12 by the gate G10. The maximum
current can then be resumed to stabilize the VOUT.
450uA

VOUT t

Figure 24 Signals in Active Burst Mode

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Functional Description

3.7.3 Protection Modes 3.7.3.1 Auto Restart mode with extended

The IC provides Auto Restart Mode as the protection blanking time
feature. Auto Restart mode can prevent the SMPS from
destructive states. The following table shows the
relationship between possible system failures and the
BA
corresponding protection modes. 5.0V
# CBK IBK
VCC Overvoltage Auto Restart Mode
Overtemperature Auto Restart Mode
0.9V
Overload Auto Restart Mode 1
S1
Open Loop Auto Restart Mode G2

VCC Undervoltage Auto Restart Mode

Short Optocoupler Auto Restart Mode
C3
Spike
Auto restart enable Auto Restart Mode 4.0V
Blanking
30us

Before entering the Auto Restart protection mode, &

some of the protections can have extended blanking
time to delay the protection and some needs to fast 4.0V 20ms
Blanking
G5 Auto
Restart
react and will go straight to the protection. Overload FB C4
Time Mode
and open loop protection are the one can have
extended blanking time while Vcc Overvoltage, Over Control Unit
temperature, Vcc Undervoltage, short opto-coupler
and external auto restart enable will go to protection Figure 25 Auto Restart Mode
right away. In case of Overload or Open Loop, the FB exceeds
After the system enters the Auto-restart mode, the IC 4.0V which will be observed by comparator C4. Then
will be off. Since there is no more switching, the Vcc the internal blanking counter starts to count. When it
voltage will drop. When it hits the Vcc turn off threshold, reaches 20ms, the switch S1 is released. Then the
the start up cell will turn on and the Vcc is charged by clamped voltage 0.9V at VBA can increase. When there
the startup cell current to Vcc turn on threshold. The IC is no external capacitor CBK connected, the VBA will
is on and the startup cell will turn off. At this stage, it will reach 4.0V immediately. When both the input signals at
enter the startup phase (soft start) with switching AND gate G5 is positive, the Auto Restart Mode will be
cycles. After the Start Up Phase, the fault condition is activated after the extra spike blanking time of 30us is
checked. If the fault condition persists, the IC will go to elapsed. However, when an extra blanking time is
auto restart mode again. If, otherwise, the fault is needed, it can be achieved by adding an external
removed, normal operation is resumed. capacitor, CBK. A constant current source of IBK will start
to charge the capacitor CBK from 0.9V to 4.0V after the
switch S1 is released. The charging time from 0.9V to
4.0V are the extendable blanking time. If CBK is 0.22uF
and IBK is 13uA, the extendable blanking time is around
52ms and the total blanking time is 72ms. In combining
the FB and blanking time, there is a blanking window
generated which prevents the system to enter Auto
Restart Mode due to large load jumps.

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Functional Description

3.7.3.2 Auto Restart without extended blanking a trigger signal to the base of the externally added
time transistor, TAE at the BA pin. When the function is
enabled, the gate drive switching will be stopped and
then the IC will enter auto-restart mode if the signal
persists. To ensure this auto-restart function will not be
Auto Restart mis-triggered during start up, a 1ms delay time is
Mode Reset
VVCC < 10.5V
implemented to blank the unstable signal.
1ms
UVLO VCC undervoltage is the Vcc voltage drop below Vcc
counter
turn off threshold. Then the IC will turn off and the start
Auto-restart BA up cell will turn on automatically. And this leads to Auto
Enable Stop
Signal C9
8us
gate Restart Mode.
0.3V Blanking Auto Restart
Time
drive Short Optocoupler also leads to VCC undervoltage as
mode
there is no self supply after activating the internal
25.5V
TAE reference and bias.
120us
C2 Blanking
VCC
Time

VCC Spike
& Blanking
C1
20.5V 30us
G1
softs_period

4.0V
C4
Voltage
FB Thermal Shutdown Reference

Tj >140C

Control Unit

Figure 26 Auto Restart mode

There are 2 modes of VCC overvoltage protection; one
is during soft start and the other is at all conditions.
The first one is VVCC voltage is > 20.5V and FB is > 4.0V
and during soft_start period and the IC enters Auto
Restart Mode. The VCC voltage is observed by
comparator C1 and C4. The fault conditions are to
detect the abnormal operating during start up such as
open loop during light load start up, etc. The logic can
eliminate the possible of entering Auto Restart mode if
there is a small voltage overshoots of VVCC during
normal operating.
The 2nd one is VVCC >25.5V and last for 120us and the
IC enters Auto Restart Mode. This 25.5V Vcc OVP
protection is inactivated during burst mode.
The Thermal Shutdown block monitors the junction
temperature of the IC. After detecting a junction
temperature higher than 130C, the Auto Restart Mode
is entered.
In case the pre-defined auto-restart features are not
sufficient, there is a customer defined external Auto-
restart Enable feature. This function can be triggered
by pulling down the BA pin to < 0.33V. It can simply add

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Electrical Characteristics

4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
(VCC) is discharged before assembling the application circuit.Ta=25C unless otherwise specified.

Parameter Symbol Limit Values Unit Remarks

min. max.
Switching drain current, pulse width tp Is - 1.67 A
limited by Tj=150C
Pulse drain current, pulse width tp limited ID_Puls - 2.32 A
by Tj=150C
Avalanche energy, repetitive tAR limited by EAR - 0.01 mJ
max. Tj=150C1)
Avalanche current, repetitive tAR limited by IAR - 0.5 A
max. Tj=150C1)
VCC Supply Voltage VVCC -0.3 27 V
FB Voltage VFB -0.3 5.5 V
BA Voltage VBA -0.3 5.5 V
CS Voltage VCS -0.3 5.5 V
Junction Temperature Tj -40 150 C Controller & CoolMOS
Storage Temperature TS -55 150 C
Thermal Resistance RthJA - 96 K/W
Junction -Ambient
Soldering temperature, wavesoldering Tsold - 260 C 1.6mm (0.063in.) from
only allowed at leads case for 10s
ESD Capability (incl. Drain Pin) VESD - 2 kV Human body model2)
1)
Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kW series resistor)

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Electrical Characteristics

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter Symbol Limit Values Unit Remarks

min. max.
VCC Supply Voltage VVCC VVCCoff 25 V Max value limited due to Vcc OVP
Junction Temperature of TjCon -25 130 C Max value limited due to thermal
Controller shut down of controller
Junction Temperature of TjCoolMOS -25 150 C
CoolMOS

4.3 Characteristics

4.3.1 Supply Section

Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from 25 C to 125 C. Typical values represent the median values, which are
related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Start Up Current IVCCstart - 150 250 mA VVCC =17V

VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V

IVCCcharge2 0.55 0.9 1.60 mA VVCC = 1V
IVCCcharge3 - 0.7 - mA VVCC =17V
Leakage Current of IStartLeak - 0.2 50 mA VDrain = 450V
Start Up Cell and CoolMOS at Tj=100C
Supply Current with IVCCsup1 - 1.5 2.5 mA
Inactive Gate
Supply Current with Active Gate IVCCsup2 - 2.5 3.4 mA IFB = 0A
Supply Current in IVCCrestart - 250 - mA IFB = 0A
Auto Restart Mode with Inactive
Gate
Supply Current in Active Burst IVCCburst1 - 450 950 mA VFB = 2.5V
Mode with Inactive Gate
IVCCburst2 - 450 950 mA VVCC = 11.5V,VFB = 2.5V
VCC Turn-On Threshold VVCCon 17.0 18.0 19.0 V
VCC Turn-Off Threshold VVCCoff 9.8 10.5 11.2 V
VCC Turn-On/Off Hysteresis VVCChys - 7.5 - V

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Electrical Characteristics

4.3.2 Internal Voltage Reference

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FB
IFB = 0

4.3.3 PWM Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Fixed Oscillator Frequency fOSC1 56.5 65.0 73.5 kHz
fOSC2 59.8 65.0 70.2 kHz Tj = 25C
Frequency Jittering Range fjitter - 2.6 - kHz Tj = 25C
Frequency Jittering period Tjitter - 4.0 - ms Tj = 25C
Max. Duty Cycle Dmax 0.70 0.75 0.80

Min. Duty Cycle Dmin 0 - - VFB < 0.3V

PWM-OP Gain AV 3.1 3.3 3.5

Voltage Ramp Offset VOffset-Ramp - 0.67 - V

VFB Operating Range Min Level VFBmin - 0.5 - V

VFB Operating Range Max level VFBmax - - 4.3 V CS=1V, limited by

Comparator C41)
FB Pull-Up Resistor RFB 9 15.4 22 kW

1)
The parameter is not subjected to production test - verified by design/characterization

4.3.4 Soft Start time

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Soft Start time tSS - 20.0 - ms

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Electrical Characteristics

4.3.5 Control Unit

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Clamped VBA voltage during VBAclmp 0.85 0.9 0.95 V VFB = 4V
Normal Operating Mode
Blanking time voltage limit for VBKC3 3.85 4.00 4.15 V
Comparator C3
Over Load & Open Loop Detection VFBC4 3.85 4.00 4.15 V
Limit for Comparator C4
Active Burst Mode Level for VFBC5 1.25 1.35 1.45 V
Comparator C5
Active Burst Mode Level for VFBC6a 3.35 3.50 3.65 V After Active Burst
Comparator C6a Mode is entered
Active Burst Mode Level for VFBC6b 2.88 3.00 3.12 V After Active Burst
Comparator C6b Mode is entered
Overvoltage Detection Limit for VVCCOVP1 19.5 20.5 21.5 V VFB = 5V
Comparator C1

Overvoltage Detection Limit for VVCCOVP2 25.0 25.5 26.5 V

Comparator C2

Auto-restart Enable level at BA pin VAE 0.25 0.33 0.4 V >30ms

Charging current at BA pin IBK 10.0 13.0 16.9 mA Charge starts after the
built-in 20ms blanking
time elapsed
Thermal Shutdown1) TjSD 130 140 150 C Controller

Built-in Blanking Time for tBK - 20 - ms without external

Overload Protection or enter capacitor at BA pin
Active Burst Mode
Inhibit Time for Auto-Restart tIHAE - 1.0 - ms Count when VCC>18V
enable function during start up
Spike Blanking Time before Auto- tSpike - 30 - ms
Restart Protection
1)
The parameter is not subjected to production test - verified by design/characterization. The thermal shutdown
temperature refers to the junction temperature of the controller.

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP.

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Electrical Characteristics

4.3.6 Current Limiting

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Peak Current Limitation Vcsth 0.96 1.03 1.10 V dVsense / dt = 0.6V/ms
(incl. Propagation Delay) (see Figure 20)
Peak Current Limitation during VCS2 0.29 0.34 0.38 V
Active Burst Mode
Leading Edge Blanking tLEB - 220 - ns

CS Input Bias Current ICSbias -1.5 -0.2 - mA VCS =0V

4.3.7 CoolMOS Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.
Drain Source Breakdown Voltage V(BR)DSS 650 - - V Tj = 110C,
Refer to Figure 30 for
other V(BR)DSS in
different Tj
Drain Source On-Resistance RDSon - 4.70 5.44 W Tj = 25C
- 10.0 12.5 W Tj=125C1)
at ID = 0.5A

Effective output capacitance, energy Co(er) - 4.75 - pF VDS = 0V to 480V1)

related
Rise Time trise - 302) - ns
2)
Fall Time tfall - 30 - ns
1)
The parameter is not subjected to production test - verified by design/characterization
2)
Measured in a Typical Flyback Converter Application

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Typical CoolMOS Performance Characteristic

5 Typical CoolMOS Performance Characteristic

Figure 27 Safe Operating area (SOA) curve for ICE3BR4765JZ

Figure 28 SOA temperature derating coefficient curve

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Typical CoolMOS Performance Characteristic

Figure 29 Power dissipation; Ptot=f(Ta)

Figure 30 Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA

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 ICE3BR4765JZ
Input Power Curve

6 Input Power Curve

Two input power curves giving the typical input power versus ambient temperature are showed below;
Vin=85Vac~265Vac (Figure 31) and Vin=230Vac+/-15% (Figure 32). The curves are derived based on a typical
discontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondary
to primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink for the device.
The input power already includes the power loss at input common mode choke, bridge rectifier and the
CoolMOS.The device saturation current (ID_Puls @ Tj=125C) is also considered.
To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient
temperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 31),
operating temperature is 50C, estimated efficiency is 85%, then the estimated output power is 15W (17.7W *
85%).

Figure 31 Input power curve Vin=85~265Vac; Pin=f(Ta)

Figure 32 Input power curve Vin=230Vac+/-15%; Pin=f(Ta)

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 ICE3BR4765JZ
Outline Dimension

7 Outline Dimension
PG-DIP-7
(Plastic Dual In-Line Outline)

Figure 33 PG-DIP-7 (Pb-free lead plating Plastic Dual-in-Line Outline)

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 ICE3BR4765JZ
Marking

8 Marking

Marking

Figure 34 Marking for ICE3BR4765JZ

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 ICE3BR4765JZ
Schematic for recommended PCB layout

9 Schematic for recommended PCB layout

Figure 35 Schematic for recommended PCB layout

General guideline for PCB layout design using F3/F3R CoolSET (refer to Figure 35):
1. Star Ground at bulk capacitor ground, C11:
Star Ground means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSET device
effectively. The primary DC grounds include the followings.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector
of IC12 should be connected to the GND pin of IC11 and then star connect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearance:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.

Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 35):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5mm (no safety concern)

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 ICE3BR4765JZ
Schematic for recommended PCB layout

b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET and
reduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.
The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through the
sensitive components such as the primary controller, IC11.

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 ICE3BR4765JZ
Schematic for recommended PCB layout

Version 2.1 31 30 Aug 2011

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