VERTEX STANDARD CO., LTD.

4-8-8 Nakameguro, Meguro-Ku, Tokyo 153-8644, Japan

VERTEX STANDARD
VX-1700 Series US Headquarters
10900 Walker Street, Cypress, CA 90630, U.S.A.
YAESU EUROPE B.V.
P.O. Box 75525, 1118 ZN Schiphol, The Netherlands
HF Multi Mode Mobile Radio YAESU UK LTD.
Service Manual Unit 12, Sun Valley Business Park, Winnall Close
Winchester, Hampshire, SO23 0LB, U.K.
VERTEX STANDARD HK LTD.
For USA Version Unit 5, 20/F., Seaview Centre, 139-141 Hoi Bun Road,
Kwun Tong, Kowloon, Hong Kong
2005 VERTEX STANDARD CO., LTD. EC051H95A

Introduction
This manual provides the technical information necessary for servicing the VX-1700 HF Transceiver.
Servicing this equipment requires expertise in handing surface-mount chip components. Attempts by non-
qualified persons to service this equipment may result in permanent damage not covered by the warranty,
and may be illegal in some countries.
Two PCB layout diagrams are provided for each double-sided board in this transceiver. Each side of the board
is referred to by the type of the majority of components installed on that side (Side A or Side B). In most
cases one side has only chip components (surface-mount devices), and the other has either a mixture of both
chip and leaded components (trimmers, coils, electrolytic capacitors, ICs, etc.), or leaded components only.
As described in the pages to follow, the advanced microprocessor design of the VX-1700 Transceiver allows a
complete alignment of this transceiver to be performed without opening the case of the radio; all adjustments
can be performed from the front panel, using the Alignment Mode menu.
While we believe the information in this manual to be correct, VERTEX STANDARD assumes no liability for
damage that may occur as a result of typographical or other errors that may be present. Your cooperation in
pointing out any inconsistencies in the technical information would be appreciated.

Contents
Specifications ...................................................................................................................................................... 2
Exploded View & Miscellaneous Parts .......................................................................................................... 3
Block Diagram .................................................................................................................................................... 5
Connection Diagram .......................................................................................................................................... 6
Circuit Description ............................................................................................................................................. 7
Connector Pinout Diagrams ........................................................................................................................... 10
Alignment .......................................................................................................................................................... 11
ALE-1 Automatic Link Establishment Unit Installation .......................................................................... 19
CE77 PC Programming Software ................................................................................................................... 21
Board Units (Schematics, Layouts & Parts)
MAIN Unit .................................................................................................................................................. 49
PA Unit ........................................................................................................................................................ 71
PANEL Unit ................................................................................................................................................ 81
GPS-INTERFACE Unit .............................................................................................................................. 87
MIC Unit ...................................................................................................................................................... 91
ENC Unit ..................................................................................................................................................... 92
ALE Unit (Option) ..................................................................................................................................... 93

1
Specifications
General
Receiver Frequency Range: 30 kHz ~ 30.0000 MHz
Transmitter Frequency: 1.600 ~ 30.0000 MHz
Emission Modes: A1A (CW), J3E (LSB/USB), A3E (AM), J2B (USB/LSB),
Frequency Synthesizer Step: 10 Hz, 100 Hz, 1 kHz
Frequency Stability: 1 ppm (Typical)
Operating Temperature Range: 14 F ~ 131 F (10 ~ +55 C) @Duty Cycle TX:RX = 1 min.: 4 min.
Antenna Impedance: 50 Ohms
Supply Voltage: 13.8 Volts DC 15%, negative ground
Power Consumption: 25 mA (Standby)
1.0 A (Receive, no signal)
1.5 A (Receive)
22 A (Transmit, 125 Watts output)
Dimensions (WxHxD): 9.5 x 3.9 x 11.2 (241 x 99 x 285 mm)
Weight (approx.): 9.5 lbs (4.3 kg)

Transmitter
Power Output: 125 Watts (A1A, J2B, J3E @1.6000 ~ 3.9999 MHz)
100 Watts (A1A, J2B, J3E @4.0000 ~ 30.0000 MHz)
31 Watts AM Carrier (A3E @1.6000 ~ 3.9999 MHz)
25 Watts AM Carrier (A3E @4.0000 ~ 30.0000 MHz)
Modulation Types: J3E: PSN type modulator,
A3E: Low-level (early stage)
Spurious Radiation: Better than 56 dB
J3E Carrier Suppression: Better than 50 dB below peak output
Undesired Sideband Suppression: Better than 60 dB below peak output
J3E Audio Response: Not more than 6 dB from 400 Hz ~ 2500 Hz
Occupied Bandwidth: A1A: less than 0.5 kHz
J3E: less than 3.0 kHz
A3E: less than 6.0 kHz
Microphone Impedance: 200 ~ 10 k Ohms (600 Ohms Nominal)

Receiver
Circuit Type: Double-conversion Superheterodyne
Intermediate Frequencies: 1st: 45.274 MHz, 2nd: 24 kHz
Sensitivity: A1A/J2B/J3E A3E
0.1 ~ 0.5 MHz
0.5 ~ 1.6 MHz: 1.41 V 8 V
1.6 ~ 30 MHz: 0.16 V 1 V
(A1A/J2B/J3E/A3E: S/N 10 dB)
Squelch Sensitivity (A1A/J2B/J3E): 0.1 ~ 0.5 MHz
0.5 ~ 1.6 MHz: 2.5 V
1.6 ~ 30 MHz: 2 V
IF Rejection: Better than 80 dB
Image Rejection: Better than 80 dB
Selectivity: 6 dB 60 dB
A1A(W), J2B(W), J3E > 2.2 kHz < 4.5 kHz
A1A(N), J2B(N) > 500 Hz < 2.0 kHz
A3E > 6 kHz < 20 kHz
Audio Output: At least 2.2 Watts into 8 Ohms @ 10% THD
Audio Output Impedance: 4 ~ 16 Ohms (8 Ohms Nominal)
Conducted Radiation: Less than 4000 W
Specifications are subject to change without notice or obligation.

2
 Exploded View & Miscellaneous Parts
14

14

14

14 14

RA0695200
14 COVER (TOP)

14

13
14
1

PA UNIT 13 2

13
13
P1090352
CONNECTOR (FM-MDR-MI)
6
6 6
13 3 6
15
5
RA0635400 RA0695600
CHASSIS HOLDER PLATE (CW)
5

T9207202A
WIRE ASSY
PANEL UNIT
RA0695700
12 HOLDER PLATE (D-SUB)
RA0696100
REFLECTOR SHEET
RA0727200
DIFFUSER SHEET (BLIND) (2pcs)
4 9
RA0695800 9
INTER CONNECTOR (2pcs)
G6090162 MAIN UNIT
LCD
4
10

RA0695000
FRONT PLATE (A) 12 RA0695900
LIGHT GUIDE (LCD)
M4090146
SPEAKER 12 RA0727100 GPS INTERFACE UNIT SUPPLIED ACCESSORIES
RA0694600 12 DIFFUSER SHEET (LCD) VXSTD P/N DESCRIPTION QTY.
PACKING PAD (SP) 11 RA0696000 2 A06870001 MH-31A8J Hand Microphone 1
2
RA069450A LCD HOLDER T9023725 DC Power Cord 1
RUBBER KNOB (PW) MIC UNIT RA0696200 Q0000074 Spare Fuse (25 A Blade Type) 1
11
RA0695500 SPONGE RUBBER (LCD)
13 13
PACKING PAD (CHASSIS) CONNECTION CABLES
ENC UNIT
8 REF. VXSTD P/N DESCRIPTION
RA0725400 M2090040 P0001 T9315504 Coaxial Cable (J1001
J2006)
9 RA0695300 FAN P0002 T9315905 Coaxial Cable (J1002
J2001)
FRONT PANEL ASSY
9 COVER (BOTTOM)
P0004 T9207203 30-pin Flat Cable ( J1003
J2002)
14 P0005 T9207210 13-pin Molex (J1008
J4001)
RA0695000 P0006 T9207211 8-pin Molex (J1005
J6002)
FRONT PLATE (B) P0007 T9207209 8-pin Molex (J3004
J6101)
4 P0008 T9207117A 30-pin Flat Cable (J1004
J3001)
14
RA069420A REF. VXSTD P/N DESCRIPTION QTY.
RUBBER KNOB (12KEY) 1 U02308002 SEMS SCREW SM3X8NI 4
RA069430A 4 2 U03308002 SEMS SCREW ASM3X8NI 7
RUBBER KNOB (4KEY) 3 U04410002 SEMS SCREW HSM4X10NI 1
RA069440A 4 U10306001 TRUSS HEAD SCREW M3X6 4
14
RUBBER KNOB (UP/DOWN) 5 U20205002 BINDING HEAD SCREW M2.6X5NI 2
S4000043 6 U20306002 BINDING HEAD SCREW M3X6NI 4
RA0694800 RA0694900 CASE LEG (FF-003) 7 U20406007 BINDING HEAD SCREW M4X6B 2
KNOB (L) KNOB (S) R3100700A 14 8 U20430002 BINDING HEAD SCREW M4X30(Ni) 4
FOOT 9 U24106002 TAPTITE SCREW M2X6NI 6
R3100700A S4000043
7 FOOT 10 U24108002 TAPTITE SCREW M2X8NI 3
CASE LEG (FF-003)
11 U24206001 TAPTITE SCREW M2.6X6 2
12 U24208002 TAPTITE SCREW M2.6X8NI 4
13 U24308002 TAPTITE SCREW M3X8NI 14
14 U31306007 OVAL HEAD SCREW M3X6B 12
7 15 U70004012 PLAIN WASHER FW4BSNI 1
R0145630
STAND Non-designated parts are available only as part of a designated assembly.

3
Exploded View & Miscellaneous Parts
Note

4
Block Diagram

5
Connection Diagram

6
 Circuit Description
Receive Signal Path The DSP IC Q1035 (UPD77115) outputs AGC data
Incoming RF signal from the ANT jack is delivered which is proportionate to the received signal
to the PA Unit, and passes through the TX/RX relay strength to the main CPU Q1018 (HD64F2134). The
RL2009 to J2006. main CPU Q1018 (HD64F2134), in turn, outputs a
DC voltage in accordance with the received signal
The RF signal is then applied to J1001 on the MAIN
strength. This DC voltage is fed through buffer am-
Unit, and passed through the limiter circuit consist-
plifier Q1039 (LM2904PW) to RF amplifiers Q1022
ing of D1006, D1007, D1008, and D1009 (all RLS245)
& Q1024 (both 2SK520) and gate 2 of IF amplifier
to prevent distortion from high RF signal input, and
Q1050 (3SK151GR), to reduce their gains when
is fed to one of eight band-pass filters which strip
strong signals are present in the receiver passband.
away unwanted signals prior to delivery of the in-
coming signal to the RF amplifiers, Q1022 and Q1024 Transmit Signal Path
(both 2SK520-K41). The speech audio from the microphone is delivered
The amplified RF signal passes through a low-pass to J6001 on the MIC Unit, then applied to J1005 on
filter to the doubly-balanced mixer D1032 the MAIN Unit.
(HSB88WS), where the RF signal is mixed with the The speech audio is amplified by Q1032-1
1st local signal delivered from buffer amplifier (UPC4572G2), then passed though the clipper,
Q1029 (2SC2954), resulting in a 45.274 MHz 1st IF D1044 (MC2850), and further amplified by Q1032-2
signal. (UPC4572G2).
The 45.274 MHz 1st IF signal is fed through mono- The amplified speech audio is fed through the A/D
lithic crystal filter XF1001, which strips away un- converter Q1081 (AK4550VT), then delivered to the
wanted mixer products, and is amplified by 1st IF DSP IC Q1035 (UPD77115), where the speech au-
amplifier Q1050 (3SK151GR); the 1st IF signal is dio is modulated in the 24 kHz TX 1st IF signal in
then applied to the 2nd mixer Q1052 (RF2713), accordance with the mode selection data from the
where it is mixed with the 45.25 MHz 2nd local sig- main CPU, Q1018 (HD64F2134).
nal which is divided from 90.5 MHz reference sig-
The modulated signal is fed through the D/A con-
nal delivered from buffer amplifier Q1075
verter Q1071 (AK4528A) and buffer amplifier Q1034
(2SC2714Y), resulting in a 24 kHz 2nd IF signal.
(UPC4572G2) to the mixer Q1054 (RF2713) where
The 24 kHz 2nd IF signal is fed through buffer am- the 24 kHz TX 1st IF signal is mixed with 1st local
plifiers Q1030 and Q1041 (both UPC4572G2) to the signal delivered from buffer amplifier Q1075
A/D converter Q1071 (AK4528A), then delivered to (2SC2714Y), resulting in a 45.274 MHz IF signal.
the DSP IC Q1035 (UPD77115), where the 24 kHz
The resulting 45.274 MHz IF signal is buffered by
2nd IF signal is demodulated in accordance with the
Q1049 (3SK151GR), then delivered to the monolith-
mode selection data from the main CPU Q1018
ic crystal filter XF1001, which strips away unwant-
(HD64F2134). The demodulated signal is delivered
ed mixer products, and then is amplified by Q1043
to the D/A converter Q1081 (AK4550VT) which con-
(3SK151GR). The amplified IF signal is delivered
verts the demodulated signal to audio.
to doubly-balanced mixer D1032 (HSB88WS),
The audio signal from the D/A converter Q1081 where it is mixed with the PLL local signal from the
(AK4550VT) is fed through a low-pass filter at Q1036 buffer amplifier, Q1029 (2SC2954).
(UPC4572G), which eliminates high-pitched noise
The resulting the RF signal at the transmit frequen-
on the audio signal, and is fed to the AF mute gate
cy is fed through a low-pass filter circuit, and then
Q1092 (2SJ125D), then applied to the audio ampli-
is amplified by Q1026 (2SC2714Y) and buffer am-
fier Q1055 (TDA2003H). The amplified audio signal
plifier Q1025 (2SC3357), and then filtered by one
is delivered to J3001 on the PANEL Unit, then pass-
of eight band-pass filters to suppress out-of-band
es through the speaker switch RL3001/Q3006
responses. The RF signal is then amplified by Q1001
(DTC143ZE) to the internal or external speaker.
(2SC2954) and delivered to the PA Unit.
7
Circuit Description
On the PA Unit, the low-level RF signal from the IC Q1056 (ADF4001BRU), which contains a refer-
MAIN Unit is amplified by pre-driver Q2001 ence divider, serial-to-parallel data latch, program-
(RD06HHF1), push-pull driver Q2008/Q2009 (both mable divider, phase comparator and a swallow
RD16HHF1), and push-pull final amplifier Q2012/ counter. The sample VCO signal is divided by the
Q2013 (both SD1405), which provides up to 120 programmable divider section of the Q1056
watts of RF output power. (ADF4001BRU). Meanwhile, the output from the
22.625 MHz TCXO reference oscillator, X1003, is
The RF output from the final amplifier is fed through
amplified by Q1062 (TC7S04FU) and divided by the
the one of seven low-pass filters, sampling direc-
DDS IC Q1060 (AD9833BRM) in accordance with
tional coupler T2005, and TX/RX relay RL2009 be-
the PLL dividing data from the main CPU, Q1018
fore delivery to the antenna jack.
(HD64F2134), then fed through the buffer amplifi-
The sampling directional coupler senses forward ers Q1063 (2SC2714Y) to ceramic filter CF1001. The
and reverse power output, which is rectified by divided and filtered reference signal is applied to
D2017 and D2018 (both MA729), respectively, and the reference divider section of the PLL subsystem
the DC voltage is then amplified by Q2015 IC Q1056 (ADF4001BRU), where it is divided by 25/
(LM2904PW) on the PA Unit. 26 to produce the loop reference.
The DC voltages derived from forward and reverse The divided signal from the programmable divider
power are applied to J1003 on the MAIN Unit, and (derived from the VCO), and that derived from the
then amplified by Q1040 (LM2904PW) and Q1044 reference oscillator, are applied to the phase detec-
(2SC2812). The amplified DC voltage is fed back to tor section of the PLL subsystem IC Q1056
the 2nd gate of the 45.275 MHz IF amplifier Q1043 (ADF4001BRU), which produces a pulsed output
(3SK151GR), so that the transmitters IF gain can with pulse duration depending on the phase differ-
be regulated by this sensing of the power output, ence between the input signals. This pulse train is
preventing overdrive or damage caused by trans- fed through the loop filter, consisting of resistors
mission into an excessive impedance mismatch at R1222, R1233, & R1247 and capacitors C1278, C1284,
the antenna. C1298, C1308, & C1418, then fed back to the VCO
varactor diodes D1047, D1048, D1049, D1050,
PLL Circuit
D1051, D1052, D1053, and D1054 (all HVU359).
The PLL local signal for the receiver 1st local and
the transmitter final local is generated by one of two Changes in the DC voltage applied to these varac-
VCOs: Q1072 or Q1073 (both 2SK210GR) in con- tor diodes affect the reactance in the tank circuit of
junction with varactor diodes D1047, D1048, D1049, VCOs Q1072 and Q1073 (both 2SK210GR), chang-
D1050, D1051, D1052, D1053, and D1054 (all ing the oscillating frequency according to the phase
HVU359) on the MAIN Unit. The oscillating frequen- difference between the signals derived from the
cy is determined primarily by the level of DC volt- VCO and the TCXO reference oscillator. The VCO
age applied to the varactor diodes. The VCO output is thus phase-locked to the reference frequency stan-
is buffered by Q1066 (2SK302Y), amplified by Q1074 dard.
(2SC2714Y), and band-pass filtered by capacitors A portion of the output of reference signal from
C1389, C1391, C1397, C1400, C1409, and C1420 and TCXO X1003 is multiplied by four at Q1070
coils L1070, L1071, L1074, and L1076. The filtered (2SC2714Y). The resulting 90.5 MHz signal is buff-
PLL local signal is fed through buffer amplifiers ered by Q1075 (2SC2714Y), then applied to a low-
Q1027 (2SC2714Y), Q1028 (2SC3356), and Q1029 pass filter, consisting of capacitors C1401, C1405,
(2SC2954) to the TX final mixer or RX 1st mixer C1410, C1411, and C1421 and coils L1075 and L1077.
D1032 (HSB88WS). The filtered reference signal is applied to the TX 1st
A portion of the output of buffer amplifier Q1066 mixer Q1054 and RX 2nd mixer Q1052 (both
(2 S K 3 0 2 Y) is further amplified by Q1064 RF2713).
(2SC2714Y), then delivered to the PLL subsystem

8
 Circuit Description
Control Circuit TX/RX Control
Major frequency control functions such as channel When the PTT switch is pressed, pin 21 of the main
selection, display, and PLL divider control are per- CPU Q1018 (HD64F2134) goes low, which causes
formed by main CPU Q1018 (HD64F2134) on the pin 60 of the main CPU Q1018 (HD64F2134) to go
MAIN Unit, at the command of the user via the tun- low. This signal disables the receiver 12 V bus at
ing knob and function switches on the front panel. Q1046 (2SA1602A). At the same time, pin 59 of the
main CPU Q1018 (HD64F2134) goes low to activate
The programmable divider data for the PLL from
the transmit 12 V bus at Q1048 (2SA1365).
the main CPU is applied directly to DDS IC Q1016
(AD9833BRM) and PLL subsystem IC Q1056 Power Supply & Regulation
(ADF4001BRU).
The +5 V bus for the main CPU Q1018 (HD64F2134)
The Mode selection data from the main CPU is also is derived from the 13.5 V bus via regulator Q1012
delivered to DSP IC Q1035 (UPD77115) to control (BA05FP) on the MAIN Unit. The +8 V bus is de-
the various circuits required for the selected mode. rived from the 13.5 V bus via regulator Q1007
The Band selection binary data from the main CPU (KIA7808API) on the MAIN Unit.
is decoded (BCD to Decimal) by Q1011 (TC4028BF). A portion of the +8 V bus is regulated by Q1008
The resulting decimal outputs are level-shifted by (L78M05T) for the +5 V bus, and is regulated by
Q1003 (TD62783AF) to select the active band-pass Q1006 (UPC2926) for the +2.6 V bus required by the
filter on the MAIN Unit required for the operating DSP IC Q1035 (UPD77115GK).
frequency. Also, the decimal outputs from Q1003
(TD62783AF) are delivered to PA Unit, where they
are used to select the active low-pass filter required
for the operating frequency.

9
Connector Pinout Diagrams
MIC Jack GPS Jack
(As Viewed From Front Panel) (As Viewed From Rear Panel)

P ENB
CNTL GND Connected with , , , and .
PTT GPS Data Input (+)
MIC N/C
MIC GND Connected with , , , and .
+ 5V GPS Data Input (--)
UP Connected with , , , and .
DOWN Connected with , , , and .
Connected with , , , and .
NC
Pin 3 PTT Open Circuit Voltage: 5 V, Closed Circuit Current: 1 mA

ACC Jack TUNE Jack DATA Jack

(As Viewed From Rear Panel) (As Viewed From Rear Panel) (As Viewed From Rear Panel)

+13.8 V OUT
TX GND +13.8 V OUT
GND TX GND DATA IN
BAND DATA A GND GND
BAND DATA B RX D DATA PTT
BAND DATA C TX D DCD
BAND DATA D TUNER SENSE DATA OUT
TX-INH RESET SQL OUT
EXT ALC Input TX-INH
TX REQ

Pin 1 +13.8 VMax. 1 A Pin 1 +13.8 VMax. 1 A Pin 1 DATA IN 60 mVp-p @1 k.

This terminal is connected This terminal is connected Pin 5 DATA OUT 500 mVp-p @1 k
in parallel with the pin 1 of in parallel with the pin 1 of Pin 6 SQL OUT SQL OPEN: 5 V
TUNE Jack. ACC Jack. SQL CLOSE: 0 V
Pin 2 TX GND Open Collector Pin 2 TX GND Open Collector
(Max. 60 V, 1A) (Max. 60 V, 1A)
This terminal is connected This terminal is connected
in parallel with the pin 2 of in parallel with the pin 2 of
TUNE Jack. ACC Jack.

Accessory Port (Located on the MAIN Unit)

ENCR_TXIN
ENCR_RXIN
INDICATOR
CODE (8)
CODE (4)
CODE (2)
CODE (1)
ENCR_RXOUT
CLEAR/SCRAMBLE
PTT
VCC
GND
ENCR_TXOUT

10