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Vedic Mathematics in Computer: A Survey

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 Shivangi Jain et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 5 (6) , 2014, 7458-7459

Vedic Mathematics in Computer: A Survey

Shivangi Jain , Prof. V. S. Jagtap

Maharashtra Institute of Technology,

Pune, India

Abstract-Knowingly or unknowingly we always use Vedic Nikhilam Sutra and Parvartya Sutra from vedic
Sutras in everyday world of technology. As an example, mathematics for binary division. Their approach shows
whenever we use i<-- i+1 or i<--i1 in software routines, we improvement in time delay as well as complexity [1].
use EkadhikinaPurvena and EkanyunenaPurvena Sutras Honey DurgaTiwari et al. gave a multiplier and square
respectively. Likewise, many Vedic sutras are used in
multiplier unit of computer. It will give faster results, which is
architecture for low power and high speed applications.
very much required in various applications like cryptographic Their approach depends upon ancient vedic mathematical
algorithms, image processing applications. Traditional sutras i.e. urdhvatirygbhyam and nikhilam sutra. They
methods used for multiplication, division require more time as showed that nikhilam sutra can be used efficiently for
compared to Vedic methods. UrdhvaTiryagbhyam, Nikhilam multiplication of two large numbers by reducing it to the
sutra are used for multiplication purpose. It require less time, multiplication of two small numbers. As compared to booth
power and give results faster. and array multiplier their approach is more efficient in
terms of space and time delay [2].
Keywords: Vedic sutra, UrdhvaTiryagbhyam, Nikhilam Sutra, DevikaJaina et al. proposed a design for multiplier
Dhvajanaka Sutra, Parvartya sutra, cryptography, image
processing.
accumulator unit (MAC). The multiplier used in MAC is
based on vedic mathematics sutra urdhvatiryagbhyam.
I. INTRODUCTION Their approach is good for digital signal processing as it
Ancient Indian sculptures (Vedas) contain Indian system of require low power. They used VHDL for coding. They
mathematics which was rediscovered in the early twentieth compared their approach with modified booth Wallace
century. It includes Vedic mathematical formulae which multiplier and high speed vedic multiplier and found that
can be applied to various branches of mathematics. The vedic approach is more efficient than with modified booth
conventional mathematical algorithms are simplified and Wallace multiplier compared ones [3].
also optimized by using vedic sutras. Trigonometry, plain Akhalesh K. Itawadiya et al. identified importance of
and spherical geometry, conics, calculs are one of few areas Digital Signal Processing (DSP) operations and use of
where these vedic sutras can be applied efficiently. Now a multiplication in these operations e.g. convolution,
days, because of increasing demand of digital signal correlation. They gave a simple and easy method for
processing, image processing and other heavy calculating DSP operations for small length of sequences.
computational applications require faster computation by For this purpose they used urdhvatiryagbhyam, a sutra from
processor. Higher throughput arithmetic operations are ancient vedic mathematics, which is used for doing
required in these signal processing applications. multiplication. They implemented these operations in
Multiplication, division are one of arithmetic operations MATLAB and showed that this approach require less
which require heavy calculations. Traditional methods for processing time as compared to inbuilt functions of
doing these operations take a lot of processing time. These MATLAB [4].
traditional methods include array, booth, carry save, Sushma R. Huddar et al. identified need of high speed
Wallace tree, etc. Multiplier architecture based all these cryptographic algorithm used in secure transactions. To
methods are not very efficient in terms of speed, area, achieve this, they developed an efficient architecture for
power. Vedic multiplication involves fewer steps to solve performing mix columns and inverse mix columns
multiplication than traditional multiplication. This helps to operation. This operation is important in Advanced
achieve optimization at all levels of design of digital Encryption Standard method of cryptography. They used
systems reducing power consumption. Vedic mathematics ancient vedic mathematic sutra for this purpose and their
based multipliers are efficient in terms of speed, power and method gave two times speed as compared to traditional
area. In this paper, we reviewed various papers that used methods used for this purpose [5].
vedic mathematical sutras for designing multiplier. M.Ramalatha et al. designed high speed energy efficient
ALU. They used vedic mathematics techniques for this
II. RELATED WORK purpose. Their high speed multiplier helps coprocessor
Surabhi Jain et al. studied vedic mathematics and using that which reduces load of processor. They showed that
gave binary division algorithm as well as high speed UrdhvaTiryagbhyam method from vedic mathematics is
deconvolution algorithm which can be used in image very efficient for multiplication operation. This method
processing. As division is bulky and difficult arithmetic reduces unwanted multiplication and produces intermediate
operation, it require higher space and time complexity results parallely [6].
while implementing on VLSI architecture. They used R. ThamilChelvan et al. gave implementation for fixed and
floating point division using vedic mathematics sutra

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 Shivangi Jain et al, / (IJCSIT) International Journal of Computer Science and Information Technologies, Vol. 5 (6) , 2014, 7458-7459

dhvajanka. They showed that their technique is used in the divisor but the number of remainders normalization
RSA cryptographic algorithm. RSA involves division required. Nikhilam and Parvartya sutra are used for
operation and their method using vedic sutra shows greater division purpose. This approach is faster as it involves
efficiency as compared to conventional division algorithm. addition and negation operations while traditional approach
They used VHDL for coding [7]. uses successive subtraction methods which are time
DigantaSengupta et al. gave algorithm based on ancient consuming. But they did not test VLSI implementation of
vedic mathematics, for fast BCD division.They showed that this algorithm [8].
execution time does not depend upon size of dividend or

Publisher
Methods/ Sutras Language or
Sr.No. Title Of Paper And Features
From Veda Tool
Year
Binary Division Algorithm
and High Speed Applied For calculating
IEEE- Nikhilam, Parvarty VHDL and
1. Deconvolution Algorithm deconvolution, reduced time delay
2014 Sutra Xilinx ISE
(Based on Ancient Indian and complexity.
Vedic Mathematics)
Multiplier design based on Faster multiplier and square ALTERA
IEEE- UrdhvaTiryakbhyam,
2. ancient Indian Vedic architecture, delay and design area Cyclone II
2008 Nikhilam
Mathematics less. FPGA
Binary number multiplication,
Vedic Mathematics Based IEEE- VHDL and
3. UrdhvaTiryakbhyam Realized easily on silicon due to
Multiply Accumulate Unit 2011 Xilinx ISE
regular and parallel structure.
Vedic mathematics based DSP
Design a DSP Operations IEEE- requires less processing time than
4. UrdhvaTiryakbhyam Matlab
using Vedic Mathematics 2013 inbuilt MATLAB functions, Gives
better result.
Novel Architecture for
UrdhvaTiryakbhyam,
Inverse Mix Columns for IEEE-
5. Advanced Encryption Low on-chip area and high speed. Xilinx
AES using Ancient Vedic 2013
Standard (AES)
Mathematics on FPGA
High Speed Energy
Efficient ALU Design IEEE- Parallel generation of intermediate
6. UrdhvaTiryakbhyam -
using Vedic Multiplication 2009 products
Techniques
VHDL and
Implementation of fixed Used in division of RSA
IJVES- FPGA synthesis
7. and floating point division Dhvajanaka Sutra encryption/decryption, efficient in
2013 using Xilinx
using Dhvajanaka sutra terms of area and speed.
library
A New Paradigm In Fast The computation time required by
BCD Division Using ICCSEA- Nikhilam and Parvartya the Vedic Division Algorithm is
8. -
Ancient Indian Vedic 2013 sutra approximately constant irrespective
Mathematics Sutras of the size of the dividend.
Table 1: Survey of Different Multiplier Design Using Vedic Math

III. CONCLUSION 3 DevikaJaina, KabirajSethi and Rutuparna Panda, Vedic

Mathematics Based Multiply Accumulate Unit, 978-0-7695-4587-
In this work, we focus on different designs of multipliers 5/11 2011 IEEE.
which are based on Vedic mathematical sutras. Vedic 4 Akhalesh K. Itawadiya, Rajesh Mahle, Vivek Patel, Dadan Kumar,
mathematic sutras are used in place of different arithmetic Design a DSP Operations using Vedic Mathematics, 978-1-4673-
operations like multiplication, division. They are useful in 4866-9/13/2013 IEEE.
5 Sushma R Huddar, SudhirRaoRupanagudi, Ramya Ravi,
different applications like digital signal processing, image ShikhaYadav& Sanjay Jain, Novel Architecture for Inverse Mix
processing, and computation of heavy calculations. More Columns for AES using Ancient Vedic Mathematics on FPGA,
focus on use of Vedic mathematical sutras used in 978-1-4673-6217-7/13/ 2013 IEEE.
multiplier will give better results and have a lot of scope in 6 M. Ramalatha, K. Deena Dayalan, P. Dharani, S. Deborah Priya,
High Speed Energy Efficient ALU Design using Vedic
computer field. Multiplication Techniques, 978-1-4244-3834-1/09/ 2009 IEEE.
7 R.ThamilChelvan, S.RoobiniPriya, Implementation of fixed and
REFERENCES floating point division using dhvajanka sutra, Vol 04, Issue 02;
1 Surabhi Jain, MukulPancholi, Harsh Garg, SandeepSaini, Binary March - April 2013, International Journal of VLSI and Embedded
Division Algorithm and High Speed Deconvolution Algorithm Systems-IJVES, ISSN: 2249 6556.
(Based on Ancient Indian Vedic Mathematics), 978-1-4799-2993- 8 DigantaSengupta, Mahamuda Sultana, AtalChaudhuri, A New
1/14/ 2014 IEEE. Paradigm In Fast BCD Division Using Ancient Indian Vedic
2 Honey DurgaTiwari, GanzorigGankhuyag, Chan Mo Kim, Yong Mathematics Sutras,David C. Wyld (Eds) : ICCSEA, SPPR, CSIA,
Beom Cho, Multiplier design based on ancient Indian Vedic WimoA 2013.
Mathematics, 978-1-4244-2599-0/08/ 2008 IEEE.

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