LM56

www.ti.com SNIS120G APRIL 2000 REVISED FEBRUARY 2013

LM56 Dual Output Low Power Thermostat

Check for Samples: LM56

1FEATURES DESCRIPTION

2 Digital Outputs Support TTL Logic Levels The LM56 is a precision low power thermostat. Two
stable temperature trip points (VT1 and VT2) are
Internal Temperature Sensor generated by dividing down the LM56 1.250V
2 Internal Comparators with Hysteresis bandgap voltage reference using 3 external resistors.
Internal Voltage Reference The LM56 has two digital outputs. OUT1 goes LOW
when the temperature exceeds T1 and goes HIGH
Available in 8-pin SOIC and VSSOP Packages
when the the temperature goes below (T1THYST).
Similarly, OUT2 goes LOW when the temperature
APPLICATIONS exceeds T2 and goes HIGH when the temperature
Microprocessor Thermal Management goes below (T2THYST). THYST is an internally set 5C
typical hysteresis.
Appliances
Portable Battery Powered 3.0V or 5V Systems The LM56 is available in an 8-lead VSSOP surface
mount package and an 8-lead SOIC.
Fan Control
Industrial Process Control
HVAC Systems
Remote Temperature Sensing
Electronic System Protection

Table 1. Key Specifications

VALUE UNIT
Power Supply Voltage 2.7V10 V
Power Supply Current 230 A (max)
VREF 1.250 V 1% (max)
Hysteresis Temperature 5 C
(+6.20 mV/C x T) +
Internal Temperature Sensor Output Voltage mV
395 mV

Table 2. Temperature Trip Point Accuracy

LM56BIM LM56CIM
+25C 2C (max) 3C (max)
+25C to +85C 2C (max) 3C (max)
40C to +125C 3C (max) 4C (max)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright 20002013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM56
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Simplified Block Diagram and Connection Diagram

Block Diagram

Typical Application

VT1 = 1.250V x (R1)/(R1 + R2 + R3)

VT2 = 1.250V x (R1 + R2)/(R1 + R2 + R3)
where:
(R1 + R2 + R3) = 27 k and
VT1 or T2 = [6.20 mV/C x T] + 395 mV therefore:
R1 = VT1/(1.25V) x 27 k
R2 = (VT2/(1.25V) x 27 k) R1
R3 = 27 k R1 R2

Figure 1. Microprocessor Thermal Management

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings (1)

Input Voltage 12V
Input Current at any pin (2) 5 mA
Package Input Current (2) 20 mA
Package Dissipation at TA = 25C (3) 900 mW
Human Body Model - Pin 3 Only 800V
All other pins 1000V
ESD Susceptibility (4)
Machine Model 125V
Storage Temperature 65C to + 150C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the LM56 Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
(2) When the input voltage (VI) at any pin exceeds the power supply (VI < GND or VI > V+), the current at that pin should be limited to 5 mA.
The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 5 mA to four.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature),
JA (junction to ambient thermal resistance) and TA (ambient temperature). The maximum allowable power dissipation at any
temperature is PD = (TJmaxTA)/JA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax =
125C. For this device the typical thermal resistance (JA) of the different package types when board mounted follow:
(4) The human body model is a 100 pF capacitor discharge through a 1.5 k resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin.

Operating Ratings (1) (2) (3)

Operating Temperature Range TMIN TA TMAX
LM56BIM, LM56CIM 40C TA +125C
Positive Supply Voltage (V+) +2.7V to +10V
Maximum VOUT1 and VOUT2 +10V

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the LM56 Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
(2) Soldering process must comply with Reflow Temperature Profile specifications. Refer to http://www.ti.com/packaging.
(3) Reflow temperature profiles are different for lead-free and non-lead-free packages.

Package Type JA
D0008A 110C/W
DGK0008A 250C/W

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LM56 Electrical Characteristics

The following specifications apply for V+ = 2.7 VDC, and VREF load current = 50 A unless otherwise specified. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25C unless otherwise specified.
LM56BIM LM56CIM
Symbol Parameter Conditions Typical (1) Units (Limits)
Limits (2) Limits (2)
Temperature Sensor
Trip Point Accuracy (Includes VREF, 2 3 C (max)
Comparator Offset, and Temperature
+25C TA +85C 2 3 C (max)
Sensitivity errors)
40C TA +125C 3 4 C (max)
Trip Point Hysteresis TA = 40C 4 3 3 C (min)
6 6 C (max)
TA = +25C 5 3.5 3.5 C (min)
6.5 6.5 C (max)
TA = +85C 6 4.5 4.5 C (min)
7.5 7.5 C (max)
TA = +125C 6 4 4 C (min)
8 8 C (max)
Internal Temperature Sensitivity +6.20 mV/C
Temperature Sensitivity Error 2 3 C (max)
3 4 C (max)
Output Impedance 1 A IL +40 A 1500 1500 (max)
Line Regulation +3.0V V+ +10V, 0.72/+0.3 0.72/+0.3 mV/V (max)
+25 C TA +85 C 6 6
+3.0V V+ +10V, 1.14/+0.6 1.14/+0.6 mV/V (max)
40 C TA <25 C 1 1
+2.7V V+ +3.3V 2.3 2.3 mV (max)
VT1 and VT2 Analog Inputs
IBIAS Analog Input Bias Current 150 300 300 nA (max)
VIN Analog Input Voltage Range V+ 1 V
GND V
VOS Comparator Offset 2 8 8 mV (max)
VREF Output
VREF VREF Nominal 1.250V V
VREF Error 1 1 % (max)
12.5 12.5 mV (max)
VREF/V+ Line Regulation +3.0V V+ +10V 0.13 0.25 0.25 mV/V (max)
+2.7V V+ +3.3V 0.15 1.1 1.1 mV (max)
VREF/IL Load Regulation Sourcing +30 A IL +50 A 0.15 0.15 mV/A (max)

(1) Typicals are at TJ = TA = 25C and represent most likely parametric norm.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

Symbol Parameter Conditions Typical (1) Limits (2) Units (Limits)

+
V Power Supply
IS Supply Current V+ = +10V 230 A (max)
+
V = +2.7V 230 A (max)
Digital Outputs
IOUT(1) Logical 1 Output Leakage Current V+ = +5.0V 1 A (max)
VOUT(0) Logical 0 Output Voltage IOUT = +50 A 0.4 V (max)

(1) Typicals are at TJ = TA = 25C and represent most likely parametric norm.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

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Typical Performance Characteristics

Quiescent Current VREF Output Voltage
vs vs
Temperature Load Current

Figure 2. Figure 3.

OUT1 and OUT2 Voltage Levels Trip Point Hysteresis

vs vs
Load Current Temperature

Figure 4. Figure 5.

Temperature Sensor Output Voltage Temperature Sensor Output Accuracy

vs vs
Temperature Temperature

Figure 6. Figure 7.

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Typical Performance Characteristics (continued)

Trip Point Accuracy Comparator Bias Current
vs vs
Temperature Temperature

Figure 8. Figure 9.

OUT1 and OUT2 Leakage Current VTEMP Output Line Regulation

vs vs
Temperature Temperature

Figure 10. Figure 11.

VREF Start-Up Response VTEMP Start-Up Response

Figure 12. Figure 13.

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FUNCTIONAL DESCRIPTION

Pin Functions
V+ This is the positive supply voltage pin. This pin should be bypassed with a 0.1 F capacitor to ground.
GND This is the ground pin.
VREF This is the 1.250V bandgap voltage reference output pin. In order to maintain trip point accuracy this pin
should source a 50 A load.
VTEMP This is the temperature sensor output pin.
OUT1 This is an open collector digital output. OUT1 is active LOW. It goes LOW when the temperature is greater
than T1 and goes HIGH when the temperature drops below T1 5C. This output is not intended to directly
drive a fan motor.
OUT2 This is an open collector digital output. OUT2 is active LOW. It goes LOW when the temperature is greater
than the T2 set point and goes HIGH when the temperature is less than T2 5C. This output is not intended to
directly drive a fan motor.
VT1 This is the input pin for the temperature trip point voltage for OUT1.
VT2 This is the input pin for the low temperature trip point voltage for OUT2.

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VT1 = 1.250V x (R1)/(R1 + R2 + R3)

VT2 = 1.250V x (R1 + R2)/(R1 + R2 + R3)
where:
(R1 + R2 + R3) = 27 k and
VT1 or T2 = [6.20 mV/C x T] + 395 mV therefore:
R1 = VT1/(1.25V) x 27 k
R2 = (VT2/(1.25V) x 27 k)R1
R3 = 27 k R1 R2

Application Hints

LM56 TRIP POINT ACCURACY SPECIFICATION

For simplicity the following is an analysis of the trip point accuracy using the single output configuration shown in
Figure 14 with a set point of 82C.
Trip Point Error Voltage = VTPE,
Comparator Offset Error for VT1E
Temperature Sensor Error = VTSE
Reference Output Error = VRE

Figure 14. Single Output Configuration

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1. VTPE = VT1E VTSE + VRE

Where:
2. VT1E = 8 mV (max)
3. VTSE = (6.20 mV/C) x (3C) = 18.6 mV
4. VRE = 1.250V x (0.01) R2/(R1 + R2)
Using Equations from Figure 1.
VT1= 1.25V x R2/(R1 + R2) = 6.20 mV/C)(82C) + 395 mV
Solving for R2/(R1 + R2) = 0.7227
then,
5. VRE = 1.250V x (0.01) R2/(R1 + R2) = (0.0125) x (0.7227) = 9.03 mV
The individual errors do not add algebraically because, the odds of all the errors being at their extremes are rare.
This is proven by the fact the specification for the trip point accuracy stated in the LM56 Electrical Characteristics
for the temperature range of 40C to +125C, for example, is specified at 3C for the LM56BIM. Note this trip
point error specification does not include any error introduced by the tolerance of the actual resistors used, nor
any error introduced by power supply variation.
If the resistors have a 0.5% tolerance, an additional error of 0.4C will be introduced. This error will increase to
0.8C when both external resistors have a 1% tolerance.

BIAS CURRENT EFFECT ON TRIP POINT ACCURACY

Bias current for the comparator inputs is 300 nA (max) each, over the specified temperature range and will not
introduce considerable error if the sum of the resistor values are kept to about 27 k as shown in the typical
application of Figure 1. This bias current of one comparator input will not flow if the temperature is well below the
trip point level. As the temperature approaches trip point level the bias current will start to flow into the resistor
network. When the temperature sensor output is equal to the trip point level the bias current will be 150 nA
(max). Once the temperature is well above the trip point level the bias current will be 300 nA (max). Therefore,
the first trip point will be affected by 150 nA of bias current. The leakage current is very small when the
comparator input transistor of the different pair is off (see Figure 15).
The effect of the bias current on the first trip point can be defined by the following equations:

(1)
where IB = 300 nA (the maximum specified error).
The effect of the bias current on the second trip point can be defined by the following equations:

(2)
where IB = 300 nA (the maximum specified error).
The closer the two trip points are to each other the more significant the error is. Worst case would be when VT1 =
VT2 = VREF/2.

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Figure 15. Simplified Schematic

MOUNTING CONSIDERATIONS
The majority of the temperature that the LM56 is measuring is the temperature of its leads. Therefore, when the
LM56 is placed on a printed circuit board, it is not sensing the temperature of the ambient air. It is actually
sensing the temperature difference of the air and the lands and printed circuit board that the leads are attached
to. The most accurate temperature sensing is obtained when the ambient temperature is equivalent to the
LM56's lead temperature.
As with any IC, the LM56 and accompanying wiring and circuits must be kept insulated and dry, to avoid leakage
and corrosion. This is especially true if the circuit operates at cold temperatures where condensation can occur.
Printed-circuit coatings are often used to ensure that moisture cannot corrode the LM56 or its connections.

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VREF AND VTEMP CAPACITIVE LOADING

Figure 16. Loading of VREF and VTEMP

The LM56 VREF and VTEMP outputs handle capacitive loading well. Without any special precautions, these outputs
can drive any capacitive load as shown in Figure 16.

NOISY ENVIRONMENTS
Over the specified temperature range the LM56 VTEMPoutput has a maximum output impedance of 1500. In an
extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is
recommended that 0.1 F be added from V+ to GND to bypass the power supply voltage, as shown in Figure 16.
In a noisy environment it may be necessary to add a capacitor from the VTEMP output to ground. A 1 F output
capacitor with the 1500 output impedance will form a 106 Hz lowpass filter. Since the thermal time constant of
the VTEMP output is much slower than the 9.4 ms time constant formed by the RC, the overall response time of
the VTEMP output will not be significantly affected. For much larger capacitors this additional time lag will increase
the overall response time of the LM56.

APPLICATIONS CIRCUITS

Figure 17. Reducing Errors Caused by Bias Current

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The circuit shown in Figure 17 will reduce the effective bias current error for VT2 as discussed in Section 3.0 to
be equivalent to the error term of VT1. For this circuit the effect of the bias current on the first trip point can be
defined by the following equations:

(3)
where IB = 300 nA (the maximum specified error).
Similarly, bias current affect on VT2 can be defined by:

(4)
where IB = 300 nA (the maximum specified error).
The current shown in Figure 18 is a simple overtemperature detector for power devices. In this example, an
audio power amplifier IC is bolted to a heat sink and an LM56 Celsius temperature sensor is mounted on a PC
board that is bolted to the heat sink near the power amplifier. To ensure that the sensing element is at the same
temperature as the heat sink, the sensor's leads are mounted to pads that have feed throughs to the back side of
the PC board. Since the LM56 is sensing the temperature of the actual PC board the back side of the PC board
also has large ground plane to help conduct the heat to the device. The comparator's output goes low if the heat
sink temperature rises above a threshold set by R1, R2, and the voltage reference. This fault detection output
from the comparator now can be used to turn on a cooling fan. The circuit as shown in design to turn the fan on
when heat sink temperature exceeds about 80C, and to turn the fan off when the heat sink temperature falls
below approximately 75C.

Figure 18. Audio Power Amplifier Overtemperature Detector

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Figure 19. Simple Thermostat

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REVISION HISTORY

Changes from Revision F (February 2013) to Revision G Page

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 PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

LM56BIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LM56

BIM
LM56BIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LM56
& no Sb/Br) BIM
LM56BIMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 125 T02B
LM56BIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 T02B
& no Sb/Br)
LM56BIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 T02B
& no Sb/Br)
LM56BIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 125 LM56
BIM
LM56BIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LM56
& no Sb/Br) BIM
LM56CIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 125 LM56
CIM
LM56CIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LM56
& no Sb/Br) CIM
LM56CIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 T02C
& no Sb/Br)
LM56CIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 T02C
& no Sb/Br)
LM56CIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 125 LM56
CIM
LM56CIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 LM56
& no Sb/Br) CIM

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 23-Aug-2017

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-May-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM56BIMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM56BIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM56BIMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM56BIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM56BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM56CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM56CIMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM56CIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM56CIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-May-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM56BIMM VSSOP DGK 8 1000 210.0 185.0 35.0
LM56BIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM56BIMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM56BIMX SOIC D 8 2500 367.0 367.0 35.0
LM56BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM56CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM56CIMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM56CIMX SOIC D 8 2500 367.0 367.0 35.0
LM56CIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
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