Chapter 5

Logic Built-In Self-Test

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 1
 What is this chapter about?

Introduce the basic concepts of logic BIST

BIST Design Rules

Test pattern generation and output response

analysis techniques

Fault Coverage Enhancement

Various BIST timing control diagrams

A Design Practice

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 2
 Introduction

What are the problems in todays
semiconductor testing?
 Traditional test techniques become quite
expensive
 No longer provide sufficiently high fault coverage

Why do we need built-in self-test (BIST)?
 For mission-critical applications
 Detect un-modeled faults
 Provide remote diagnosis

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 3
 BIST Techniques Categories

Online BIST
 Concurrent online BIST
 Non Concurrent online BIST

Offline BIST
 Functional offline BIST
 Structural offline BIST

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 4
 A General Form of Logic BIST
BIST

Offline Online
[Abramovici 1994]
Non-
Functional Structural Concurrent concurrent

Logic BIST Techniques

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 5
 A Typical Logic BIST System
Test Pattern Generator
(TPG)

Logic
BIST Circuit Under Test
Controller (CUT)

Output Response Analyzer

(ORA)

Structural off-line BIST

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 6
 BIST Design Rules
Logic BIST requires much more stringent design restrictions when
compared to conventional scan. Therefore, when designing a logic BIST
system, it is essential that the circuit under test meet all scan design rules
and BIST specific design rules, called BIST design rules.

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 7
 Typical X-bounding Methods

Methods for blocking an unknown (X) source

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 8
 X-bounding Methods
Depending on the nature of each unknown (X) source, several
X-bounding methods can be appropriate for use.

Common problems:
(1) Increase the area of the design.
(2) Impact timing.

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 9
 Typical Unknown Sources

Analog Blocks
 Adding bypass logic.
 Adding control-only scan point

Memories and Non-Scan Storage Elements
 Bypass logic
 Initialization

Combinational Feedback Loops
 Scan points

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 10
 Typical Unknown Sources (contd)

Asynchronous Set/Reset Signals
 using the existing scan enable (SE) signal to
protect each shift operation and adding a
set/reset clock point (SRCK) on each set/reset
signal to test the set/reset circuitry.

SRCK Set/Reset
Circuitry
SE

Functional
[Abdel-Hafez 2004]
0 R
Logic D Q
1
Scan-In CK

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 11
 Typical Unknown Sources (contd)

Asynchronous Set/Reset Signals

Shift Window Capture Window Shift Window Capture Window Shift Window
C1
CK
C2
SRCK

SE

Timing control diagram for testing data and set/reset faults

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 12
 Typical Unknown Sources (contd)

Tri-State Buses
 Re-synthesize each bus with multiplexers.
 One-hot decoder

A one-hot decoder for testing a tri-state bus with 2 drivers

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 13
 Typical Unknown Sources (contd)

False Paths
 0-control point
 1-control point

Critical Paths
 Adding an extra input pin to a selected
combinational gate on the critical path.

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 14
 Typical Unknown Sources (contd)

Multiple-Cycle Paths
 0-control point
 1-control point
 Holding certain scan cell output states

Floating Ports
 PI or PO must have a proper connection to Power
(Vcc) or Ground (Vss).
 Floating inputs to any internal modules must be
avoided.

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 15
 Typical Unknown Sources (contd)

Bi-directional I/O Ports
 Fix the direction of each bi-directional I/O port to
either input or output mode.

EN
SE D IO
BIST_mode Z

Forcing a bi-directional port to output mode

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 16
 Re-Timing
Races and hazards caused by clock skews may occur between the TPG
and the (scan chain) inputs of the CUT as well as between the (scan chain)
outputs of the CUT and the ORA. To avoid these potential problems and
ease physical implementation, we recommend adding re-timing logic
between the TPG and the CUT and between the CUT and the ORA.

T D Q D Q D Q D Q O
P R
G CUT A
CK CK CK CK

CK1 CK2 CK3

Re-timing logic among the TPG, CUT, and ORA

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 17
 Test Pattern Generation

Test pattern generators (TPGs) constructed
from linear feedback shift registers (LFSRs)

TPG
 Exhaustive testing
 Pseudo-random testing
 Pseudo-exhaustive testing

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 18
Standard LFSR

Consists of n D flip-flops and a
selected number of exclusive-OR
(XOR) gates

hn-1 hn-2 h2 h1
[Golomb 1982]
Si0 Si1 Sin-2 Sin-1

An n-stage (external-XOR) standard LFSR

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 19
Modular LFSR

Each XOR gate placed between two
adjacent D flip-flops

h1 h2 hn-2 hn-1

[Golomb 1982]
Si0 Si1 Sin-2 Sin-1

An n-stage (internal-XOR) modular LFSR

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 20
 LFSR Properties

The internal structure of the n-stage
LFSR can be described by a
characteristic polynomial of degree n,
f(x).

hi is either 1 or 0,depending on the feedback path

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 21
 LFSR Properties

Let Si represent the contents of the n-
th
stage LFSR after ii shifts of the initial
contents,S0,of the LFSR, and Si(x) be
the polynomial representation of Si

If T is the smallest positive integer such that f(x) divides 1 + xT ,then

the integer T is called the period of the LFSR.

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 22
 4-stage standard and modular LFSRs

4-stage Standard LFSR

4-stage Modular LFSR

f (x ) = 1 + x + x
2 4

f (x ) = 1 + x + x 4

s0 = x 3

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 23
 Hybrid LFSR
a ( x ) = 1 + b( x ) + c ( x )
Fully decomposable iff both b(x) and c(x) have no common terms
and there exists an integer j such that c ( x ) = x j b ( x ), j 1

Assume: f(x) is fully decomposable

f (x ) = 1 + b(x ) + x j b(x )

A (hybrid) top-bottom LFSR [Wang 1988a] can be constructed:

s (x ) = 1 + x j + x j b (x )
Indicate the XOR gate with one input
Is connected to the feedback path, not
between stages
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EE141 Ch. 5 - Logic BIST - P. 24
 5-stage hybrid LFSRs

(a) 5-stage top-bottom LFSR

(b) 5-stage bottom-top LFSR

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 25
 Primitive polynomials list
Primitive polynomials of degree n up to 100

Note: 24 4 3 1 0 means p ( x) = x 24 + x 4 + x 3 + x1 + x 0
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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 26
 Exhaustive Testing

Exhaustive Testing
 Applying 2 n exhaustive patterns to an n-input
combinational circuit under test (CUT)

Exhaustive pattern generator
 Binary counter
 Complete LFSR

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 27
 Binary counter

X4
X1 X2 X3

Example binary counter as EPG

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 28
 Complete LFSR
0 0 0 1 0 0 0 1

(a) 4-stage standard CFSR (b) 4-stage modular CFSR

0 0 0 1 1 0 0 0

(c) A minimized version of (a) (d) A minimized version of (b)

Example complete LFSRs as EPG

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 29
 Exhaustive Testing performance

Exhaustive Testing guarantees all
detectable, combinational faults will be
detected.

Test time maybe be prohibitively long if
input number is large than 20.

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 30
 Pseudo-Random Testing

Pseudo-random pattern generator

Reduce test length but sacrifice the fault
coverage

Difficult to determine the required test
length and fault coverage

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 31
 Pseudo-Random Testing

Maximum-length LFSR
 RP-resistant problem

Weighted LFSR

Cellular Automata

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 32
 Weighted LFSR

1 0 0 1

X4
X3
X2
X1

Example weighted LFSR as PRPG

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 33
 Cellular Automata

Provide more random test patterns

Provide high fault coverage in a random-
pattern resistant (RP-resistant) circuit

Implementation advantage

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 34
 Cellular Automata
A general structure of an n-stage CA

0
Cell Cell Cell Cell
0 1 n-2 n-1
0

Each rule determines the next state of a cell based on

the state of the cell and its neighbors

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 35
 Example cellular automaton
A 4-stage CA Test sequence
0001
0 0010
0111
1111
0 0011
X0 X1 X2 X3 0101
1000
1100
0110
1101
0100
1010
1011
1001
1110

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 36
 CA construction rules
Construction rules for cellular automata of length n up to 53

[Hortensius 1989]

*For n=7, Rule=152=001,101,010=1,101,010, where 0 denotes a rules 90 and

1 denotes a rule 150 cell, or vice versa

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 37
 Pseudo-Exhaustive Testing

Reduce test time while retaining many
advantages of exhaustive testing

Guarantee 100% single-stuck fault coverage

 Verification test technique [McCluskey 1984]

 Segmentation test technique [McCluskey 1981]

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 38
 Verification Testing
Divide the CUT into m cones, backtracing from each output to
determine the inputs that drive the output. Each cone will receive
exhaustive test patterns and are tested concurrently.
[McCluskey 1984]

Pseudo-exhaustive pattern generators

x1 x2 x3 x4
PEPGs

y1 y2 y3 y4

An (n, w)=(4, 2) CUT

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 39
 Syndrome Driver Counter
Use SDC to generate test patterns. Check whether some inputs
can share the same test signal. If n-p Inputs can share test inputs with
other p inputs, then the circuit can be tested exhaustively with these
p inputs.
[Savir 1980]

X1 X2 X3
A 3-stage syndrome
driver counter
X4

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 40
 Constant-Weight Counter
Use CWCs to generate test patterns. Constant-Weight counters
are constructed using constant-weight code or M-out-of-N code.
The constant-weight test set is a minimum-length test set for many
circuits.
[McCluskey 1982]

A 3-stage constant-weight
X1 X2 X3 counter

X4

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 41
 Combined LFSR/SR
Use a combination of an LFSR and a shift register (SR) for pattern
generation. The method is most effective when w is much less than n.
In general, this technique requires much more tests than other schemes
when w is greater than n/2.
[Barzilai 1983 ] [Tang 1984]

A 4-stage combined
X1 X2 X3 X4 LFSR/SR

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 42
 Combined LFSR/PS
A combined LFSR/PS approach using a combination of an LFSR
and a linear phase shifter which includes a network of XOR gates to
generate test pattern. Similar to combined LFSR/SR, this technique
requires more tests than other schemes when w is greater than n/2.

[Vasanthavada 1985]
X1 X2 X3

A 3-stage combined
X1 X2 X3
LFSR/PS

X4

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 43
 Condensed LFSR
Condensed LFSRs are constructed based on linear codes.
Define g(x) and p(x) as the generator polynomial and primitive
polynomial over GF(2), respectively. An (n, k) condensed LFSR
can be realized using
f ( x) = g ( x) p ( x) = (1 + x + x 2 + ... + x n k ) p ( x)
Where
w < [k / (n k + 1)] + [k /( n k + 1)]

[Wang 1986a]

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 44
 Example Condensed LFSR
A (4,3) condensed LFSR Test sequence

1100
0110
0011
1010
X1 X2 X3 X4
0101
1001
1111

Set

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 45
 Cyclic LFSR
Use cyclic LFSRs to reduce the test length when w < n/2.
A cyclic code always exists when n ' = 2b 1, b > 1
To exhaustively test any (n,w) CUT
 find a generator polynomial g(x) of largest degree k (or smallest
degree k), for generating an (n,k) = (n,n-k) cyclic code, that
divides 1+x^^n and has a design distance d > w+1;
 construct an (n,k) cyclic LFSR using f(x) = h(x)p(x) =
(1+x^^n)p(x)/g(x), where h(x) = (1+x^^n)/g(x); and
 shorten this (n,k) cyclic LFSR to an (n,k) cyclic LFSR by deleting
the rightmost, middle, or leftmost n-n stages from the (n,k) cyclic
LFSR.

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 46
 Example Cyclic LFSR
A (8,5) cyclic LFSR, picking the first 6 stages and the last two
stages of the (15,5) cyclic LFSR.

1 0 1 0 0 1 0 0

[Wang 1988b]
b,
An (n,k-s) shorted cyclic LFSR can be employed when n = 2 b > 2

1 0 1 0 1 0 1 0

[Wang 1987b]
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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 47
 Compatible LFSR
The combined LFSR of an l-stage LFSR and an l-to-n mapping logic,
called l-stage compatible LFSR, can further reduce the test length, when
only single stuck faults are considered.
X1
Y1
0 0
X2

X3

X4
Y2
X5
X1 X2 X3 X4 X5

(a) An (n,w) = (5,4) CUT (b) A 2-stage compatible LFSR

Example compatible LFSR as PEPG

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 48
 Segmentation Testing

Used when
 Test length using previous techniques is too long
or
 Output depends on all inputs.

Divide the circuit into segments
 Hardware partitioning
 Sensitized partitioning

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 49
 Delay Fault Testing

Need 2 n (2 n 1) patterns to test delay fault
exhaustively

Test set could cause test invalidation
when more than one inputs change.

TESTTYPE hn-1 hn-2 h2 h1

0

1
X1 X2 Xn-1 Xn
[Bushnell 2000]

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 50
 Output Response Analysis

Ones count testing

Transition count testing

Signature analysis

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 51
 Ones Count Testing
Assume the CUT has one output and the output contains a
stream of L bits. Let the fault-free output response be

{r0 , r1 , r2 L rL 1}

Ones count testing will need a counter to count the number of 1s

in the bit stream.

Aliasing probability [Savir 1985]

POC (m) = (C ( L, m) 1) /( 2 L 1)

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 52
 One Count Testing

T Signature
CUT
Counter

CLK

One counter as ORA

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 53
 Transition Count Testing
Transition count testing is similar to that for ones count testing,
except the signature is defined as the number of 1-to-0 and
0-to-1 transitions.
[Hayes 1976]

Aliasing probability

PTC (m) = (2C ( L 1, m) 1) /(2 L 1)

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 54
 Transition Count Testing

ri
ri-1
T CUT D Q Counter Signature

CLK

Transition counter as ORA

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 55
 Signature Analysis
Signature analysis is the most popular compaction technique
used today, based on cyclic redundancy checking.

Two signature analysis schemes

 Serial signature analysis
 Parallel signature analysis

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 56
 Serial Signature Analysis
An n-stage single-input signature register

h1 h2 hn-2 hn-1

M r0 r1 rn-2 rn-1

Define L-bit output sequence M

M ( x) = m0 + m1 x + m2 x + ... + mL 1 x L 1

Let the polynomial of the modular be f(x)

Signature is the
IF M ( x) = q ( x) f ( x) + r ( x)
polynomial remainder, r(x)

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 57
 Example
M

A 4-stage SISR
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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 58
 Parallel Signature Analysis
Multiple-input signature register (MISR)

h1 h2 hn-2 hn-1

r0 r1 rn-2 rn-1

M0 M1 M2 Mn-2 Mn-1

An n-input MISR can be remodeled as a single-input SISR with

effective input sequence M(x) and effective error polynomial E(x)

M ( x) = M 0 ( x) + xM 1 ( x) + ... + x n 2 M n 2 ( x) + x n 1M n 1 ( x)

E ( x) = E0 ( x) + xE1 ( x) + ... + x n 2 En 2 ( x) + x n 1 En 1 ( x)

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 59
 4-stage MISR

M0 1 0 0 1 0
M1 0 1 0 1 0
M2 1 1 0 0 0
M3
M0 M2 M3 1 0 0 1 1
M1
M 1 0 0 1 1 0 1 1

A 4-stage MISR An equivalent M sequence

Aliasing probability

PPSA (n) = (2( mL n ) 1) /(2 mL 1)

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 60
 Logic BIST Architectures
Four Types of BIST Architectures:

No special structure to the CUT

Make use of scan chains in the CUT

Configure the scan chains for test pattern
generation and output response analysis

Use concurrent checking circuitry of the
design

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VLSI Test Principles and Architectures
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 Type I - Centralized and Separate
Board-Level BIST (CSBL)
Two LFSRs and two multiplexers are added to the circuit.
The first LFSR acts as a PRPG, the second serves as a SISR.
The first multiplexer selects the inputs, another routes the PO to
the SISR.
[Benowitz 1975]

n
PIs M n m
CUT POs
n U
X (C or S)
CSBL Architecture
PRPG 1 MUX SISR
k 1
k = [log2m]
TEST

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 62
 Type I - Built-In Evaluation and Self-
Test (BEST)
Use a PRPG and a MISR. Pseudo-random patterns are applied in
parallel from the PRPG to the chip primary inputs (PIs) and a MISR is
used to compact the chip output responses .
[Perkins 1980]

P M
R CUT I BEST Architecture
PIs P S POs
(C or S)
G R

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 63
 Type II - LSSD On-Chip Self-Test
(LOCST)
In addition to the internal scan chain, an external scan chain
comprising all primary inputs and primary outputs is required. The
External scan-chain input is connected to the scan-out point of the
internal scan chain.
[Eichelberger 1983]

Sin PRPG SISR Sout

R1 R2

CUT LOCST Architecture

PIs (C) POs
Si So
SRL SRL

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 64
 Type II - Self-Testing Using MISR and Parallel
SRSG (STUMPS)
Contains a PRPG (SRSG) and a MISR. The scan chains are
loaded in parallel from the PRPG. The system clocks are then pulsed
and the test responses are scanned out to the MISR for compaction.
New test patterns are scanned in at the same time when the test
responses are being scanned out.
[Bardell 1982]

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VLSI Test Principles and Architectures
EE141 Ch. 5 - Logic BIST - P. 65
 STUMPS

PRPG PRPG

Linear Phase Shifter

CUT

(C or S)
CUT

(C or S)
MISR

Linear Phase Compactor

MISR

STUMPS A STUMPS-based Architecture

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VLSI Test Principles and Architectures
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 Type III - Built-In Logic Block Observer
(BILBO)
The architecture applies to circuits that can be partitioned into
independent modules (logic blocks). Each module is assumed to have
its own input and output registers (storage elements), or such registers
are added to the circuit where necessary. The registers are redesigned
so that for test purposes they act as PRPGs or MISRs.

[Konemann 1980]

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 Built-In Logic Block Observer

Y0 Y1 Y2
B2
B1

0
D Q D Q D Q
1

Scan-In SCK X0 X1 Scan-Out/X2

A 3-stage BILBO

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VLSI Test Principles and Architectures
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 Type III - Concurrent Built-In Logic Block
Observer (CBILBO)

Y0 Y1 Y2

B1

Scan-Out
0
D Q D Q D Q
1

1 1D
2D Q
1D
2D Q
1D
2D Q
[Wang 1986c]
0 SEL SEL SEL

Scan-In B2 SCK X X1 X2
0

A 3-stage concurrent BILBO (CBILBO)

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VLSI Test Principles and Architectures
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 Type III - Circular Self-Test Path (CSTP)
All primary inputs and primary outputs are reconfigured as external
scan cells. They are connected to the internal scan cells to form a circular
path. During self-test, all primary inputs (PIs) are connected as a shift
register (SR), whereas all internal scan cells and primary outputs (POs)
are reconfigured as a MISR.
[Krasniewsk 1989]

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 Circular Self-Test Path
PIs
CIRCULATE
Sin 0
SR MISR
1 TEST

Yi 0
CUT Xi
(C) D Q
1
Xi-1
Sout MISR MISR CLK

POs

(a) The CSTP architecture (b) Self-Test cell

CSTP architecture
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 Type IV - Concurrent Self-Verification (CSV)
PRPG
n

Functional Circuitry Duplicate Circuitry

m m

Checking Circuitry

two-rail checker

CSV Architecture

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EE141 Ch. 5 - Logic BIST - P. 72
 Summary

B: board-level testing
C: combinational circuit
S: sequential circuit

Representative Logic BIST Architectures

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 Fault Coverage Enhancement
Three approaches to enhance the fault coverage

Test point insertion

Mixed-mode BIST

Hybrid BIST

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 Test Point Insertion
Two typical types of test points

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 Test Point Insertion Example
An example where one control point and one observation
point are inserted to increase the detection probability of a
6-input AND-gate.

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 Test Point Placement
Where to place the test points in the circuit to maximize the
coverage and minimize the number of test points required.

Fault simulation guided techniques

Testability measure guided techniques

Timing-driven test point insertion techniques

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 Control Point Activation
During normal operation, all control points must be
deactivated. During testing, there are different strategies
as to when and how the control points are activated.

Random activation

Deterministic activation

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 Mixed-Mode BIST
Mixed-mode BIST is an alternative way to improve fault
coverage without modifying the CUT.
Pseudo-random patterns are generated to detect the RP-
testable faults, and then some additional deterministic
patterns are generated to detect the RP-resistant faults.

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VLSI Test Principles and Architectures
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 Mixed-Mode BIST
Approaches for generating deterministic patterns on-chip:

ROM Compression.

LFSR Reseeding.

Embedding Deterministic Patterns.
..
Decoding
Logic

LFSR Scan Chain
LFSR

Poly. Id Seeds Bit-Flipping
Function

Reseeding with multiple- Bit-flipping BIST

polynomial LFSR
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 Hybrid BIST
For manufacturing fault coverage enhancement where a
tester is present, deterministic data from the tester can be
used to improve the fault coverage.

Top-up ATPG

Store the compressed deterministic patterns
on the tester

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 BIST Timing Control

To test Multiple-clock-domain circuits

To detect Intra-clock-domain faults and
inter-clock-domain faults

Capture-clocking schemes
 Single-capture
 Skewed-load
 Double-capture

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 One-Hot Single-Capture
A capture pulse is applied to one clock domain, while holding all
other test clocks inactive, during each capture window.

Benefit: a single and slow global scan mode signal

Drawback: long test time

Shift Window Capture Window Shift Window Capture Window Shift Window

C1
CK1
d1 d2
C2
CK2

GSE

One-hot single-capture
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 Staggered Single-Capture
Shift Window Capture Window Shift Window
C1

CK1
d1 d2 d3
Staggered single-capture
C2

CK2

GSE

Benefits: short test time; a single and slow global scan mode signal
Drawback: some structural fault coverage loss

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 Skewed-Load

An at-speed delay test technique

Address intra-clock-domain delay faults

Three approaches
 One-hot skewed-load
 Aligned skewed-load
 Staggered skewed-load

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 One-Hot Skewed-Load
Tests all clock domains one by one by applying a-shift-followed
by-a-capture pulses to detect intra-clock-domain delay faults.

Drawbacks:
(1) Cannot detect inter-clock-domain delay faults
(2) Test time is long
(3) Single and global scan enable (GSE) signal can no longer be used

Shift Window Capture Window Shift Window Capture Window Shift Window

S1 C1
CK1
d1
SE1
S2 C2
CK2
d2
SE2

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 Aligned Skewed-Load

Solve the long test time problem

Test all intra-clock-domain and inter-
clock-domain faults

Need complex timing-control

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 Aligned Skewed-Load
S1 C S
S2
S3 Capture Window
C1 S1

CK1 CK1

SE1 SE1
C2

CK2 CK2

SE2 SE2
C3

CK3 CK3

SE3
SE3

Capture aligned skewed-load Launch aligned skewed-load

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 Staggered Skewed-Load
When two test clocks cannot be aligned precisely, we can simply
insert a proper delay to eliminate the clock skew. The two last shift
pulses are used to create transitions and their output responses are
caught by the next two capture.

Drawback: Need at-speed scan enable signal for each clock domain

Shift Window Capture Window Shift Window

S1 C1
CK1
d1 Staggered skewed-load
SE1
d3
S2 C2
CK2
d2
SE2

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 Double Capture

Solve the physical implementation
difficulty using skewed-load

True at-speed test

Double-capture benefits
 Detect intra-clock-domain faults and inter-clock-domain
structural faults or delay faults at-speed
 Facilitate physical implementation
 Ease integration with ATPG

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 One-Hot Double-Capture
Test all clock domains one by one by applying two consecutive
capture pulses at their respective domains frequencies to test
intra-clock-domain delay faults.

Benefit: true at-speed testing of intra-clock-domain delay faults

Drawbacks: (1) Cannot detect inter-clock-domain delay faults
(2) Test time is long

Shift Window Capture Window Shift Window Capture Window Shift Window
C1 C2
CK1
d1
C3 C4
One-Hot double-capture
CK2
d2
GSE

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 Aligned Double-Capture
C1 C
C2 C
C3 Capture Window
C1 C4

CK1 CK1
C2

CK2 CK2
C3

CK3
CK3
GSE
GSE

Aligned double-capture - I Aligned double-capture - II

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 Staggered Double-Capture
In the capture window, two capture pulses are generated for each
clock domain. The first two capture pulses are used to create transitions
at the outputs of scan cells, and the output responses to the transitions
are caught by the next two capture pulses, respectively.

Shift Window Capture Window Shift Window

C1 C2
CK1
d1 d2 d3 d4 d5
Staggered double-capture
C3 C4
CK2

GSE

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 Fault Detection

Intra-clock-domain delay fault detection is relatively
easy.

Testing inter-clock-domain delay faults is more
complex.

A single capture yields the highest fault coverage of
inter-clock-domain delay faults.

Shift Window Capture Window Shift Window

C1
CK1
d
C2
CK2
GSE

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 Fault Detection Capability

Note: A hybrid double-capture scheme using staggered

double-capture and aligned double-capture seems to be the
preferred scheme for true at-speed testing

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 A Design Practice
An example of designing a logic BIST system for testing a scan-based
design (core) comprising two clock domains using s38417 and s38584.
The two clock domains are taken from the ISCAS-1989 benchmark
circuits [Brglez 1989].

Design statistics

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 Design flow

BIST Rule Checking and Violation Repair

Logic BIST System Design

RTL BIST Synthesis

Design Verification and Fault Coverage
Enhancement

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 BIST Rule Checking and Violation Repair
All DFT rule violations of the scan design rules and BIST-specific design
rules must be repaired. In addition, we should be aware of the following
design parameters:

The number of test clocks present in the design

The number of set/reset clocks present in the design

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 Logic BIST System Design
The second step is to design the logic BIST system at the RTL,
including:

The type of logic BIST architecture to adopt

The number of PRPG-MISR (or PEPG-MISR) pairs to use

The length of each PRPG-MISR (or PEPG-MISR) pair

The faults to be tested and BIST timing control diagrams to be
used

The types of optional logic to be added

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 Logic BIST Architecture
We choose to implement a STUMPS-based architecture, since it is easy
to integrate with scan/ATPG and is the industry widely used architecture.

Logic BIST Controller TPG

PRPG1 PRPG2
SCK1 PLL
SCK2 CK1
CK2 PS1/SpE1 PS2/SpE2

Data/
Input Selector PIs/ SIs
Control

Start CCK1 Clock TCK1 Clock Clock

Test CCK2 Gating
Finish TCK 2 Domain C Domain
Controller
Block
POs/ SOs
Result CD1 CD2
BIST-Ready Core

SpC1 SpC2

MISR1 MISR2
ORA

A logic BIST system for testing a design with 2 cores

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 TPG and ORA
Next, we need to determine the length of each PRPG-MISR pair. Using a
separate PRPG-MISR pair for each clock domain allows us to reduce the
Length of each PRPG and MISR.

PRPG-MISR Choices

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 Test Controller
The test controller plays a central role in coordinating the overall BIST
operation. Often, external signals are controlled through an IEEE 1149.1
Boundary-Scan Standard based test access port (TAP) controller.

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 Test Controller (cont)
In order to test structural faults in the BIST-ready core, we choose the
Staggered single-capture approach.

Shift Window Capture Window Shift Window

C1
TCK1
C2
TCK2
GSE

Slow-speed timing control using staggered single-capture

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 Test Controller (cont)
In order to test delay faults in the BIST-ready core, we choose the
Staggered double-capture approach if CD1 and CD2 are asynchronous,
or the aligned double-capture approach if they are synchronous.

Shift Window Capture Window Shift Window Shift Window Capture Window Shift Window
C 1 C2 C1 C2
TCK1 TCK1
d
C3 C 4 C3 C4
TCK2
TCK2
GSE
GSE

Staggered double-capture Aligned double-capture

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 Clock Gating Block
In order to generate an ordered sequence of single-capture or
double-capture clocks, clock suppression [Rajski 2003] [Wang 2004],
daisy-chain clock-triggering, or token-ring clock-enabling [Wang 2005a]
can be used.

GSE
C1 C2

TCK1
d C3 C4

TCK2

Daisy-chain clock-triggering

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 Clock Gating Block (cont)
SE1
BIST SE1 2-Pulse TCK1
mode Generator Controller
CK1
CK1
SE2
SE2 2-Pulse
TCK2
Generator Controller
CK2
CK2

A daisy-chain clock-triggering circuit

0
0 0 1 1 TCK1
CK1
CK1
GSE 0
BIST GSE 1 1 1 1 TCK2
CK1
mode Generator
CK2

A clock suppression circuit

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 Re-Timing Logic
we recommend adding two pipelining registers between each PRPG and
the BIST-ready core, and two additional pipelining registers between the
BIST-ready core and each MISR. In this case, the maximum scan chain
length for each clock domain,CD1 or CD2, is effectively increased by 2,
not 4.

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 Fault Coverage Enhancing Logic and
Diagnostic Logic
In order to improve the circuits fault coverage, we recommend adding
extra test points and additional logic for top-up ATPG support at the RTL.

We also recommend including diagnostic logic in the RTL BIST code to

facilitate debug and diagnosis.

Example test modes to be supported by

the logic BIST system
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 RTL BIST Synthesis
At this stage, it is possible to either design the logic BIST system by hand
or generate the RTL code automatically using a (commercially available)
RTL logic BIST tool.

In either case, the number of scan chains for each clock domain should
be specified along with the names of their associated scan inputs (SIs)
and scan outputs (SOs) without inserting the actual scan chains into the
circuit.

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 Design Verification and Fault Coverage
Enhancement
Finally, the synthesized netlist needs to be verified with functional and/or
Timing verification.

Next, fault simulation needs to be performed on the pseudo-random

Patterns generated by the TPG in order to determine the circuits
fault coverage.
Test Point Selection at RTL Design

Logic/Scan Synthesis
Fault simulation and test
Fault Simulation point insertion flow

Gate-Level Test No Coverage

Point Insertion Acceptable ?
Yes
Done
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 Concluding Remarks

STUMPS is an industry widely adopted logic
BIST architecture, but hits problems due to
low fault coverage.

Some challenges ahead
 Whether the CBILBO-based architecture proposed by Wang
and McCluskey would perform as it always guarantee 100%
single stuck-fault coverage.
 Whether pseudo-exhaustive testing would become the
preferred BIST technique.

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