1.

BJT is a Bipolar Junction Transistor, while MOSFET is a Metal Oxide

Semiconductor Field-Effect Transistor.

2. A BJT has an emitter, collector and base, while a MOSFET has a gate, source
and drain.

3. BJTs are preferred for low current applications, while MOSFETs are for high
power functions.

4. In digital and analog circuits, MOSFETs are considered to be more commonly

used than BJTs these days.

5. The operation of MOSFET depends on the voltage at the oxide-insulated gate

electrode, while the operation of BJT is dependent on the current at the base.

Read more: Difference Between BJT and MOSFET | Difference

Between http://www.differencebetween.net/technology/difference-between-bjt-
and-mosfet/        
Next: 7.3 6T SRAM Cell Up: 7. Case Studies Previous: 7.1 Power MOS
Devices 

Subsections

 7.2.1 Voltage Transfer Characteristics

 7.2.2 Steady State Degradation
 7.2.3 Transient Behavior

7.2 CMOS Inverter

For the investigation of circuit-level degradation a CMOS (complementary

MOS) inverter is analyzed. A major advantage of CMOS technology is the
ability to easily combine complementary transistors, n-channel and p-channel,
on a single substrate. The CMOS inverter consists of the two transistor types
which are processed and connected, as seen schematically in Figure 7.10.

Figure 7.10: Schematic of a CMOS inverter as processed on a p-type silicon

substrate. The effect of NBTI mainly impacts the p-channel MOSFET (right hand
side transistor).

The p-channel MOSFET relies on an n-type substrate. As commonly p-type

wafers are used for processing, an additional n-type well implant is necessary.
In this well, which is a deep region of n-type doping, the p-channel MOSFET
is placed. As the p-substrate and the n-well junction is reverse biased, no
significant current flows between these regions and the two transistors are
isolated.

The output current of the p-channel MOSFET is typically much lower than the
current of an n-channel MOSFET with similar dimensions and dopings. This is
due to the lower carrier mobility of holes compared to electrons. As the
characteristics of the complementary transistors should be as equal as
possible, the width of the p-channel MOSFET is typically made larger to
compensate the difference. In our example device the necessary geometry
factor is   to obtain equal drain currents for equal gate biases.
 Figure 7.11: Schematic of a CMOS inverter circuit. In the stationary case the
circuit does not consume any power when assuming perfect devices without

leakage current. NBT stress is imposed on the p-channel device at .

Figure 7.11 gives the schematic of the CMOS inverter circuit. It can be seen

that the gates are at the same bias   which means that they are always in a

complementary state. When  is high,  , the voltage between gate

and substrate of the nMOS transistor is also approximately   and the

transistor is in on-state. The gate-substrate bias at the pMOS on the other

side is nearly zero and the transistor is turned off. The output voltage   is
pulled to ground, which is the low state. When the input voltage is in a high-
state, the complementary situation occurs and the pMOSFET is turned on

while the nMOSFET is turned off. The output voltage is therefore pulled to   
which is the high-state. It is important to note that in both states, high and low,
no static current flows through the inverter. This is of course only valid when
assuming ideal devices with zero off- and leakage-currents.
Considering negative bias temperature instability, the worst stress conditions
are imposed on the p-channel MOSFET at  . At this bias condition
the pMOSFET is turned on, with approximately the same potential at the
source and the drain   and negative gate to substrate
voltage  .

7.2.1 Voltage Transfer Characteristics

The voltage transfer characteristic (VTC) gives the response of the inverter

circuit,  , to specific input voltages,  . It is a figure of merit for the static

behavior of the inverter.

The gate-source voltage   of the n-channel MOSFET is equal to   while
the gate-source voltage of the p-channel MOSFET calculates as 

(7.1
)

and the drain-source voltage   of the pMOSFET can be expressed as 

(7.2
)

Looking at the output characteristics of the two transistors (Figure 7.12), and

considering that the drain currents,  , of both transistors must be equal, the
voltage transfer characteristic can be extracted, as seen on Figure 7.13. From
this figure it is obvious that a shift of the output characteristics of one
transistor can have big impact especially around the turn-over point of the
VTC.
n-channel MOSFET 

p-channel MOSFET 
Figure 7.12: Output characteristics of both transistors up to  V. The

resulting drain currents in the inverter circuit must be equal for each  .

Figure 7.13: Extraction of the voltage transfer characteristics of a CMOS inverter.

The drain currents of both transistors must be equal. Therefore, the intersection

of the output characteristics of both transistors for each input voltage   give the

output voltage  . The circles mark five points of the voltage transfer
characteristics.

The mixed-mode of Minimos-NT allows to simulate the whole circuit while the
device characteristics for each device are solved using the semiconductor
device equations. Thus, the degradation of the p-channel MOSFET due to
negative bias temperature instability can be accounted for in the circuit
simulation.

7.2.2 Steady State Degradation

 Figure 7.14: Voltage transfer characteristics of the CMOS inverter without

degradation. The transition from  to   is symmetric and very

well centered around  .

The voltage transfer characteristics of the unstressed inverter can be seen in

Figure 7.14. The transition from the on to the off state is very well aligned

around  .

NBT stress has its highest impact on the p-channel MOSFET during low
input  . At this condition the transistor has a gate to substrate voltage
of approximately  . When the circuit is additionally subject to thermal
stress, then the threshold voltage of the p-channel transistor is degraded. As
the n-channel device has a much lower susceptibility to this type of stress
(Section 6.3.7), the circuit loses its symmetry. As shown in Figure 7.15, is the
switching point of the output potential moved to a lower input voltage. An

interface trap density  , which is already a severely damaged

interface (Chapter 3), reduces the switching point by more than 1V.
 Figure 7.15: Degrading voltage transfer characteristics due to NBTI. Only the
threshold voltage of the p-channel MOSFET shifts. The CMOS inverter does not
switch symmetrically anymore and the switching point shifts to lower input

voltages  .

7.2.3 Transient Behavior

Figure 7.16: Transient switching-on behavior of the CMOS inverter. Because of
the threshold voltage shift of the p-channel device, the degraded circuit needs

more time to reach  .

Figure 7.17: Transient switching-off behavior of the CMOS inverter. When

switching the input from low to high state, the degraded circuit even outperforms
 the fresh circuit. This is due to the p-channel device turning off at lower gate
voltage as the threshold voltage is shifted to a more negative voltage.

Not only in the stationary case does the degradation influence the circuit
performance. Transient simulations show (Figure 7.16 and 7.17) that the
switching behavior of a circuit comprising a degraded p-channel MOSFET is
different. This must be kept in mind when designing timing-critical CMOS
circuits.

At high input,  , the p-channel MOSFET is turned off and the n-

channel device turned on, pulling the output voltage to ground,  .
Switching to  turns off the n-channel device and on the p-channel
device. The switching speed depends on the magnitude of the gate
overdrive,  . An NBT degraded pMOS transistor has a lower (more
negative) threshold voltage, therefore a lower gate overdrive and is turned on
slower. The result is a slower CMOS inverter when turning the
output  , as seen in Figure 7.16.

The opposite case, turning the inverter from   to   is

completely different, as seen in Figure 7.17. Here, the p-channel transistor is
switched from on to off. In this case the gate overdrive equals the magnitude
of the threshold voltage. The degraded device, with its more negative   is
driven into stronger inversion and can, thus, be turned off more quickly.

       
Next: 7.3 6T SRAM Cell Up: 7. Case Studies Previous: 7.1 Power MOS
Devices

R. Entner: Modeling and Simulation of Negative Bias Temperature Instability

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