FPGA implementation

of a Digital System
involved in a human
temperature
measuring device

Design features:
1. Storing capability of eight
temperature readings and corresponding
time.
2. Programmable alarm for intimating the
user to take the temp reading.
3. Programmable timer which display the
real time.

HDL USED:Verilog HDL

FPGA :Xilinx SPARTAN 2
PIN DETAILS

Din[7:0]

sysclk D
I Yout[7:0]
reset
G
ret0 I
ret1 T En[3:0]

A
set
L
rwm One Hz

live T
H
autos Alarm_led
E
Ti/temp R
s0 M sc1
O
s1
M
s2 E sc0

s3 T
E
s4 Led_auto
R
s5

s6
 Direction Pin Assignment on FPGA Functional Description
Name

Din [7:0] Input s0,s1,s2,s3,s4,s5,s6,s7 Temparature Data in digital

form
System Input p15 6MHz Board Clock
Clock
p19 On board pin which is used for
Reset Input the reset the time .

Ret0,ret1 Input p10,p11 Return lines from the Key pad

Sc0,sc1 Output p13,p20 Scan lines for key board

Every one minute, device will

Auto Input s9 sample the temp data and
switch corresponding time .Also
device switches the display in
every 5sec between temp and
time.

Ti/temp Input s10 Display permanently settles to

time mode or temp .
Set Input s11 For setting the current time ,
changing the memory location .
Rwm Input s12 Select the read or write
operation by using the key
buttons
Enable the reading and writing
live Input s13 operation at clock speed
(6MHz).
Read/Write to alarm
S0 Input L9 memory.0>Read;
1>Write.
S1,s2,s3 Input L10,L11,L12 Address to the alarm memory

Mode select for Alarm . modes

S4,s5,s6 Input L13,L14,L15 will enable the user to use
alarm at different times in a
day. For example user can set
parallelly 8 alarm times, or
any no: below 8 in a day.
Led _auto Output L1 In auto (sampling of data at
one minute interval),led glows
for one second at the time of
writing the new value.
Alarm_led Output L4 Alarm is indicated by glowing
of this LED.
One_Hz Output L8 LED showing the 1 Hz
variation.
En[3:0] Output P7,p6,p4,p3 Enable lines for the 4 seven
seg LEDs
Yout Output P22,p23,p26,p27 Data out to display.
[7:0] ,p29,p40,p42,p43
Assumptions taken:

Digital Data representing the measured human temperature is

readily available at the input of the Digital System.
Crystal clock frequency available on the board is 6MHz and
stable.

Coding and Logic Circuit Diagrams: Each module and

their codes are described below.

Top Module:

module dtm
(Din,sysclk,resetn,onehtz,ret0,ret1,sc0,sc1,set,rwm,live,autos,autoled,titemp,En,Yout,s0,s1,
s2,s3,s4,s5,s6,aled);
input sysclk,resetn,ret0,ret1,rwm,live,autos,titemp,set,s0,s1,s2,s3,s4,s5,s6;
input [7:0]Din;
output onehtz,sc0,sc1,autoled,aled;
output [3:0] En;
wire[2:0]add;
output [7:0]Yout;
wire [15:0] H,out16,In;
wire [7:0] out8;
wire [11:0]B;
wire [15:0]U;
wire ret0t,ret1t,ret0a,ret1rw,rd,wr,autoled,auto,b,onehtz,sw,tt;

timer cas0 (resetn,ret0t,ret1t,sysclk,sc0,sc1,b,H);

memory16 cas1 (H,add,rd,wr,out16,sysclk);
memory8 cas2 (Din,sysclk,rd,wr,add,out8);
ssdd cas3 (In,Yout,sysclk,En);
mux_time_temp cas4 (U,out16,tt,In);
bbc8 cas5 (out8,B);
countermt cas6 (ret0a,add);
demux0 cas7 (ret0,ret1,ret0t,ret1t,ret0a,ret1rw,set);
demux1 cas8 (rwm,ret1rw,live,rd,wr,auto);
countermtime cas9 (b,autos,auto);
autodsplyshft cas10 (b,autos,sw);
or cas11 (tt,sw,titemp);
alarm cas12 (H,sysclk,s0,s1,s2,s3,s4,s5,s6,aled);

assign autoled=auto;
assign U={1'b0,add,B};
assign onehtz=b;
endmodule
TIMER

module timer(resetn,ret0,ret1,sysclk,scan0,scan1,b,H);
input resetn,sysclk,ret0,ret1;
output [15:0]H;
output b,scan0,scan1;
wire[7:0]min;
wire[7:0]hrs;
wire b;
wire un1,un2,un3,pro;
wire [3:0] TENS1,ONES1,TENS0,ONES0;
wire [15:0] H;

clockdividert cas1 (sysclk,pro,b);

mhg cas2 (un3,resetn,hrs,min);
setter cas6 (un1,un2,pro,ret0,ret1,un3);
setclk cas7 (sysclk,scan0,scan1,un1);
bcdconv cas8 (hrs,TENS1,ONES1);
bcdconv cas9 (min,TENS0,ONES0);

assign un2=scan0;
assign H={TENS1,ONES1,TENS0,ONES0};
endmodule
 Clock_divider(timer)

1minute pulse

Divide 1Hz Divide

System
Clock
by 6M by 60
6MHz

One Hz

module clockdividert (clock,omco,oso);

input clock ;
output omco,oso;

div11 abc1 (clock,oso);

div12 abc2 (oso,omco);
endmodule

module div11(cl1,out1);
input cl1;
output out1;
reg out1;
integer n;
always@(posedge cl1)
begin
n <= n+1;
if(n<3000000)
out1 = 1;
else if (n<6000000)
out1 =0;
else
n <=0;
end
endmodule

module div12 (cl2,out2);

input cl2;
output out2;
reg out2;
integer no;

always@(posedge cl2)
begin
no <= no+1;
if(no<30)
out2 = 1;
else if (no<60)
out2 =0;
else
no <=0;
end
endmodule
//time dividers for setting the time( Time set clock dividers)

module setclk (syclk,sc0,sc1,hshr);

input syclk;
output sc0,sc1,hshr;
wire sc0,sc1,hshr;
wire y;
dividr1 ab1 (syclk,hshr);
dividr2 ab2 (hshr,y);
assign sc1=y;
assign sc0=!y;
endmodule

module dividr1 (clkk,yy);

input clkk;
output yy;
integer n;
reg yy;
always@(posedge clkk)
begin
n<=n+1;
if (n<30000)
yy=1;
else if (n<60000)
yy=0;
else
n<=0;
end
endmodule
module dividr2 (ckk,xy);
input ckk;
output xy;
integer n;
reg xy;
always@(posedge ckk)
begin
n<=n+1;
if (n<50)
xy=1;
else if (n<100)
xy=0;
else
n<=0;
end
endmodule
Time set clock router

module setter (in300,in5,mi1,aa,ab,outm);

input in300,in5,mi1,aa,ab;
output outm;
wire ac1,ac2,ac3;
assign ac1=aa;

xor x (ac2,aa,ab);
muxes mu1 (in5,in300,ac1,ac3);
muxes mu2 (mi1,ac3,ac2,outm);
endmodule

module muxes (in1,in2,mct,xout);

input in1,in2,mct;
output xout;
reg xout;
always@(mct)
begin
case (mct)
0:xout=in1;
1:xout=in2;
endcase
end
endmodule
 HOUR AND MINUTE GENERATOR

module mhg(clkin,reset,HR,MN);
input clkin,reset;
output [7:0]HR,MN;
wire cn;

hrblock abc4 (cn,reset,HR);

mnblock abc5 (clkin,reset,cn,MN);
endmodule

module hrblock (clkh,reseth,HRO);

input clkh,reseth;
output[7:0]HRO;
reg[7:0]HRO;

always@(posedge clkh or posedge reseth )

begin
if(reseth)
HRO <= 0;
else if(HRO<23)
HRO<=HRO+1;
else
HRO<=0;
end
endmodule

module mnblock (clkm,resetm,ohr,MNO);

input clkm,resetm;
output[7:0]MNO;
output ohr;
reg [7:0]MNO;
reg ohr;

always@ (posedge clkm or posedge resetm)

begin
if(resetm)
MNO <= 0;
else if (MNO<59)
 begin
MNO <= MNO + 1;
ohr<=0;
end
else
begin
ohr<=1;
MNO<=0;
end
end
endmodule

//binary to bcd conversion//A special algorithm called “add-3 shift” is used

here for the conversion of binary to BCD
(taken from internet)

C is a combinational circuit which will generate the output as per the

input values. If the input is more than or equal to 5 ,the logic will
add 3 to the input and sum will be the output otherwise(Input<5)output
will be the same input. Let us try one example.
module bcdconv (B,TENS,ONES);
input[7:0]B;
output[3:0]ONES;
output[3:0]TENS;
wire [3:0]c1,c2,c3;
wire [3:0]d1,d2,d3;

assign d1 = {B[6:3]};
assign d2 = {c1[2:0],B[2]};
assign d3 = {c2[2:0],B[1]};

add3t C1 (d1,c1);
add3t C2 (d2,c2);
add3t C3 (d3,c3);

assign ONES = { c3[2:0],B[0]};

assign TENS = { B[7],c1[3],c2[3],c3[3]};
endmodule

module add3t (AI,BI);

input[3:0]AI;
output[3:0]BI;
reg[3:0]BI;

always@(AI)
begin
case(AI)
0:BI = 4'b0000;
1:BI = 4'b0001;
2:BI = 4'b0010;
3:BI = 4'b0011;
4:BI = 4'b0100;
5:BI = 4'b1000;
6:BI = 4'b1001;
7:BI = 4'b1010;
8:BI = 4'b1011;
9:BI = 4'b1100;
default:BI=4'b0000;
endcase
end
endmodule
 Memory Module

Two different memory modules are used in the design

1.RAM 8*8 –for storing the 8 bit temp data.
2.RAM 8*16-for storing the time.
Structures used in the memory are same. Also in design,
both memories using the same address lines and control
signals rd and wr.

MEMORY 8*8

module memory8 (Din,clk,rd,wr,ad,Yout);

input clk,rd,wr;
input [7:0]Din;
input [2:0] ad;
output [7:0]Yout;
wire [7:0] al;
decoder1 cas0 (ad,al);
ram cas1 (al,wr,rd,clk,Din,Yout);
endmodule

module decoder1 (ad,al);

input [2:0]ad;
output[7:0]al;
reg [7:0]al;
always@(ad)
begin
case(ad)
0:al=8'b00000001;
1:al=8'b00000010;
2:al=8'b00000100;
3:al=8'b00001000;
4:al=8'b00010000;
5:al=8'b00100000;
6:al=8'b01000000;
7:al=8'b10000000;
endcase
end
endmodule

module ram (al,wr,rd,clk,Din,Yout);

input wr,rd,clk;
wire un2;
input [7:0] al;
input[7:0]Din;
output[7:0]Yout;
wire[7:0]Yout;
regs cas0 (al[0],wr,rd,clk,Din,Yout);
regs cas1 (al[1],wr,rd,clk,Din,Yout);
regs cas2 (al[2],wr,rd,clk,Din,Yout);
regs cas3 (al[3],wr,rd,clk,Din,Yout);
regs cas4 (al[4],wr,rd,clk,Din,Yout);
regs cas5 (al[5],wr,rd,clk,Din,Yout);
regs cas6 (al[6],wr,rd,clk,Din,Yout);
regs cas7 (al[7],wr,rd,clk,Din,Yout);
endmodule

module regs (al,wr,rd,clk,Din,Yout);

input al,wr,rd,clk;
input [7:0]Din;
output [7:0]Yout;
wire [7:0]c;
wire [7:0]Zout;
wire un0,un1,un2;
and an0 (un0,al,wr);
regs0 re (un0,clk,Din,c);
assign un1= (al&rd);
assign un2=(al&(!rd));
assign Zout=0;
bufif1 (Yout,c,un1);
bufif1 (Yout,Zout,un2);
endmodule
module regs0 (wr,clk,Din,Dout);
input wr,clk;
input [7:0]Din;
output [7:0] Dout;
reg [7:0] Dout;
always@(posedge clk or posedge wr)
begin
if ( wr)
Dout<=Din;
end
endmodule

MEMORY 8*16

module memory16(Din,ad,rd,wr,Yout,clk);
input clk,rd,wr;
input [15:0]Din;
input [2:0] ad;
output [15:0]Yout;
wire [7:0] al;
decoder16 cas0 (ad,al);
ram16 cas1 (al,wr,rd,clk,Din,Yout);
endmodule

module decoder16 (ad,al);

input [2:0]ad;
output[7:0]al;
reg [7:0]al;
always@(ad)
begin
case(ad)
0:al=8'b00000001;
1:al=8'b00000010;
2:al=8'b00000100;
3:al=8'b00001000;
4:al=8'b00010000;
5:al=8'b00100000;
6:al=8'b01000000;
7:al=8'b10000000;
endcase
end
endmodule

module ram16 (al,wr,rd,clk,Din,Yout);

input wr,rd,clk;
wire un2;
input [7:0] al;
input[15:0]Din;
output[15:0]Yout;
wire[15:0]Yout;
regs16 cas0 (al[0],wr,rd,clk,Din,Yout);
regs16 cas1 (al[1],wr,rd,clk,Din,Yout);
regs16 cas2 (al[2],wr,rd,clk,Din,Yout);
regs16 cas3 (al[3],wr,rd,clk,Din,Yout);
regs16 cas4 (al[4],wr,rd,clk,Din,Yout);
regs16 cas5 (al[5],wr,rd,clk,Din,Yout);
regs16 cas6 (al[6],wr,rd,clk,Din,Yout);
regs16 cas7 (al[7],wr,rd,clk,Din,Yout);
endmodule

module regs16 (x,wr,rd,clk,Din,Yout);

input x,wr,rd,clk;
input [15:0]Din;
output [15:0]Yout;
wire [15:0]c;
wire [15:0]Zout;
wire un0,un1,un2;
and an0 (un0,x,wr);
regs016 re (un0,clk,Din,c);
assign un1= (x&rd);
assign un2=(x&(!rd));
assign Zout=0;
bufif1 (Yout,c,un1);
bufif1 (Yout,Zout,un2);
endmodule

module regs016 (wr,clk,Din,Dout);

input wr,clk;
input [15:0]Din;
output [15:0] Dout;
reg [15:0] Dout;
always@(posedge clk )
begin
if ( wr)
Dout<=Din;
end
endmodule

Binary to BCD Conversion

//A special algorithm called “add-3 shift” is used here for the
conversion of binary to BCD
//A special algorithm called “add-3 shift” is used here for the
conversion of binary to BCD
 C is a combinational circuit which will generate the output as
per the input values. If the input is more than or equal to 5
,the logic will add 3 to the input and sum will be the output
otherwise(Input<5)output will be the same input. Let us try one
example.
module bbc8 (Dout,B);
input[7:0]Dout;
output[11:0]B;
wire [11:0] B;
wire [3:0]c1,c2,c3,c4,c5,c6,c7;
wire[3:0]d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,Dout[7:5]};
assign d2 = {c1[2:0],Dout[4]};
assign d3 = {c2[2:0],Dout[3]};
assign d4 ={c3[2:0],Dout[2]};
assign d5= {c4[2:0],Dout[1]};
assign d6= {1'b0,c1[3],c2[3],c3[3]};
assign d7={c6[2:0],c4[3]};

add3 C1 (d1,c1);
add3 C2 (d2,c2);
add3 C3 (d3,c3);
add3 C4 (d4,c4);
add3 C5 (d5,c5);
add3 C6 (d6,c6);
add3 C7 (d7,c7);

assign B={2'b00,c6[3],c7[3:0],c5[3:0],Dout[0]};
endmodule
 Alarm Generating section
Timer Data

R/W R
Memory
W +
Clock Comparat
ors
Addr Alarm
LED

Mode

module add3 (AI,BI);

input[3:0]AI;
output[3:0]BI;
reg[3:0]BI;

always@(AI)
begin
case(AI)
0:BI = 4'b0000;
1:BI = 4'b0001;
2:BI = 4'b0010;
3:BI = 4'b0011;
4:BI = 4'b0100;
5:BI = 4'b1000;
6:BI = 4'b1001;
7:BI = 4'b1010;
8:BI = 4'b1011;
9:BI = 4'b1100;
default:BI=4'b0000;
endcase
end
endmodule

module alarm (H,sysclk,s0,s1,s2,s3,s4,s5,s6,aled);

input [15:0] H;
input sysclk,s0,s1,s2,s3,s4,s5,s6;
output aled;
wire q;
meco cas0 (H,sysclk,s0,q,s1,s2,s3,s4,s5,s6,aled);
assign q=!s0;
endmodule
Memory+Comparators in the Alarm section

We can store 8 times in 8 registers that we need for alarms.8 comparators are
also using for the comparison between the current time and stored time. Mode
will enable the data out from the different registers to comparator
For example if we select the mode 7 ,alarm will give for all times that we
stored in the registers.

module meco (H,clk,wr,rd,s1,s2,s3,s4,s5,s6,aled);

input [15:0]H;
input clk,wr,rd,s1,s2,s3,s4,s5,s6;
output aled;
wire [7:0] al,m,com;
adddec cas0 ({s3,s2,s1},al);
modedec cas1 ({s6,s5,s4},m);
memcom cas3 (al[0],m[0],wr,rd,clk,H,com[0]);
memcom cas4 (al[1],m[1],wr,rd,clk,H,com[1]);
memcom cas5 (al[2],m[2],wr,rd,clk,H,com[2]);
memcom cas6 (al[3],m[3],wr,rd,clk,H,com[3]);
memcom cas7 (al[4],m[4],wr,rd,clk,H,com[4]);
memcom cas8 (al[5],m[5],wr,rd,clk,H,com[5]);
memcom cas9 (al[6],m[6],wr,rd,clk,H,com[6]);
memcom cas10 (al[7],m[7],wr,rd,clk,H,com[7]);
or cas11 (aled,com[0],com[1],com[2],com[3],com[4],com[5],com[6],com[7]);
endmodule

module adddec (ad,al);

input [2:0]ad;
output[7:0]al;
reg [7:0]al;
always@(ad)
begin
case(ad)
0:al=8'b00000001;
1:al=8'b00000010;
2:al=8'b00000100;
3:al=8'b00001000;
4:al=8'b00010000;
5:al=8'b00100000;
6:al=8'b01000000;
7:al=8'b10000000;
endcase
end
endmodule

module modedec (md,m);

input [2:0]md;
output[7:0]m;
reg [7:0]m;
always@(md)
begin
case(md)
0:m=8'b00000000;
1:m=8'b01000001;
2:m=8'b01001010;
3:m=8'b00101101;
4:m=8'b11100111;
5:m=8'b11001111;
6:m=8'b00100100;
7:m=8'b11111111;
endcase
end
endmodule

Memory + Comparators (Alarm)

module memcom (al,m,wr,rd,clk,H,com);

input al,m,wr,rd,clk;
input [15:0] H;
output com;
wire c0,c1;
wire[15:0]O,Y;
and cas0 (c0,al,wr);
and cas1 (c1,m,rd);
reg0mc cas2(c0,clk,H,O);
bufif1 cas3(Y,O,c1);
comparator cas4 (Y,H,com);
endmodule

module reg0mc (wr,clk,H,O);

input wr,clk;
input[15:0] H;
output [15:0]O;
reg [15:0] O;
always@(posedge clk)
begin
if (wr)
O<=H;
end
endmodule

module comparator (In1,In2,res);

input [15:0] In1,In2;
output res;
reg res;
always@(In1 or In2)
begin
if(In1==In2)
res<=1;
else
res<=0;
end
endmodule

DISPLAY SECTION
 module ssdd (In,Out,sysclk,En);
input [15:0] In;
input sysclk;
output [3:0]En;
output [7:0]Out;
wire [31:0] T;
wire [1:0]sel;
wire t1;
decoder cas0 (In,T);
ds cas1 (sel,T,Out);
controller cas2(t1,{En,sel});
div1 cas3 (sysclk,t1);
endmodule

//controller for data selector and providing the enable signal

for DISPLAYS

The controller provides the select lines for the Multiplexer and
enable signals (Active LOW) for the 4 seven segment LEDs.It
enable any one of the 4 LEDs and correspondingly gives the
select line status of the Mux. Actually ,we feel it like a
continuous display but one LED is ON at a time. Switching speed
is 4000Hz.

module controller(cont,ctrl);
input cont;
output[5:0]ctrl;
counter abcde1 (cont,ctrl[1:0]);
ctdecoder abcde2 (ctrl[1:0],ctrl[5:2]);
endmodule
module counter(inclk,oc);
input inclk;
output[1:0]oc;
reg[1:0]oc;
always@(posedge inclk)
oc <= oc+1;
endmodule

module ctdecoder(din1,dout1);
input[1:0]din1;
output[3:0]dout1;
reg[3:0]dout1;
always@(din1)
begin
case(din1)
0:dout1=4'b0111;
1:dout1=4'b1011;
2:dout1=4'b1101;
3:dout1=4'b1110;
endcase
end
endmodule
module decoder(I,D);
input [15:0]I;
output [31:0]D;

decode abcd1 (I[15:12],D[31:24]);

decode abcd2 (I[11:8],D[23:16]);
decode abcd3 (I[7:4],D[15:8]);
decode abcd4 (I[3:0],D[7:0]);
endmodule

module decode (I1,DOUT);

input [3:0]I1;
output [7:0]DOUT;
reg [7:0]DOUT;
always@(I1)
begin
case (I1)
0:DOUT=8'b00111111;
1:DOUT=8'b00000110;
2:DOUT=8'b01011011;
3:DOUT=8'b01001111;
4:DOUT=8'b01100110;
5:DOUT=8'b01101101;
6:DOUT=8'b01111101;
7:DOUT=8'b00000111;
8:DOUT=8'b01111111;
9:DOUT=8'b01100111;
endcase
end
endmodule

M
ult DISPLAY
Data from ipl
Decoder ex
er

Select
Lines

module ds(s,T,U);
input[1:0]s;
input[31:0]T;
output[7:0]U;
reg[7:0]U;
always@(s)
begin
case(s)
0 : U=T[31:24];
1 : U=T[23:16];
2 : U=T[15:8];
3 : U=T[7:0];
endcase
end
endmodule

module div1(clock,t1);
input clock;
output t1;
reg t1;
integer n;
always@(posedge clock)
begin
n <= n+1;
if(n<750)
t1 = 1;
else if (n<1500)
t1 =0;
else
n <=0;
end
endmodule

Other Modules in the Top module

demux0

module demux0 (ret0,ret1,ret0t,ret1t,ret0a,ret1rw,set);

input ret0,ret1,set;
output ret0t,ret1t,ret0a,ret1rw;

dmx cas0 (ret0,ret0t,ret0a,set);

dmx cas1 (ret1,ret1t,ret1rw,set);
endmodule
module dmx (ret0,ret0t,ret0a,set);
input ret0,set;
output ret0t,ret0a;
assign ret0t= set&ret0;
assign ret0a=(!set)&ret0;
endmodule

module countermt (c1,ad);

input c1;
output [2:0] ad ;
reg [2:0] ad;
always @(negedge c1)
begin
ad<=ad+1;
end
endmodule

module demux1 (rwm,ret,live,rd,wr,auto);

input rwm,ret,live,auto;
output rd,wr;
assign rd=(((!rwm)&(!ret))|live)|(!auto);
assign wr=((rwm&(!ret))|live)|auto;
endmodule
module countermtime (clk,autos,auto);
input clk,autos;
output auto;
wire u0;

and a (u0,autos,clk);
countmtime ca1 (u0,auto);
endmodule

module countmtime (u0,auto);

input u0;
output auto;
reg auto;
integer n;
always @(posedge u0)
begin
if (n<60)
begin
auto=0;
n=n+1;
end
else
begin
n=0;
auto=1;
end
end
endmodule

module mux_time_temp (U,out16,shft,Out);

input [15:0] U,out16;
input shft;
output [15:0]Out;
reg[15:0] Out;
always@(shft)
begin
case(shft)
0:Out=U;
1:Out=out16;
endcase
end
endmodule
Auto Display Shift

module autodsplyshft (b,autos,autoshft);

input b,autos;
output autoshft;
wire ws;

swdiv cas0 (b,ws);

and cas1 (autoshft,ws,autos);
endmodule
module swdiv (b,ws);
input b;
output ws;
reg ws;
integer n;
always@(posedge b)
begin
n<=n+1;
if(n<4)
ws<=0;
else if (n<8)
ws<=1;
else
n<=0;
end
endmodule