CXP82032/82040/82052/82060

CMOS 8-bit Single Chip Microcomputer

Description
The CXP82032/82040/82052/82060 is a CMOS 8- 100 pin QFP (Plastic)
bit single chip microcomputer integrating on a single
chip an A/D converter, serial interface, timer/counter,
time-base timer, capture timer/counter, fluorescent
display panel controller/driver, remote control
reception circuit, and PWM output besides the basic
configurations of 8-bit CPU, ROM, RAM, and I/O port.
The CXP82032/82040/82052/82060 also provides
sleep/stop function that enables lower power
consumption.
Structure
Features Silicon gate CMOS IC
• Wide-range instruction system (213 instructions)
to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM capacity 32k bytes (CXP82032)
40k bytes (CXP82040)
52K bytes (CXP82052)
60K bytes (CXP82060)
• Incorporated RAM capacity 3984 bytes (including fluorescent display area)
• Peripheral functions
— A/D converter 8 bits, 8 channels, successive approximation method
(Conversion time of 3.25µs/16MHz)
— Serial interface Buffer RAM incorporated (Auto transfer for 1 to 32 bytes), 1 channel
8-bit clock synchronized type (MSB/LSB first selectable), 1 channel
Start-stop synchronized type (UART), 1 channel
— Timers 8-bit timer, 8-bit timer/counter, 19-bit time-base timer
16-bit capture timer/counter, 32kHz timer/counter
— Fluorescent display panel controller/driver Supports the universal grid fluorescent display panel.
High voltage drive output port of 56 pins (40V)
Maximum of 640 segments display possible
Display timing number of 1 to 20
Dimmer function
Incorporated pull-down resistor (Mask option)
Hardware key scan function (Maximum of 16 × 8 key matrix
supportable)
— Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
— PWM output 14 bits, 1 channel
• Interruption 17 factors, 15 vectors, multi-interruption possible
• Standby mode Sleep/stop
• Package 100-pin plastic QFP
• Piggy/evaluation chip CXP82000 100-pin ceramic QFP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97413A95-PS
 Block Diagram

INT3/NMI

INT1
INT0
XTAL

INT2
VDD

EXTAL

TEX
VSS

RST

TX
2

AN0 to AN7 8 A/D CONVERTER

SPC 700 CLOCK GENERATOR/ 8 PA0 to PA7

PORT A
CPU CORE SYSTEM CONTROL
G0/A0 to G15/A15 16
FDP
A16 to A23 8 CONTROLLER/ RAM 8 PB0 to PB7
DRIVER
A24 to A56 32
PORT B

VFDP
KR0 to KR7 8 KEY SCAN RAM
ROM RAM 8 PC0 to PC7
RxD UART RECEIVER
PORT C

32K/40K/ 52K/60K 3984

TxD UART TRANSMITTER BYTES BYTES
UART BAUD RATE
8 PD0 to PD7
GENERATOR
PORT D

INTERRUPT CONTROLLER
PWM 14-BIT PWM GENERATOR 6 PE0 to PE5

–2–
2 PE6 to PE7
PORT E

RMC REMOCON FIFO

CS0 8 PF0 to PF7

SERIAL
BUFFER
PORT F

SI0
INTERFACE
SO0 RAM
SCK0 (CH0)
8 PG0 to PG7
SI1
PORT G

SO1 SERIAL INTERFACE (CH1) PRESCALER/ 32kHz

SCK1 TIME-BASE TIMER TIMER/COUNTER
2
EC0 8-BIT TIMER/COUNTER 0 8 PH0 to PH7
PORT H

8-BIT TIMER 1
2
TO 16-BIT CAPTURE 4 PI0 to PI4
CINT
PORT I

TIMER/COUNTER 2
EC1
2
ADJ
CXP82032/82040/82052/82060
 CXP82032/82040/82052/82060

Pin Assignment (Top View)

G10/A10
G11/A11
G12/A12

G13/A13
G14/A14
G15/A15
G2/A2
G3/A3
G4/A4
G5/A5
G6/A6
G7/A7
G8/A8
G9/A9

A16
A17
A18
A19
A20
VDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

G1/A1 1 80 A21
G0/A0 2 79 A22
NC 3 78 A23
PE0/EC0/INT0 4 77 PH7/A24
PE1/EC1/INT1 5 76 PH6/A25
PE2/INT2 6 75 PH5/A26
PE3/INT3/NMI 7 74 PH4/A27
PE4/RMC 8 73 PH3/A28
PE5/CINT 9 72 PH2/A29
PE6/PWM 10 71 PH1/A30
PE7/TO/ADJ 11 70 PH0/A31
PC0/KR0 12 69 PG7/A32
PC1/KR1 13 68 PG6/A33
PC2/KR2 14 67 PG5/A34
PC3/KR3 15 66 PG4/A35
PC4/KR4 16 65 PG3/A36
PC5/KR5 17 64 PG2/A37
PC6/KR6 18 63 PG1/A38
PC7/KR7 19 62 PG0/A39
PB0/TxD 20 61 PF7/A40
PB1/CS0/RxD 21 60 PF6/A41
PB2/SCK0 22 59 PF5/A42
PB3/SI0 23 58 PF4/A43
PB4/SO0 24 57 PF3/A44
PB5/SCK1 25 56 PF2/A45
PB6/SI1 26 55 PF1/A46
PB7/SO1 27 54 PF0/A47
PI0 28 53 PD7/A48
PA0/AN0 29 52 PD6/A49
PA1/AN1 30 51 PD5/A50

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PI3/TEX
Vss
PI2/TX

VDD
VFDP
PD0/A55
PD1/A54
PD2/A53
PD3/A52
PD4/A51
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
PI1
RST
EXTAL
XTAL

Note) 1. NC (Pin 3) is left open.

2. VDD (Pins 44 and 89) must be connected to VDD.

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 CXP82032/82040/82052/82060

Pin Description

Symbol I/O Functions

(Port A)
8-bit I/O port. I/O can be set in a
PA0/AN0 unit of single bits. Incorporation
I/O/ Analog inputs to A/D converter.
to of the pull-up resistor can be set
Analog input (8 pins)
PA7/AN7 through the program in a unit of
4 bits.
(8 pins)
PB0/TxD I/O/Output UART transmission data output.
Chip select input
PB1/CS0/ I/O/Input/ UART reception
for serial interface
RxD Input (Port B) data input pin.
(CH0).
8-bit I/O port. I/O can be set in a
PB2/SCK0 I/O/I/O unit of single bits. Incorporation Serial clock I/O (CH0).
PB3/SI0 I/O/Input of the pull-up resistor can be set Serial data input (CH0).
through the program in a unit of
PB4/SO0 I/O/Output 4 bits. Serial data output (CH0).
PB5/SCK1 I/O/I/O (8 pins) Serial clock I/O (CH1).
PB6/SI1 I/O/Input Serial data input (CH1).
PB7/SO1 I/O/Output Serial data output (CH1).
(Port C)
8-bit I/O port. I/O can be set in a
PC0/KR0 unit of single bits. Can drive Serves as key return inputs when
to 12mA sink current. operating key scan with fluorescent
I/O/Input
Incorporation of the pull-up display panel (FDP) segment signal.
PC7/KR7
resistor can be set through the (8 pins)
program in a unit of 4 bits.
(8 pins)
(Port D)
PD0/A55
8-bit I/O port. I/O can be set in a FDP segment signal (anode
to I/O/Output
unit of single bits. connection) outputs.
PD7/A48
(8 pins)
PE0/INT0/ Input/Input/
EC0 Input External event inputs
Inputs for for timer/counter.
PE1/INT1/ Input/Input/ external (2 pins)
EC1 Input interruption
PE2/INT2 Input/Input request.
(4 pins)
PE3/INT3/ Input/Input/ (Port E) Non-maskable
NMI Input 8-bit port. Lower 6 bits are for interruption request input.
inputs; upper 2 bits are for
PE4/RMC Input/Input outputs. Remote control reception circuit input.
(8 pins) External capture input to 16-bit
PE5/CINT Input/Input
timer/counter.
PE6/PWM Output/Output 14-bit PWM output.
Output for the 16-bit timer/counter
PE7/TO/ Output/Output/
rectangular waves, and 32kHz
ADJ Output
oscillation frequency division.

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 CXP82032/82040/82052/82060

Symbol I/O Functions

(Port F)
PF0/A47 FDP segment signal (anode
8-bit I/O port. I/O can be set in a
to I/O/Output connection) outputs.
unit of single bits.
PF7/A40 (8 pins)
(8 pins)
PG0/A39 (Port G) FDP segment signal (anode
to Output/Output 8-bit output port. connection) outputs.
PG7/A32 (8 pins) (8 pins)
PH0/A31 (Port H) FDP segment signal (anode
to Output/Output 8-bit output port. connection) outputs.
PH7/A24 (8 pins) (8 pins)
PI0 Input
PI1 Input (Port I)
4-bit input port.
PI2/TX Input Crystal connectors for 32kHz timer/counter clock
(4 pins)
oscillation. For usage as event counter, input to TEX,
PI3/TEX Input/Input and leave TX open.

A16 to A23 Output FDP segment signal (anode connection) outputs.

(8 pins)
G0/A0 Outputs for FDP timing signals (grid connection)/segment signals (anode
to Output/Output connection).
G15/A15 (16 pins)

VFDP FDP voltage supply when incorporated pull-down (PD) resistor is set by
mask option.
EXTAL Input Crystal connectors for system clock oscillation. When the clock is
supplied externally, input to EXTAL; opposite phase clock should be
XTAL input to XTAL.
RST Input Low-level active, system reset.
NC NC. Under normal operation, leave this pin open.
VDD VCC supply.
VSS GND.

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 CXP82032/82040/82052/82060

I/O Circuit Format for Pins

Pin Circuit format After a reset

Port A
Pull-up resistor ∗

"0" after a reset

Port A data

PA0/AN0 Port A direction IP Input protection circuit

to
"0" after a reset
PA7/AN7 Hi-Z
Internal data bus

RD (Port A)

Port A input selection

Input multiplexer
"0" after a reset
A/D converter
8 pins ∗ Pull-up transistor approx. 100kΩ

Port B
Pull-up resistor ∗
"0" after a reset

Port B data
PB0/TxD
PB1/CS0/RxD
PB3/SI0 Port B direction IP Hi-Z
PB6/SI1 "0" after a reset
Schmitt input (PB0/TxD excluded)
Internal data bus

RD (Port B) CS0
SI0
SI1
RxD
4 pins ∗ Pull-up transistor approx. 100kΩ

Port B

Pull-up resistor ∗
"0" after a reset
SCK OUT
Serial clock output enable

Port B output selection

PB2/SCK0
"0" after a reset
PB5/SCK1
Port B data Hi-Z
IP
Port B direction
"0" after a reset
Internal Schmitt input
data bus

RD (Port B)

SCK IN ∗ Pull-up transistor approx. 100kΩ

2 pins

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 CXP82032/82040/82052/82060

Pin Circuit format After a reset

Port B

Pull-up resistor ∗
"0" after a reset
SO
Serial data output enable

PB4/SO0 Port B output selection

PB7/SO1 "0" after a reset
Port B data
Hi-Z

IP
Port B direction
"0" after a reset
Internal
data bus

RD (Port B)
2 pins ∗ Pull-up transistor approx. 100kΩ

Port C
Pull-up resistor ∗2

"0" after a reset

Port C data
PC0/KR0
to
PC7/KR7 ∗1
Port C direction IP
Hi-Z
"0" after a reset

Internal data bus

RD (Port C)
8 pins Key input signak ∗1 Large current 12mA
∗2 Pull-up transistor approx. 100kΩ

Port E
PE0/EC0/INT0 EC0/INT0
PE1/EC1/INT1 EC1/INT1
Schmitt input INT2
PE2/INT2 INT3/NM1
PE3/INT3/NMI IP RMC
Hi-Z
PE4/RMC CINT
PE5/CINT Internal data bus

RD (PortE)
6 pins

Port E PWM

Port E output selection

"0" after a reset
PE6/PWM
Port E data High level
Output enable
"1" after a reset

Internal data bus

1 pin
RD (Port E)

–7–
 CXP82032/82040/82052/82060

Pin Circuit format After a reset

Port E
Internal reset signal

Port E data 00
"1" after a reset TO 01 MPX High level
ADJ16K∗1 10 (High level at
∗2
PE7/TO/ADJ ADJ2K∗2 11
ON resistance
of pull-up
Port E output selection (upper) transistor
Port E output selection (lower) during a reset)
"00" after a reset ∗1 ADJ signal is a frequency dividing
output for 32kHz oscillation frequency adjustment.
TO output enable ADJ2K can be used for buzzer output.
∗2 Pull-up transistor approx. 150kΩ
1 pin

Port D
Port F Segment output data
PD0/A55 ∗
Output selection control signal
to ("0" after a reset)
PD7/A48 Hi-Z or
PF0/A47 Low level
OP
to
Port D and F data (when PD
PF7/A40 IP Pull-down resistor resistor is
Port D and F direction
connected)
"1" after a reset VFDP
Internal
data bus
16 pins RD (Ports D and F) ∗
∗ High voltage drive transistor

Port G
Segment output data
Port H
PG0/A39 Output selection control signal ∗
to ("0" after a reset)
Hi-Z or
PG7/A32
OP Mask option Low level
PH0/A31 Port G and H data (when PD
to
"0" after a reset Pull-down resistor resistor is
PH7/A24
VFDP connected)
Internal data bus

16 pins RD (Ports G and H) ∗ High voltage drive transistor

Segment output data

∗
Output selection control signal
("0" after a reset) Hi-Z or
A16 to A23 Mask option OP Low level
(when PD
Pull-down resistor resistor is
VFDP
connected)

8 pins ∗ High voltage drive transistor

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 CXP82032/82040/82052/82060

Pin Circuit format After a reset

Segment output data

Timing output data ∗
Output selection control signal Hi-Z or
G0/A0 ("0" after a reset)
to Low level
Mask option OP (when PD
G15/A15
resistor is
Pull-down resistor connected)
VFDP
∗ High voltage drive transistor
16 pins

• Diagram shows circuit

EXTAL EXTAL composition during
IP IP oscillation.
XTAL
• Feedback resistor is Oscillation
removed and XTAL
becomes High level
XTAL during stop.
2 pins

PI0
PI1 IP Internal data bus
Hi-Z
2 pins RD (Port I)

TEX oscillation circuit control

"1" after a reset
Internal data bus

A A A
RD
PI2/TX Internal data bus

A A A
PI3/TEX RD Oscillation
PI3/TEX IP IP
Clock input
stop
Port input

2 pins PI2/TX
A
A
Pull-up resistor

RST
Mask option OP Low level
IP

1 pin Schmitt input

–9–
 CXP82032/82040/82052/82060

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Rating Unit Remarks

Supply voltage VDD –0.3 to +7.0 V
FDP display supply voltage VFDP –40∗2 to +7.0∗1 V
Input voltage VIN –0.3 to +7.0∗1 V
Output voltage VOUT –0.3 to +7.0∗1 V
Display output voltage VOD –40∗2 to +7.0∗1 V
All pins excluding display outputs∗3
IOH –5 mA
(value per pin)
High level output current IODH1 –15 mA Display outputs A20 to A55 (value per pin)
Display outputs G0/A0 to G15/A15, and
IODH2 –50 mA
A16 to A19 (value per pin)

High level total output ∑IOH –30 mA Total for all pins excluding display outputs
current ∑IODH –120 mA Total for all display outputs
IOL 15 mA Pins excluding large current output (value per pin)
Low level output current
IOLC 20 mA Large current output pins∗4 (value per pin)
Low level total output current ∑IOL 100 mA Total for all output pins
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +150 °C
Allowable power dissipation PD 600 mW
∗1VIN, VOUT and VOD must not exceed VDD + 0.3V.
∗2VFDP and VOD must not exceed VDD – 40V.
∗3Specifies output current of general-purpose I/O ports.
∗4The large current drive transistor is the N-CH transistor of Port C (PC).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be
conducted under the recommended operating conditions. Exceeding these conditions may adversely affect
the reliability of the LSI.

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 CXP82032/82040/82052/82060

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

Guaranteed operation range during
4.5 5.5 V 1/2 and 1/4 frequency dividing operation
mode
During 1/16 frequency dividing
Supply voltage VDD 3.5 5.5 V
operation mode or sleep mode
Guaranteed operation range with TEX
2.7 5.5 V
clock
2.5 5.5 V Guaranteed data hold range during stop
VIH 0.7VDD VDD V ∗1

VIHS 0.8VDD VDD V ∗2

High level input
voltage VIHH 0.7VDD VDD V ∗3

VIHEX VDD – 0.4 VDD + 0.3 V EXTAL∗4

VIL 0 0.3VDD V ∗1

VILS 0 0.2VDD V ∗2
Low level input
voltage VILH 0 0.7 V ∗3

VILEX –0.3 0.4 V EXTAL∗4

Operating temperature Topr –20 +75 °C
∗1 Value for each pin of normal input port (PA,PB0, PB4, PB7, PC).
∗2 Value of the following pins: RST, CINT, CS0/TxD, RxD, SI0, SI1, SCK0, SCK1, EC0/INT0, EC1/INT1, INT2,
INT3/NMI, RMC.
∗3 Value of the following pins: PD, PF.
∗4 Specifies only during external clock input.

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 CXP82032/82040/82052/82060

Electrical Characteristics

DC Characteristics (Ta = –20 to +75°C, VSS = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit
PA to PD, VDD = 4.5V, IOH = –0.5mA 4.0 V
High level VOH PE6, PE7,
output voltage VDD = 4.5V, IOH = –1.2mA 3.5 V
PF to PH
PA to PC, VDD = 4.5V, IOL = 1.8mA 0.4 V
Low level PE6, PE7
output voltage VOL VDD = 4.5V, IOL = 3.6mA 0.6 V
PC VDD = 4.5V, IOL = 12.0mA 1.5 V
IIHE VDD = 5.5V, VIH = 5.5V 0.5 40 µA
EXTAL
IILE VDD = 5.5V, VIL = 0.4V –0.5 –40 µA
IIHT VDD = 5.5V, VIL = 5.5V 0.1 10 µA
TEX
IILT VDD = 5.5V, VIL = 0.4V –0.1 –10 µA
Input current
IILR RST∗1 –1.5 –400 µA
VDD = 5.5V, VIL = 0.4V
–50 µA
IIL PA to PC∗2
VDD = 4.5V, VIL = 4.0V –3.3 µA
A20 to A55 –8 mA
Display output G0/A0 to VDD = 4.5V
IOH
current G15/A15 VOH = VDD –2.5V –30 mA
A16 to A19
Open drain
G0/A0 to VDD = 5.5V
output leakage
ILOL G15/A15 VOL = VDD – 35V –20 µA
current (P-CH
A16 to A55 VFDP = VDD – 35V
Tr off state)
G0/A0 to
Pull-down VDD = 5V
resistor∗3
RL G15/A15 30 70 220 kΩ
VOD – VFDP = 30V
A16 to A55
PA to PC∗2,
I/O leakage PD∗4,PE0 to VDD = 5.5V
PE5,PF∗4,PI,
IIZ ±10 µA
current VI = 0, 5.5V
RST∗1

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 CXP82032/82040/82052/82060

Item Symbol Pins Conditions Min. Typ. Max. Unit

1/2 frequency dividing
IDD1 operation mode
23 50 mA
VDD = 5.5V, 16MHz crystal
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
IDD2 30 100 µA
oscillation (C1 = C2 = 47pF)
Power supply Sleep mode
current∗5
VDD
IDDS1 VDD = 5.5V, 16MHz crystal 1.2 8 mA
oscillation (C1 = C2 = 15pF)
VDD = 3V, 32kHz crystal
IDDS2 12 30 µA
oscillation (C1 = C2 = 47pF)
Stop mode
IDDS3 VDD = 5.5V, termination of 16MHz 10 µA
and 32kHz crystal oscillation

PA to PC,
PD∗4,
Clock 1MHz
PE0 to PE5,
Input capacity 10 20 pF
PF∗4,PI,
CIN 0V for all pins excluding
measured pins
EXTAL,
TEX, RST

∗1 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor
has been selected.
∗2 PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no
resistor has been selected.
∗3 When incorporated pull-down resistor has been selected through mask option.
∗4 PD and PF pins are used as inputs by program. They specify pull-down resistor when no resistor has been
selected by mask option.
∗5 When all pins are open.

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 CXP82032/82040/82052/82060

AC Characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pin Conditions Min. Typ. Max. Unit
XTAL
System clock frequency fC Fig. 1, Fig. 2 1 16 MHz
EXTAL
tXL Fig. 1, Fig. 2
System clock input pulse width EXTAL 28 ns
tXH External clock drive
System clock input rise time, tCR Fig. 1, Fig. 2
fall time tCF EXTAL
External clock drive
tsys + 50∗1 200 ns

Event count input clock tEH EC0,

Fig. 3 ns
pulse width tEL EC1
Event count input clock tER EC0,
Fig. 3 20 ms
rise time, fall time tEF EC1
VDD = 2.7 to 5.5V
TEX
System clock frequency fC Fig. 2 (32kHz clock 32.768 kHz
TX
applied condition)
Event count input tTL TEX Fig. 3 10 µs
pulse width tTH
Event count input rise time, tTR TEX Fig. 3 20 ms
fall time tTF
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
1/fc

VDD – 0.4V
EXTAL
0.4V

tXH tCF tXL tCR

Fig. 1. Clock timing

AAAAAAAAAAAA
Crystal oscillation 32kHz clock applied condition
Ceramic oscillation External clock Crystal oscillation

AAAAAAAAAAAA
EXTAL

C1
XTAL

C2
EXTAL

74HC04
XTAL

C1
TEX TX

C2

Fig. 2. Clock applied conditions

0.8VDD
TEX
EC0
EC1 0.2VDD

tEH tEF tEL tER

tTH tTF tTL tTR

Fig. 3. Event count clock timing

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 CXP82032/82040/82052/82060

(2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Conditions Min. Max. Unit

CS0 ↓ → SCK0 Chip select transfer mode
tDCSK SCK0 tsys + 200 ns
delay time (SCK0 = output mode)
CS0 ↑ → SCK0 Chip select transfer mode
tDCSKF SCK0 tsys + 200 ns
float delay time (SCK0 = output mode)
CS0 ↓ → SO0
tDCSO SO0 Chip select transfer mode tsys + 200 ns
delay time
CS0 ↑ → SO0
tDCSOF SO0 Chip select transfer mode tsys + 200 ns
float delay time
CS0 High level width tWHCS CS0 Chip select transfer mode tsys + 200 ns
Input mode 2tsys + 200 ns
SCK0 cycle time tKCY SCK0
Output mode 16000/fc ns

SCK0 tKH Input mode tsys + 100 ns

High, Low level width SCK0
tKL Output mode 8000/fc – 50 ns

SI0 input set-up time SCK0 input mode 100 ns

(for SCK0 ↑) tSIK SI0
SCK0 output mode 200 ns

SI0 input hold time SCK0 input mode tsys + 200 ns

(for SCK0 ↑) tKSI SI0
SCK0 output mode 100 ns

SCK0 ↓ → SO0 SCK0 input mode tsys + 200 ns

delay time tKSO SO0
SCK0 output mode 100 ns

Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
clock control register (CLC: 00FEh).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.

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 CXP82032/82040/82052/82060

tWHCS

CS0
0.8VDD

0.2VDD

tKCY

tDCSK tDCSKF
tKL tKH

0.8VDD 0.8VDD

SCK0

0.2VDD

tSIK tKSI

0.8VDD

SI0 Input data

0.2VDD

tDCSO tKSO tDCSOF

0.8VDD
SO0 Output data
0.2VDD

Fig. 4. Serial transfer CH0 timing

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 CXP82032/82040/82052/82060

Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

Input mode 1000 ns
SCK1 cycle time tKCY SCK1
Ouput mode 16000/fc ns

SCK1 tKH Input mode 400 ns

SCK1
High, Low level width tKL Ouput mode 8000/fc – 50 ns

SI1 input set-up time SCK1 input mode 100 ns

(for SCK1 ↑)
tSIK SI1
SCK1 ouput mode 200 ns

SI1 input hold time SCK1 input mode 200 ns

(for SCK1 ↑)
tKSI SI1
SCK1 ouput mode 100 ns
SCK1 input mode 200 ns
SCK1 ↓ → SO1 delay time tKSO SO1
SCK1 ouput mode 100 ns
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.

tKCY

tKL tKH

0.8VDD
SCK1
0.2VDD

tSIK tKSI

0.8VDD
SI1 Input data
0.2VDD

tKSO

0.8VDD
SO1 Output data
0.2VDD

Fig. 5. Serial transfer CH1 timing

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 CXP82032/82040/82052/82060

(3) A/D converter characteristics

(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Typ. Max. Unit

Resolution 8 Bits
Linearity error ±3 LSB

VZT∗1
Zero transition Ta = 25°C
–10 10 70 mV
voltage VDD = 5.0V
VSS = 0V
VFT∗2
Full-scale
4910 4970 5030 mV
transition voltage
Conversion time tCONV 26/fADC∗3 µs
Sampling time tSAMP 6/fADC∗3 µs
Analog input voltage VIAN AN0 to AN7 0 VDD V

∗1 VZT: Value at which the digital conversion value changes from

FFh
00h to 01h and vice versa.
FEh
∗2 VFT: Value at which the digital conversion value changes from
Digital conversion value

FEh to FFh and vice versa.

∗3 fADC indicates the below values due to the contents of bit 6 (CKS)
of the A/D control register (ADC: 00F9h) and bits 7 (PCK1) and 6
(PCK0) of the clock control register (CLC: 00FEh).
Linearity error fADC = fc (CKS = "0"), fc/2 (CKS = "1")
However, the selection for fADC = fc (CKS = "0") is
01h
00h
limited in the clock range of fc = 1 to 14MHz (VDD = 4.5
VZT VFT to 5.5V).
Analog input

Fig. 6. Definition of A/D converter terms

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 CXP82032/82040/82052/82060

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pin Condition Min. Max. Unit

INT0
External interruption tIH INT1
1 µs
High, Low level width tIL INT2
NMI/INT3
Reset input Low level width tRSL RST 32/fc µs

tIH tIL

0.8VDD
INT0
0.2VDD
INT1
INT2 tIL tIH
NMI/INT3
(NMI specifies only for the
falling edge)

Fig. 7. Interruption input timing

tRSL

RST
0.2VDD

Fig. 8. RST input timing

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 CXP82032/82040/82052/82060

Appendix

AAAA
(i) Main clock

AAAA
EXTAL XTAL
AAAA
(ii) Main clock

AAAA
EXTAL XTAL
AAAA
(iii) Sub clock

AAAAEXTAL
TEX XTAL
TX

Rd Rd Rd

C1 C2 C1 C2
C1 C2

Fig. 9. Recommended oscillation circuit

Circuit
Manufacturer Model fc (MHz) C1 (pF) C2 (pF) Rd (Ω) Remarks
example
CSA10.0MTZ 10.0
30 30
CSA12.0MTZ 12.0 (i)
MURATA CSA16.00MXZ040 16.0 5 5
MFG 0
CO., LTD. CST10.0MTW∗ 10.0
30 30
CST12.0MTW∗ 12.0 (ii)
CST16.00MXW0C1∗ 16.0 5 5
8.0 18 18
RIVER ELETEC
CO., LTD HC-49/U03 12.0 12 12 330
16.0 10 10
(i)
8.0 10 10
KINSEKI
HC-49/U (-S) 12.0 5 5 0
LTD.
16.0 Open Open
Seiko VTC-200
32.768kHz 18 18 330k (iii) CL = 12.5pF
Instruments Inc. SP-T

Models marked with an asterisk (∗) have the built-in ground capacitance (C1, C2).

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 CXP82032/82040/82052/82060

Characteristics Curve

IDD vs. VDD IDD vs. fc

(Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical)
100 25

1/2 dividing mode

20
1/4 dividing mode
10

1/2 dividing mode

1/16 dividing mode

IDD – Supply current [mA]

IDD – Supply current [mA]

15

Sleep mode
1

10
1/4 dividing mode

0.1
32kHz mode
5

32kHz 1/16 dividing mode

Sleep mode

Sleep mode
0.01 0
0 1 2 3 4 5 6 7 0 5 10 15 20
VDD – Supply voltage [V] fc – System clock [MHz]

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 CXP82032/82040/82052/82060

Package Outline Unit: mm

100PIN QFP (PLASTIC)

23.9 ± 0.4
+ 0.4 + 0.1
20.0 – 0.1 0.15 – 0.05

80 51

81 50

15.8 ± 0.4
14.0 – 0.1
17.9 ± 0.4
+ 0.4
A

100 31

1 + 0.15 30
0.65 0.3 – 0.1 + 0.35
0.13 M 2.75 – 0.15

+ 0.2
0.1 – 0.05
0.15
(16.3)

0° to 10°
0.8 ± 0.2

DETAIL A

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP-100P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE QFP100-P-1420 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 1.7g

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