Omni ision

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Preliminary Datasheet

OV7660/OV7161 CMOS VGA (640x480) CAMERACHIPTM with OmniPixelTM Technology

General Description Applications

The OV7660/OV7161 CAMERACHIPTM is a low voltage • Cellular and Picture Phones
CMOS image sensor that provides the full functionality of • Toys
a single-chip VGA camera and image processor in a small • PC Multimedia
footprint package. The OV7660/OV7161 provides • Digital Still Cameras
full-frame, sub-sampled or windowed 8-bit images in a
wide range of formats, controlled through the Serial Key Specifications
Camera Control Bus (SCCB) interface.
Array Element (VGA) 664 x 492
Digital Core 1.8VDC
This product has an image array capable of operating at
Power Supply Analog 2.45V to 2.8V
up to 30 frames per second (fps) in VGA with complete I/O 2.5V to (VDD-A+0.3V)
user control over image quality, formatting and output data Power Active 40 mW without loading
transfer. All required image processing functions, Requirements Standby < 10 µA
including exposure control, gamma, white balance, color Temperature Operation -20°C to 80°C
saturation, hue control and more, are also programmable Range Stable Image -10°C to 60°C
through the SCCB interface. In addition, OmniVision • YUV/YCbCr 4:2:2
CAMERACHIPs use proprietary sensor technology to Output Formats (8-bit) • RGB 4:2:2
improve image quality by reducing or eliminating common • Raw RGB Data
lighting/electrical sources of image contamination, such Lens Size 1/5"
as fixed pattern noise (FPN), smearing, blooming, etc., to Lens Chief Ray Angle ~20°
VGA, CIF,
produce a clean, fully stable color image. Max Image QCIF, QQCIF 30 fps
Transfer Rate QVGA,
60 fps
Features QQVGA
Sensitivity 1.0 V/Lux-sec
• High sensitivity for low-light operation S/N Ratio > 48 dB (AGC off, Gamma=1)
• Low operating voltage for embedded portable Dynamic Range > 72 dB
applications Scan Mode Progressive
Electronics Exposure Up to 510:1 (for selected fps)
• Standard SCCB interface
Gamma Correction 0.45/0.55/1.00
• VGA, QVGA, QQVGA, CIF, QCIF, QQCIF and Pixel Size 4.2 µm x 4.2 µm
windowed outputs with Raw RGB, RGB (GRB 4:2:2), Dark Current 30 mV/s at 60°C
YUV (4:2:2) and YCbCr (4:2:2) formats Well Capacity 35 K e
• VarioPixelTM method for sub-sampling formats Fixed Pattern Noise < 0.03% of VPEAK-TO-PEAK
Image Area 2.76 mm x 2.05 mm
• Automatic image control functions including:
Package Dimensions 4155 µm x 3975 µm
Automatic Exposure Control (AEC), Automatic Gain
Control (AGC), Automatic White Balance (AWB), Figure 1 OV7660/OV7161 Pin Diagram
Automatic Brightness Control (ABC), and Automatic
Black-Level Calibration (ABLC)
• Image quality controls including color saturation, A1 A2 A3 A4 A5
hue, gamma, sharpness (edge enhancement), and AVDD AGND SIO_C D1 D3
anti-blooming
B1 B2 B3 B4 B5

VREF
Ordering Information
PWDN SIO_D D0 D2

C1 C2
OV7660/OV7161
Product Package VSYNC DVDD

D1 D2 D3 D4 D5
OV07660-KL6A (Color) CSP-22 HREF PCLK RESET D7 D5

OV07161-KL6A (B&W with microlens) CSP-22 E1 E2 E3 E4 E5

DOVDD XCLK1 DOGND D6 D4

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Functional Description
Figure 2 shows the functional block diagram of the OV7660/OV7161 image sensor. The OV7660/OV7161 includes:
• Image Sensor Array
• Analog Signal Processor
• A/D Converters
• Digital Signal Processor (DSP)
• Output Formatter
• Timing Generator
• SCCB Interface
• Digital Video Port

Figure 2 Functional Block Diagram

Analog
Video
Processing A/D DSP Formatter D[7:0]
R Port

Column Sense Amp Exposure/Gain White Balance

Detect Detect
Row Select

Image Array
(664 x 492)
Registers

Clock Video Timing Generator

Exposure/Gain White Balance SCCB

Control Control Interface

XCLK1 HREF PCLK VSYNC RESET PWDN

SIO_C SIO_D

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Omni ision Functional Description

Image Sensor Array In addition to the A/D conversion, this block also has the
following functions:
The OV7660/OV7161 sensor has an active image array of • Digital Black-Level Calibration (BLC)
640 columns x 480 rows (307,200 pixels). Figure 3 shows • Optional U/V channel delay
a cross-section of the image sensor array. • Additional A/D range controls

Figure 3 Image Sensor Array In general, the combination of the A/D Range Multiplier
and A/D Range Control sets the A/D range and maximum
Microlens
value to allow the user to adjust the final image brightness
Glass
as a function of the individual application.

Digital Signal Processor (DSP)

Blue Green Red This block controls the interpolation from Raw data to
RGB and some image quality control.
• Edge enhancement (a two-dimensional high pass
filter)
• Color space converter (can change Raw data to RGB
Timing Generator or YUV/YCbCr)
• RGB matrix to eliminate color cross talk
In general, the timing generator controls the following • Hue and saturation control
functions:
• Programmable gamma control
• Array control and frame generation (7 different
• Transfer 10-bit data to 8-bit
format outputs)
• Internal timing signal generation and distribution
• Frame rate timing
Output Formatter
• Automatic Exposure Control (AEC)
• External timing outputs (VSYNC, HREF/HSYNC, and This block controls all output and data formatting required
PCLK) prior to sending the image out.

Analog Signal Processor Digital Video Port

This block performs all analog image functions including: Register bits COM2[1:0] increase IOL/IOH drive current
• Automatic Gain Control (AGC) and can be adjusted as a function of the customer’s
• Automatic White Balance (AWB) loading.

A/D Converters SCCB Interface

After the Analog Processing block, the bayer pattern Raw The Serial Camera Control Bus (SCCB) interface controls
signal is fed to a 10-bit analog-to-digital (A/D) converter the CAMERACHIP operation. Refer to OmniVision
shared by G and BR channels. This A/D converter Technologies Serial Camera Control Bus (SCCB)
operates at speeds up to 12 MHz and are fully Specification for detailed usage of the serial control port.
synchronous to the pixel rate (actual conversion rate is
related to the frame rate).

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Pin Description

Table 1 Pin Description

Pin Number Name Pin Type Function/Description

A1 AVDD Power Analog power supply (+2.5 VDC)

A2 AGND Power Analog ground

A3 SIO_C Input SCCB serial interface clock input

A4 D1a Output YUV/RGB video component output bit[1]

A5 D3 Output YUV/RGB video component output bit[3]

B1 VREF Reference Reference voltage - connect to ground using a 0.1 µF capacitor

Power Down Mode Selection

B2 PWDN Input (0)b 0: Normal mode
1: Power down mode

B3 SIO_D I/O SCCB serial interface data I/O

B4 D0 Output YUV/RGB video component output bit[0]

B5 D2 Output YUV/RGB video component output bit[2]

C1 VSYNC Output Vertical sync output

C2 DVDD Power Power supply (+1.8 VDC) for digital logic core

D1 HREF Output HREF output

D2 PCLK Output Pixel clock output

D3 RESET Input (0) Clears all registers and resets them to their default values.

D4 D7 Output YUV/RGB video component output bit[7]

D5 D5 Output YUV/RGB video component output bit[5]

E1 DOVDD Power Digital power supply for I/O (VDD-IO = 2.5 to (VDD-A+03.V))

E2 XCLK1 Input System clock input

E3 DOGND Power Digital ground

E4 D6 Output YUV/RGB video component output bit[6]

E5 D4 Output YUV/RGB video component output bit[4]

a. D[7:0] for 8-bit YUV or RGB (D[7] MSB, D[0] LSB)

b. Input (0) represents an internal pull-down resistor.

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Electrical Characteristics

Table 2 Absolute Maximum Ratings

Ambient Storage Temperature -40ºC to +95ºC

VDD-A 4.5 V

Supply Voltages (with respect to Ground) VDD-C 3V

VDD-IO 4.5 V

All Input/Output Voltages (with respect to Ground) -0.3V to VDD-IO+1V

Lead-free Temperature, Surface-mount process 245ºC

ESD Rating, Human Body model 2000V

NOTE: Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.

Table 3 DC Characteristics (-20°C < TA < 70°C)

Symbol Parameter Condition Min Typ Max Unit

VDD-A DC supply voltage – Analog – 2.45 2.5 2.8 V

VDD-C DC supply voltage – Digital Core – 1.62 1.8 1.98 V

VDD-IO DC supply voltage – I/O power – 2.25 VDD-A+0.3V V

IDDA Active (Operating) Current See Note a 20 mA

IDDS-SCCB Standby Current 1 mA

See Note b
IDDS-PWDN Standby Current 10 20 µA

VIH Input voltage HIGH CMOS 0.7 x VDD-IO V

VIL Input voltage LOW 0.3 x VDD-IO V

VOH Output voltage HIGH CMOS 0.9 x VDD-IO V

VOL Output voltage LOW 0.1 x VDD-IO V

IOH Output current HIGH See Note c 8 mA

IOL Output current LOW 15 mA

IL Input/Output Leakage GND to VDD-IO ±1 µA

a. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V

IDDA = ∑{IDD-IO+ IDD-C + IDD-A}, fCLK = 24MHz at 7.5 fps YUV output, no I/O loading
b. VDD-A = 2.5V, VDD-C = 1.8V, VDD-IO = 2.5V
IDDS:SCCB refers to a SCCB-initiated Standby, while IDDS:PWDN refers to a PWDN pin-initiated Standby
c. Standard Output Loading = 25pF, 1.2KΩ

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Table 4 Functional and AC Characteristics (-20°C < TA < 70°C)

Symbol Parameter Min Typ Max Unit
Functional Characteristics
A/D Differential Non-Linearity + 1/2 LSB
A/D Integral Non-Linearity +1 LSB
AGC Range 18 dB
Red/Blue Adjustment Range 12 dB
Inputs (PWDN, CLK, RESET)

fCLK Input Clock Frequency 10 24 48 MHz

tCLK Input Clock Period 21 42 100 ns

tCLK:DC Clock Duty Cycle 45 50 55 %

tS:RESET Setting time after software/hardware reset 1 ms

tS:REG Settling time for register change (10 frames required) 300 ms
SCCB Timing (see Figure 4)

fSIO_C Clock Frequency 150 KHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tAA SIO_C low to Data Out valid 100 900 ns

tBUF Bus free time before new START 1.3 µs

tHD:STA START condition Hold time 600 ns

tSU:STA START condition Setup time 600 ns

tHD:DAT Data-in Hold time 0 µs

tSU:DAT Data-in Setup time 100 ns

tSU:STO STOP condition Setup time 600 ns

tR, tF SCCB Rise/Fall times 300 ns

tDH Data-out Hold time 50 ns

Outputs (VSYNC, HREF, PCLK, and D[7:0] (see Figure 5, Figure 6, Figure 7, Figure 9, and Figure 10)

tPDV PCLK[↓] to Data-out Valid 5 ns

tSU D[7:0] Setup time 15 ns

tHD D[7:0] Hold time 8 ns

tPHH PCLK[↓] to HREF[↑] 0 5 ns

tPHL PCLK[↓] to HREF[↓] 0 5 ns

• VDD: VDD-C = 1.8V, VDD-A = 2.5V, VDD-IO = 2.5V

• Rise/Fall Times: I/O: 5ns, Maximum
AC SCCB: 300ns, Maximum
Conditions: • Input Capacitance: 10pf
• Output Loading: 25pF, 1.2KΩ to 2.5V
• fCLK: 24MHz

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Omni ision Timing Specifications

Timing Specifications

Figure 4 SCCB Timing Diagram

tF t HIGH tR
tLOW

SIO_C
t HD:STA t HD:DAT t SU:DAT
tSU:STA tSU:STO

SIO_D
IN
t BUF
tAA t DH
SIO_D
OUT

Figure 5 Horizontal Timing

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[7:0] Last Byte First Byte Last Byte

tPDV

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Figure 6 VGA Frame Timing

510 x tLINE

VSYNC
480 x tLINE
4 x tLINE 11 tLINE
tLINE = 784 tP 15 tLINE
144 tP
HREF

640 tP
80 tP 45 tP 19 tP
HSYNC

D[7:0] Invalid Data Invalid Data

P0 - P639
Row 0 Row 1 Row 2 Row 479
NOTE:
For Raw data, tP = tPCLK
For YUV/RGB, tP = 2 x tPCLK

Figure 7 QVGA Frame Timing

328 x tLINE

VSYNC
240 x tLINE
3 x tLINE 12 x tLINE
tLINE = 608 tP
73 x tLINE
288 tP
HREF

320 tP
80 tP 181 tP 27 tP
HSYNC

D[7:0] Invalid Data Invalid Data

P0 - P319
Row 0 Row 1 Row 2 Row 239
NOTE:
For Raw data, tP = tPCLK
For YUV/RGB, tP = 2 x tPCLK

Figure 8 QQVGA Frame Timing

328 x tLINE

VSYNC

120 x 2tLINE
3 x tLINE 12 x tLINE
tLINE = 608 tP
73 x tLINE
181 tP 288 tP
HREF

320 tP
80 tP 288tP + 1tLINE 27 tP
HSYNC

D[7:0] Invalid Data Invalid Data

P0 - P159
Row 0 Row 1 Row 119
NOTE:
For Raw data, tP = tPCLK / 2
For YUV/RGB, tP = tPCLK

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Omni ision Timing Specifications

Figure 9 CIF Frame Timing

328 x tLINE

VSYNC

288 x tLINE
tLINE = 608 tP
25 tLINE
3 x tLINE 12 tLINE 256 tP

HREF

352 tP
40 tP 91 tP 125 tP
HSYNC

D[7:0] Invalid Data Invalid Data

P0 - P351
Row 0 Row 1 Row 2 Row 287
NOTE:
For Raw data, tP = tPCLK
For YUV/RGB, tP = 2 x tPCLK

Figure 10 QCIF Frame Timing

328 x tLINE

VSYNC

144 x 2tLINE
tLINE = 608 tP
25 tLINE
3 x tLINE 12 tLINE 256 tP

HREF
352 tP 256tP + 1tLINE
40 tP 91 tP 125 tP
HSYNC

D[7:0] Invalid Data Invalid Data

P0 - P175
Row 0 Row 1 Row 143
NOTE:
For Raw data, tP = tPCLK / 2
For YUV/RGB, tP = tPCLK

Figure 11 QQCIF Frame Timing

328 x tLINE

VSYNC

3 x tLINE 72 x 4tLINE
tLINE = 608 tP
12 x tLINE 256 tP 25 tLINE

HREF
352 tP 256tP + 3tLINE

40 tP 91 tP 125 tP

HSYNC

D[7:0] Invalid Data Invalid Data

P0 - P87
NOTE: Row 0 Row 1 Row 71
For Raw data, tP = tPCLK / 4
For YUV/RGB, tP = tPCLK / 2

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Figure 12 RGB 565 Output Timing Diagram

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[7:0] Last Byte First Byte Last Byte

tPDV

First Byte Second Byte

D[7] R4 G2 D[7]
D[6] D[6]
D[5] G0 D[5]
D[4] B4 D[4]
D[3] R0 D[3]
D[2] G5 D[2]
D[1] D[1]
D[0] G3 B0 D[0]

Figure 13 RGB 555 Output Timing Diagram

tPCLK

PCLK

t PHL tPHL

HREF (Row Data)

tSU
t HD

D[7:0] Last Byte First Byte Last Byte

tPDV

First Byte Second Byte

D[7] X G2 D[7]
D[6] R4 D[6]
D[5] G0 D[5]
D[4] B4 D[4]
D[3] D[3]
D[2] R0 D[2]
D[1] G4 D[1]
D[0] G3 B0 D[0]

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Omni ision Timing Specifications

OV7660/OV7161 Light Response

Figure 14 OV7660/OV7161 Light Response

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Register Set
Table 5 provides a list and description of the Device Control registers contained in the OV7660/OV7161. For all register
Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 42 for write and 43 for read.

Table 5 Device Control Register List

Address Register Default

(Hex) Name (Hex) R/W Description

AGC – Gain control gain setting

00 GAIN 00 RW
• Range: [00] to [7F]

AWB – Blue channel gain setting

01 BLUE 80 RW
• Range: [00] to [FF]

AWB – Red channel gain setting

02 RED 80 RW
• Range: [00] to [FF]

Vertical Frame Control

Bit[7:6]: AGC[9:8]
Bit[5]: Fix gain1
03 VREF 00 RW
Bit[4]: Fix gain0
Bit[3:2]: VREF end low 2 bits (high 8 bits at VSTOP[7:0]
Bit[1:0]: VREF start low 2 bits (high 8 bits at VSTRT[7:0]

Common Control 1
Bit[7]: Reserved
Bit[6]: CCIR656 format
Bit[5]: QQVGA or QQCIF format. Effective only when QVGA or
QCIF output is selected (register bit COM7[4] or COM7[3])
and related HREF skip mode based on format is selected
(register COM1[3:2])
04 COM1 00 RW Bit[4]: Reserved
Bit[3:2]: HREF skip option
00: No skip
01: YUV/RGB skip every other row for YUV/RGB, skip 2
rows for every 4 rows for Raw data
1x: Skip 3 rows for every 4 rows for YUV/RGB, skip 6
rows for every 8 rows for Raw data
Bit[1:0]: AEC low 2 LSB (see registers AECHH for AEC[15:10] and
AECH for AEC[9:2])

U/B Average Level

05 BAVE 00 RW
Automatically updated based on chip output format

Y/Ge Average Level

06 GEAVE 00 RW
Automatically updated based on chip output format

Exposure Value - AEC MSB 5 bits

Bit[7:6]: Reserved
07 AECHH 00 RW
Bit[5:0]: AEC[15:10] (see registers AECH for AEC[9:2] and COM1
for AEC[1:0])

V/R Average Level

08 RAVE 00 RW
Automatically updated based on chip output format

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 2
Bit[7:5]: Reserved
Bit[4]: Soft sleep mode
Bit[3:2]: Reserved
09 COM2 01 RW Bit[1:0]: Output Drive Capability
00: 1x
01: 2x
10: 2x
11: 4x

0A PID 76 R Product ID Number MSB (Read only)

0B VER 60 R Product ID Number LSB (Read only)

Common Control 3
Bit[7]: Reserved
Bit[6]: Output data MSB and LSB swap
Bit[5]: Tri-state option for output clock at power-down period
0: Tri-state at this period
1: No tri-state at this period
Bit[4]: Tri-state option for output data at power-down period
0C COM3 00 RW 0: Tri-state at this period
1: No tri-state at this period
Bit[3:2]: Horizontal average control
x0: No average
01: 2 pixel average
11: 4 pixel average
Bit[1]: VarioPixel for QVGA, QQVGA, CIF, QCIF, and QQCIF
Bit[0]: Single frame output (used for Frame Exposure mode only)

Common Control 4
0D COM4 40 RW
Bit[7:0]: Reserved

Common Control 5
Bit[7]: System clock selection. If the system clock is 48 MHz, this
0E COM5 01 RW
bit should be set to high to get a higher frame rate
Bit[6:0]: Reserved

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 6
Bit[7]: Output of optical black line option
0: Disable HREF at optical black
1: Enable HREF at optical black
Bit[6]: BLC input selection
0: Use electrical black line as BLC signal
1: Use optical black line as BLC signal
0F COM6 43 RW
Bit[5:4]: Reserved
Bit[3]: Enable bias for ADBLC
Bit[2]: ADBLC offset
0: Use 4-channel ADBLC
1: Use 2-channel ADBLC
Bit[1]: Reset all timing when format changes
Bit[0]: Enable ADBLC option

Exposure Value
10 AECH 40 RW Bit[7:0]: AEC[9:2] (see registers AECHH for AEC[15:10] and
COM1 for AEC[1:0])

Data Format and Internal Clock

Bit[7]: Digital PLL option
0: Disable double clock option, meaning the maximum
PCLK can be as high as half input clock
11 CLKRC 00 RW 1: Enable double clock option, meaning the maximum
PCLK can be as high as input clock
Bit[6]: Use external clock directly (no clock pre-scale available)
Bit[5:0]: Internal clock pre-scalar
F(internal clock) = F(input clock)/(Bit[5:0]+1)
• Range: [0 0000] to [1 1111]

Common Control 7
Bit[7]: SCCB Register Reset
0: No change
1: Resets all registers to default values
Bit[6]: Reserved
12 COM7 00 RW Bit[5]: Output format - CIF selection
Bit[4]: Output format - QVGA selection
Bit[3]: Output format - QCIF selection
Bit[2]: Output format - RGB selection
Bit[1]: Reserved
Bit[0]: Output format - Raw RGB (COM7[2] must be set high)

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 8
Bit[7]: Enable fast AGC/AEC algorithm
Bit[6]: AEC - Step size limit
0: 1/16 x AEC
1: Step size = AEC
13 COM8 8F RW Bit[5]: Banding filter ON/OFF - In order to turn ON the banding
filter, BD50ST (0x9D) or BD60ST (0x9E) must be set to a
non-zero value.
Bit[4:3]: Reserved
Bit[2]: AGC Enable
Bit[1]: AWB Enable
Bit[0]: AEC Enable

Common Control 9
Bit[7]: Reserved
Bit[6:4]: Automatic Gain Ceiling - maximum AGC value
000: 2x
001: 4x
010 8x
011: 16x
100: 32x
14 COM9 4A RW 101 64x
110: 128x
111: 128x
Bit[3]: Reserved
Bit[2]: Data format - VSYNC drop option
0: VSYNC always exists
1: VSYNC will drop when frame data drops
Bit[1]: Enable drop frame when AEC step is larger than VSYNC
Bit[0]: Freeze AGC/AEC

Common Control 10
Bit[7]: Reserved
Bit[6]: HREF changes to HSYNC
Bit[5]: PCLK output option
0: PCLK always output
15 COM10 00 RW 1: No PCLK output when HREF is low
Bit[4]: PCLK reverse
Bit[3]: HREF reverse
Bit[2]: Reserved
Bit[1]: VSYNC negative
Bit[0]: HSYNC negative

16 RSVD XX – Reserved

Output Format - Horizontal Frame (HREF column) start high 8-bit (low
17 HSTART 11 RW
3 bits are at HREF[2:0])

Output Format - Horizontal Frame (HREF column) end high 8-bit (low
18 HSTOP 61 RW
3 bits are at HREF[5:3])

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Output Format - Vertical Frame (row) start high 8-bit (low 2 bits are at
19 VSTRT 02 RW
VREF[1:0])

Output Format - Vertical Frame (row) end high 8-bit (low 2 bits are at
1A VSTOP 7A RW
VREF[3:2])

Data Format - Pixel Delay Select (delays timing of the D[7:0] data relative
to HREF in pixel units)
1B PSHFT 00 RW
• Range: [00] (no delay) to [FF] (256 pixel delay which accounts for
whole array)

1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)

1D MIDL A2 R Manufacturer ID Byte – Low (Read only = 0xA2)

Mirror/VFlip Enable
Bit[7]: 2x gain
Bit[6]: Reserved
Bit[5]: Mirror
1E MVFP 00 RW 0: Normal image
1: Mirror image
Bit[4]: VFlip enable
1: VFlip enable
Bit[3:0]: Reserved

1F LAEC 00 RW Reserved

B Channel ADBLC Result

Bit[7]: Offset adjustment sign
20 BOS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range (high 7 bits)

Gb channel ADBLC result

Bit[7]: Offset adjustment sign
21 GBOS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range

Gr channel ADBLC result

Bit[7]: Offset adjustment sign
22 GROS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range

R channel ADBLC result

Bit[7]: Offset adjustment sign
23 ROS 80 RW 0: Add offset
1: Subtract offset
Bit[6:0]: Offset value of 10-bit range

24 AEW 78 RW AGC/AEC - Stable Operating Region (Upper Limit)

25 AEB 68 RW AGC/AEC - Stable Operating Region (Lower Limit)

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Omni ision Register Set

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

AGC/AEC Fast Mode Operating Region

26 VPT D4 RW Bit[7:4]: High nibble of upper limit
Bit[3:0]: High nibble of lower limit

B Channel Signal Output Bias (effective only when COM6[3] = 1)

Bit[7]: Bias adjustment sign
27 BBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range

Gb Channel Signal Output Bias (effective only when COM6[3] = 1)

Bit[7]: Bias adjustment sign
28 GbBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range

29 RSVD XX – Reserved

Dummy Pixel Insert MSB

Bit[7]: Reserved
2A EXHCH 00 RW Bit[6:4]: 3 MSB for dummy pixel insert in horizontal direction
Bit[3:2]: HSYNC falling edge delay 2 MSB
Bit[1:0]: HSYNC rising edge delay 2 MSB

Dummy Pixel Insert LSB

2B EXHCL 00 RW
8 LSB for dummy pixel insert in horizontal direction

R Channel Signal Output Bias (effective only when COM6[3] = 1)

Bit[7]: Bias adjustment sign
2C RBIAS 80 RW 0: Add bias
1: Subtract bias
Bit[6:0]: Bias value of 10-bit range

2D ADVFL 00 RW LSB of insert dummy lines in vertical direction (1 bit equals 1 line)

2E ADVFH 00 RW MSB of insert dummy lines in vertical direction

2F YAVE 00 RW Y/G Channel Average Value

30 HSYST 08 RW HSYNC Rising Edge Delay (low 8 bits)

31 HSYEN 30 RW HSYNC Falling Edge Delay (low 8 bits)

HREF Control
Bit[7:6]: HREF edge offset to data output
32 HREF A4 RW
Bit[5:3]: HREF end 3 LSB (high 8 MSB at register HSTOP)
Bit[2:0]: HREF start 3 LSB (high 8 MSB at register HSTART)

Array Current Control

33 CHLF 00 RW
Bit[7:0]: Reserved

Array Reference Control

34 ARBLM 03 RW
Bit[7:0]: Reserved

35-36 RSVD XX – Reserved

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

ADC Control
Bit[7:4]: Reserved
Bit[3]: ADC range adjustment
0: 1x range
37 ADC 04 RW 1: 1.5x range
Bit[2:0]: ADC range adjustment
000: 0.8x
100: 1x
111: 1.2x

ADC and Analog Common Mode Control

Bit[7:4]: Reserved
38 ACOM 12 RW
Bit[3:2]: ADC offset positive to make output greater than zero
Bit[1:0]: Reserved

ADC Offset Control

Bit[7:4]: Reserved
39 OFON 00 RW Bit[3]: Line buffer power down - must be set to "1" before chip
power down
Bit[2:0]: Reserved

Line Buffer Test Option

Bit[7:5]: Reserved
Bit[4]: UV output value
0: Use normal UV output
1: Use fixed UV value set in registers MANU and MANV
as UV output instead of chip output
3A TSLB 0C RW Bit[3:2]: Output sequence
00: Y U Y V
01: Y V Y U
10: V Y U Y
11: U Y V Y
Bit[1]: Reserved
Bit[0]: Data output window reset enable

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 11
Bit[7]: Night mode
0: Night mode disable
1: Night mode enable - If the AGC gain goes over 2, then
AGC gain drops to 0 and frame rate changes by half.
COM11[6:5] limits the minimum frame rate. Also,
ADVFH and ADVFL will be automatically updated.
Bit[6:5]: Night mode insert frame option
3B COM11 00 RW 00: Normal frame rate
01: 1/2 frame rate
10: 1/4 frame rate
11: 1/8 frame rate
Bit[4]: Reserved
Bit[3]: Banding filter value select
0: Select BD60ST[7:0] (0x9E) as Banding Filter Value
1: Select BD50ST[7:0] (0x9D) as Banding Filter Value
Bit[2:0]: Reserved

Common Control 12
Bit[7]: HREF option
0: No HREF when VREF is low
3C COM12 40 RW 1: Always has HREF
Bit[6:3]: Reserved
Bit[2]: Enable UV average
Bit[1:0]: Reserved

Common Control 13
Bit[7:6]: Gamma selection for signal
00: No gamma function
01: Gamma used for Y channel only
10: Gamma used for Raw data before interpolation
3D COM13 99 RW
11: Not allowed
Bit[5]: Reserved
Bit[4]: Enable color matrix for RGB or YUV
Bit[3]: Enable Y channel delay option
Bit[2:0]: Output Y/UV delay

Common Control 14
3E COM14 0E RW
Bit[7:0]: Reserved

Edge Enhancement Adjustment

Bit[7:2]: Edge enhancement threshold[7:2]
3F EDGE 88 RW
Bit[1:0]: Edge enhancement factor[3:2] (see register DSPC2[7:6]
for Edge enhancement factor[1:0])

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OV7660/OV7161 CMOS VGA (OmniPixel™) CAMERACHIP™ Omni ision

Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

Common Control 15
Bit[7:6]: Data format - output full range enable
0x: Output range: [10] to [F0]
10: Output range: [01] to [FE]
11: Output range: [00] to [FF]
40 COM15 C0 RW Bit[5:4]: RGB 555/565 option (must set COM7[2] = 1 and
COM7[0] = 0)
x0: Normal RGB output
01: RGB 565
11: RGB 555
Bit[3:0]: Reserved

Common Control 16
Bit[7:6]: Reserved
Bit[5]: Enable edge enhancement for YUV output (effective only
for YUV/RGB, no use for Raw data)
Bit[4]: Edge enhancement option
41 COM16 10 RW 0: Edge enhancement factor = (EDGE[1:0], DSPC2[7:6])
1: Edge enhancement factor =
2 x (EDGE[1:0], DSPC2[7:6])
Bit[3:2]: Reserved
Bit[1]: Color matrix coefficient double option
Bit[0]: RB average option for interpolation

Common Control 17
Bit[7:3]: Reserved
42 COM17 08 RW Bit[2]: Select single frame out
Bit[1]: Tri-state output after single frame out
Bit[0]: Reserved

43-4E RSVD XX – Reserved

4F MTX1 58 RW Matrix Coefficient 1

50 MTX2 48 RW Matrix Coefficient 2

51 MTX3 10 RW Matrix Coefficient 3

52 MTX4 28 RW Matrix Coefficient 4

53 MTX5 48 RW Matrix Coefficient 5

54 MTX6 70 RW Matrix Coefficient 6

55 MTX7 40 RW Matrix Coefficient 7

56 MTX8 40 RW Matrix Coefficient 8

57 MTX9 40 RW Matrix Coefficient 9

Matrix Coefficient Sign for coefficient 9 to 2

58 MTXS 0F RW 0: Plus
1: Minus

59-61 RSVD XX – Reserved

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Table 5 Device Control Register List (Continued)

Address Register Default

(Hex) Name (Hex) R/W Description

62 LCC1 00 RW Lens Correction Option 1

63 LCC2 00 RW Lens Correction Option 2

64 LCC3 10 RW Lens Correction Option 3

65 LCC4 80 RW Lens Correction Option 4

Lens Correction Control

Bit[7:3]: Reserved
66 LCC5 00 RW Bit[2]: Lens correction control select
Bit[1]: Reserved
Bit[0]: Lens correction enable

67 MANU 80 RW Manual U Value (effective only when register TSLB[4] is high)

68 MANV 80 RW Manual V Value (effective only when register TSLB[4] is high)

Manual Banding Filter MSB

Bit[7:6]: B channel pre-gain
69 HV 00 RW Bit[5:4]: R channel pre-gain
Bit[3:1]: Reserved
Bit[0]: Matrix coefficient 1 sign

6A GGAIN 00 RW Reserved

Band Gap Reference Adjustment

6B DBLV 3A RW Bit[7:4]: Reserved
Bit[3:0]: Band gap reference adjustment

6C-7B GSP XX RW Gamma curve

7C-8A GST XX RW Gamma curve

8B-91 RSVD XX – Reserved

92 DM_LNL 00 RW Dummy Line low 8 bits

93 DM_LNH 00 RW Dummy Line high 8 bits

94-9C RSVD XX – Reserved

50 Hz Banding Filter Value

9D BD50ST 99 RW
(effective only when COM8[5] is low and COM11[3] is high)

60 Hz Banding Filter Value

9E BD60ST 7F RW
(effective only when COM8[5] is low and COM11[3] is low)

9F RSVD XX – Reserved

DSP Control 2
Bit[7:6]: Edge enhancement factor[1:0] (see register EDGE[1:0] for
A0 DSPC2 00 RW
Edge enhancement factor[3:2])
Bit[5:0]: Reserved

A1-A5 RSVD XX – Reserved

NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.

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Package Specifications
The OV7660/OV7161 uses a 22-ball Chip Scale Package (CSP). Refer to Figure 15 for package information, Table 6 for
package dimensions and Figure 16 for the array center on the chip.

Note: For OVT devices that contain lead, all part marking letters are
upper case. For OVT devices that are lead-free, all part marking letters
are lower case

Figure 15 OV7660/OV7161 Package Specifications

Pin Indicator
A
S1 J1
1 2 3 4 5 S2 5 4 3 2 1

A A

B B
J2
B C C

D D

E E

Center of BGA (Die) =

Top View (Bumps Down) Bottom View (Bumps Up)
Center of the package
Glass
Die C3
C2

C
C1 Side View

Table 6 OV7660/OV7161 Package Dimensions

Parameter Symbol Minimum Nominal Maximum Unit

Package Body Dimension X A 4130 4155 4180 µm
Package Body Dimension Y B 3950 3975 4000 µm
Package Height C 760 820 880 µm
Ball Height C1 150 180 210 µm
Package Body Thickness C2 605 640 675 µm
Thickness of Glass Surface to Wafer C3 400 420 440 µm
Ball Diameter D 320 350 380 µm
Total Pin Count N 22
Pin Count X-axis N1 5
Pin Count Y-axis N2 5
Pins Pitch X-axis J1 700 µm
Pins Pitch Y-axis J2 700 µm
Edge-to-Pin Center Distance Analog X S1 647.5 677.5 707.5 µm
Edge-to-Pin Center Distance Analog Y S2 557.5 587.5 617.5 µm

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Omni ision Package Specifications

Sensor Array Center

Figure 16 OV7660/OV7161 Sensor Array Center

A1 A2 A3 A4 A5
2755 µm

Array Center
2049 µm (189.8 µm, 189.3 µm)

Package Center
Sensor
(0,0)
Array

OV7660/OV7161

NOTES: 1. This drawing is not to scale and is for reference only.

2. As most optical assemblies invert and mirror the image, the chip is typically mounted
with pins A1 to A5 oriented down on the PCB.

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IR Reflow Ramp Rate Requirements

OV7660/OV7161 Lead-Free Packaged Devices

Note: For OVT devices that are lead-free, all part marking letters are
lower case

Figure 17 IR Reflow Ramp Rate Requirements

300.0
Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
280.0

260.0

240.0

220.0

200.0

180.0
Temperature (∞C )

160.0

140.0

120.0

100.0

80.0

60.0

40.0

20.0
0.0 0.6 1.1 1.6 2.2 2.8 3.3 3.9
0.0
-22 -2 18 38 58 78 98 118 138 158 178 198 218 238 258 278 298 318 338 358 369
Time (sec)

-0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
Time (min.)

Table 7 Reflow Conditions

Condition Exposure
Average Ramp-up Rate (30°C to 217°C) Less than 3°C per second
> 100°C Between 330 - 600 seconds
> 150°C At least 210 seconds
> 217°C At least 30 seconds (30 ~ 120 seconds)
Peak Temperature 245°C
Cool-down Rate (Peak to 50°C) Less than 6°C per second
Time from 30°C to 255°C No greater than 390 seconds

Environmental Specifications
Table 8 OV7660/OV7161 Reliability Test Results

Parameter Test Condition

Temperature/Humidity 85°C/85% Relative Humidity, 1000 hrs.a
Temperature Cycling (Air-to-Air) -25°C / +125°C, 72 cycles/day, 1000 cyclesa
Highly Accelerated Stress Test (HAST) 110°C / 85% Relative Humidity, 168 hrs.a
High Temperature Storage (HTS) 150°C, 1000 hrs.a
High Temperature Static Bias (HTSB) 125°C, 1000 hrs.a
a. Pre-Condition (Moisture Level II): 125°C, 24h → 85°C/60% RH/168h → IR Reflow 235°C, 10 sec, 3 cycles

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Note:

• All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.

• OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).

• Reproduction of information in OmniVision product documentation and specifications is

permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.

• This document is provided with no warranties whatsoever, including any warranty of

merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.

• ‘OmniVision’, ‘CameraChip’ are trademarks of OmniVision Technologies, Inc. All other trade,
product or service names referenced in this release may be trademarks or registered trademarks of
their respective holders. Third-party brands, names, and trademarks are the property of their
respective owners.

For further information, please feel free to contact OmniVision at info@ovt.com.

OmniVision Technologies, Inc.

1341 Orleans Drive
Sunnyvale, CA USA
(408) 542-3000

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26 Proprietary to OmniVision Technologies Version 1.91, January 24, 2005