EE Department DSD

PRACTICAL WORK BOOK

For The Course
Digital System Design

For

B.E. Electrical Engineering

Group Members

Degree Syndicate

Complied By: Checked By:

Lab. Engineer Azmat Saeed Dr. Usman

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Standard Equipments and Components;

Software:
1) Xilinx
2) Modelsim

Hardware:
FPGA kit

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List Of Experiments

S.NO. TITLE OF EXPERIMENT Page No

01 Introduction To Modelsim &Xilinx 4
02 Design of Half Adder, Full Adder, 4 bit Adders at various 13
abstraction levels
03 Implementation of sequential circuits 15
04 Introduction and use of Xilinx cores including math 16
functions
05 Design and Simulation of Arithmetic Logic Unit 17
06 Introduction to FPGA 19
07 Implementation of ALU on FPGA 20
08 ASM design of four 1s detected problem 22
9 Simulation of a Shift-and-Add Multiplier Circuit using 24
Algorithmic State Machine
10 Simulation of an Enhanced Divider Circuit using 26
Algorithmic State Machine
11 Implementation of Time-Shared Architecture for FIR Filter 28
12 Design of Micro Programmed State Machine 29
13 VGA Port Interfacing 31

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Lab#1: Introduction to ModelSim/Xilinx

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

Step 1
Find the Xilinx ISE 12.1 shortcut on desktop and run the program. This opens the
following window on your screen.

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There are 3 main panes, SOURCES, PROCESSES and TRANSCRIPT. SOURCES pane
lists all your source files in proper hierarchy (as long as files are instantiated properly)
and for different purposes of simulation and synthesis. PROCESSES pane lists all the
processes that can be run on the files and TRANSCRIPT pane gives a log of all the
commands run. The errors/warnings in code can also be looked at in the TRANSCRIPT
pane.

Step 2
Create a new project in Xilinx ISE 12.1 as described below.

a.Click on FILE >> NEW PROJECT. A window pops-up.

b. Type Lab01 as project name (You can give the project any name you want to). Set the
work-directory for project and select HDL for Top-Level Source Type field.
c. Click on NEXT.

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d. On the next screen, you can select your target device. Set the options as per the picture
below and then click on NEXT. (This will be covered later in the course)

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e.Create New Source:click on the NEW SCREEN button to create a new source file
automatically where the tool writes the first few lines of code automatically mentioning
the ports, their size and direction.

f. Select VERILOG MODULE from different file types on the left-hand menu. In the file
name field, type the name of Verilog file e.g. Lab01. Click on NEXT.

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g. Type the names of the input/output ports and select their type from the Direction
dropdown
list.
Input ports for this module are
A, B, C and D which are all 1-bit inputs
Outputs for this module are E and F which are also a1-bit signals.
Then click on NEXT.

h. On the next screen, click on FINISH. Xilinx will ask for permission to create the target
work-directory for the project (if not already there).

When the file is created/added, it is listed in the SOURCES pane.

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The PROCESSES pane lists the processes that can be performed on this file.
Since, we are only interested in simulation at this stage, change the
SYNTHESIS/IMPLEMENTATION option to SIMULATION.

Since, we are only interested in simulation at this stage, change the

SYNTHESIS/IMPLEMENTATION option to SIMULATION.Note the list of processes
in the PROCESSES pane changed by changing the option to SIMULATION

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Write the following code in a new source-file.

To test the functionality of the written code, we’ll write another code which provides test
signals for the inputs in our circuit. In the SOURCES pane, right-click and select NEW
SOURCE.New Source Wizard window pops up. Create the testbenchfile.Remember that
the testbench does not have any ports. The code for testbench is as follows.

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Note the hierarchy changing in the SOURCES pane. Since, testbench is ‘calling’
“combo_boolean”, it is shown as the top-level file in hierarchy.
In Verilog HDL, the process of calling another module is called “Instantiation”.

In the SOURCES pane, select the testbench file and see the available processes for it.

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Click on SIMULATE BEHAVIORAL MODEL to start the simulation.

After clicking on SIMULATE BEHAVIORAL MODEL, ModelSim SE 6.5 is launched

which simulates the circuit. It opens a number of windows which are briefly explained by
their window title.

Task 1:
Design a 4 to 1 multiplexer circuit and implement it in modelsim. Make a test bench for
simulation.
Task 2:
Design a 4 to 1 multiplexer circuit and implement it in Xilinx. Make a test bench for
simulation.

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Lab#2: Design of Half Adder, Full Adder, 4 bit Adders at various

abstraction levels

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

Objective;
In this lab you will learn:
• modeling at Gate level
• modeling at Dataflow level
• modeling at Behavioral level

Part (A);
Write Verilog code/module in Gate level, Data flow level and Behavioral level for
Half and Full Adder.
Background;
The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise
addition between two input bits. Depending on the result of the operation, the HA either
sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for
carry—in, and the modified unit is called the Full Adder (FA).

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1) Gate level Design;

At gate level, the circuit is described in terms of gates (e.g; and, or, xor). Hardware
design at this level is intuitive for a user with a basic knowledge of digital logic design because it
is possible to see a one-to-one correspondence between the logic circuit diagram and the
Verilog description.

2) Dataflow level Design;

Dataflow modeling provides a powerful way to implement a design. Verilog allows a
circuit to be designed in terms of the data flow between registers and how a design processes
data rather than instantiation of individual gates.

3) Behavioral level Design

With the increasing complexity of digital design, it has become vitally important to make
wise design decisions early in a project. Designers need to be able to evaluate the trade-offs of
various architectures and algorithms before they decide on the optimum architecture and
algorithm to implement in hardware. Thus, architectural evaluation takes place at an algorithmic
level where the designers do not necessarily think in terms of logic gates or data flow but in
terms of the algorithm they wish to implement in hardware. They are more concerned about
the behavior of the algorithm and its performance. Only after the high-level architecture and
algorithm are finalized, do designers start focusing on building the digital circuit to implement
the algorithm. Verilog provides designers the ability to describe design functionality in an
algorithmic manner. In other words, the designer describes the behavior of the circuit. Thus,
behavioral modeling represents the circuit at a very high level of abstraction.

Tasks :
1) Write a Verilog code for Half adder, Full adder and 4-bit adder at various
abstraction level.
2) Write a test bench for verifying the functionality.

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Lab#3: Implementation of sequential circuits

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

Objective
In this lab, you will build:
1) implementation of 4-bit Up/Down Counter
2) implementation of universal shift register

Task 1:
Design a 4-bit up/down counter and write a Verilog code for it on
modelsim/Xilinx. Write a test bench code.

en out[3]
clk out[2]
up/down Counter out[1]
out[0]

Task 2:
Design a 4-bit universal shift register and write a Verilog code for it on
modelsim/Xilinx. Write a test bench code.

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Lab#4: Introduction and use of Xilinx cores including math functions

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

Task 1:
(a) Use Xilinx IP Core to simulate a 4-bit adder and subtracter.
(b) Vary the Latency and observe the response.

Task 2:
(a) Use Xilinx IP Core to simulate a 4-bit multiplier.
(b) Vary Latency and observe the response.

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Lab#5: Design and Simulation of Arithmetic Logic Unit

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

DESCRIPTION:

4- bit Multiplier

Comparator

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Task 1:
(a) Design an ALU as shown in the figure above performing the desired set of
functions.
(b) Demonstrate read and write operations for the results on ROM.

Task 2:
(a) Add another memory as shown below that can store the instructions to be
executed.

Program Memory

4x19 ROM
A B S R/W Address
L14 L13 N17 H18

(b) Design a system that takes instruction from the program memory sequentially and
execute them to give the desired results.

1001_0110_01_1_00000001 //Writing difference of first two numbers to the memory

1001_1010_10_1_00000010 //Writing product of first two numbers to the memory
1001_0010_11_1_00000011 //Compares first two numbers and writes the result to memory
0000_0000_00_0_00000001 //Read second memory location
0000_0000_00_0_00000010 //Read third memory location
0000_0000_00_0_00000011 //Read fourth memory location

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Lab#6: Introduction to FPGA

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

Task: Implement a two bit adder taking input from the onboard slider switches
and display the result on FPGA.

Step 1: Writing Verilog code of the circuit we want to implement

Step 2: Simulating the Verilog code using a simulator (ModelSim/Xilinx) to check

if the intended functionality has been achieved

Step 3: Use Xilinx PlanAhead tool to assign input and output ports to the input
out variables so it can generate a user constraint file (.ucf).

Step 3: Synthesizing the Verilog code using a tool form Xilinx called ISE so that it
can be programmed onto an FPGA

Step 4: Program the Verilog code on the FPGA.

Step 5: Applying inputs to and observing outputs from our circuit using the
peripherals (like switches, buttons, LEDs, etc) on the FPGA board

Button 1 Button 2 Button 3 Button 4

L14 L13 N17 H18

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Lab#7: Implementation of ALU on Spartan 3E

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

DESCRIPTION:

4- bit Multiplier

Comparator

4x12 ROM
A B S R/W Address

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Task:
(a) Simulate the Verilog code using a simulator (ModelSim/Xilinx) to check if the
intended functionality has been achieved

(b) Synthesize the Verilog code using a tool form Xilinx called ISE so that it can be
programmed onto an FPGA

(c) Assign the desired input outputs to the respective hardware pins.

(d) Program the Verilog code on the FPGA

Note: Use 50MHz clock extracted from C9 pin of Spartan 3E to decrease the frequency
upto 1Hz, for ROM input.

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Lab#8: ASM representations of four 1s detected problem

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

Introduction to ASM

ASM is a flowchart like graphical notation that describes the cycle by cycle behavior of
an algorithm. Each step transitioning from one state to another or to the same state takes
one clock cycle. The ASM is composed of three basic building blocks: rectangles,
diamonds and ovals. Arrows are used to interconnect these building blocks. Each
rectangle represents a state and the state output is written inside the rectangle. The state
output is always an unconditional output, which is asserted when the FSM transitions to a
state represented by the respective rectangle. A diamond is used for specifying a
condition. Based on whether the condition is TRUE or FALSE, the next state or
conditional output is decided. An oval is used to represent a conditional output. As Moore
machines only have state outputs, Moore FSM implementations do not have ovals, but
Mealy machines may contain ovals in their ASM representations. Figure 9.13 shows the
relationship of three basic components in an ASM representation. For TRUE or FALSE,
T and F are written on respective branches. The condition may terminate in an Oval,
which lists conditional output.

Figure 1

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Task 1:
Write Verilog code for 4-entry FIFO system by Mealy and Moore State Machines.
Simulate the code and demonstrate the results. ASM chart is shown in the figure

Figure 1 (a) Mealy Machine (b) Moore Machine

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Lab#9: Simulation of a Shift-and-Add Multiplier Circuit using

Algorithmic State Machine

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

The objective is to write and simulate the Verilog code for the multiplication of two
binary numbers using state machine. The Pseudo Code, ASM chart and Data Path are
shown below

(a) Pseudo-code

(b) Data Path Circuit for Multiplier

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(b) ASM Chart

Task: Write a Verilog code for the design shown above. Multiply two 4-bit numbers and
demonstrate the output using simulation results.

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Lab#10: Simulation of an Enhanced Divider Circuit using Algorithmic

State Machine

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

The objective is to write and simulate the Verilog code for the multiplication of two
binary numbers using state machine. The Pseudo Code, ASM chart and Data Path are
shown below

(a) Pseudo-code

(b) Data Path Circuit for Multiplier

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(b) ASM Chart

Task: Write a Verilog code for the design shown above. Divide two 4-bit numbers and
demonstrate the output using simulation results.

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Lab#11: Implementation of Time shared architecture of FIR Filter

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

A time shared architecture design is shown in the figure:

reg

Figure 1

Task 1: Implement the time-shared architecture of FIR filter as shown above. Write a
Verilog code and demonstrate the results:

x[n] = 0000000001111101010101010000111110000

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Lab#12: Micro Programmed State Machine Design

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

The objective is to design, simulate and implement a micro-coded state machine as

shown in the figure:

Figure 1
The design supports a program that uses the following set of micro codes:
+,-,AND,OR
if(N) jump label
if(!N) jump label
if(Z) jump label
if(!Z) jump label
jump label
Register = value
The following diagrams show Non-overlapping fields and Overlapping fields (to reduce
the width of the PM) in the micro code of programmable state machine , respectively

Figure 2

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Task 1: Design the micro programmed state machine and execute the following set of
instructions

label0 : R0 = 50
R1 = -7
R2 = R0+R1
label1: R2 = R2+R1
if(!N)
jump label1

Note: Add extra logic for writing data to the registers R7…R0
Registers R7…R0 are 8-bit registers

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Lab#13: VGA Port Interfacing on Spartan 3E

GROUP MEMBERS 1.
2.
3.
DATE
INSTRUCTOR

Task:
(a) Read and understand the VGA specification.
(b) Display exclamation mark sign (‘!’) using color bars on the LCD.

VGA Basics
The term VGA really means one of two things depending on how you use the acronym.
It’s either a standard 15-pin connector used to drive video devices (e.g. a VGA cable) or
it’s the protocol used to drive information out on that cable (e.g. a VGA interface spec.).
The interface defines how information is sent across the wires from your board to the
VGA device. The cable defines which pins you use on the standard connector for those
signals. There are some slides on VGA on the class web site, and there is a nice
description of VGA (both the connector and the protocol) in the Spartan3E board User
Guide, also linked to the class web site. The most basic thing to know about VGA is that
it is a protocol designed to be used with analog CRT (cathode ray tube) output devices.
On these devices the electron beam moves across the screen from left to right as you’re
looking at the screen at a fixed rate (the refresh rate defines how fast the beam moves),
and also moves down the screen from top to bottom at a fixed rate. While it’s moving
across and down the screen, you can modify the Red, Green, and Blue values on the
VGA interface to control what color is being painted to the screen at the current location.
So, painting a certain color on the screen is as easy as keeping track of where the beam is,
and making sure the R, G, and B signals are at the right values when the beam is over the
point on the screen where you want that color. If you don’t do anything to stop it, the
beam will move to the right and bottom of the screen and get stuck there. You can force
the beam to move back to the left by asserting an active-low signal called hSync
(horizontal sync). You can force the beam to move back to the top of the screen by
asserting an active-low signal called vSync (vertical sync). Because the beam moves at a
fixed.rate (defined by the monitor’s refresh rate), you can keep track of where the beam is
on the screen by counting clock ticks after the hSync and vSync signals. So, the basics of
the VGA control/timer circuit are just a pair of counters to count horizontal ticks and
vertical ticks of the VGA clock. How many ticks are there? That depends on how fast
your clock is, and how many pixels you want to paint during the time the beam moves
across the screen. The basic (ancient) standard for “plain” VGA is 640 pixels on each
line, and 480 lines down the screen. This is “640x480” mode. Figure 1 shows a 640x480
screen, and the horizontal sync (hSync) timing required to make it work. After the hSync
pulse, you must wait for a certain number of ticks before painting pixels to the screen.
This gives the beam time to get back to the left and start moving forward again. This time
is called the “back porch” because it’s in back of the hSync timing pulse. Then you count
640 pixels as the beam moves. After the 640th pixel, you wait for some amount of time

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(this is the “front porch” because it’s in front of hSync), then assert the hSync signal
(asserted low) for a certain amount of time. Note that the figure in the Spartan3e .

The timing for all this depends on the monitor refresh rate. For a monitor with 60Hz
refresh in 640x480 mode and a 25MHz pixel clock, you can use the timings in Figure 2.
The timings in this figure define the display time (the time when the pixel is one of the
640 visible pixels in a line), pulse width (hSync or vSync), and the front porch and back
porch timings. These times (in µs or ms) can also be measured in terms of the number of
ticks of the 25MHz pixel clock, or in terms of the number of horizontal lines. That is, the
vertical timing can be measured in terms of how many hSync pulses have been seen. The
bottom line is that both the horizontal and vertical timing for the vgaControl are just
counters. You may have to enable things or reset things or change things when the
counters get to a certain value, but basically they’re just counters.

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