Half Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is
begin
s <= x xor y;
c <= x and y;
end Behavioral;
Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY halfadder_tb IS
END halfadder_tb;
ARCHITECTURE behavior OF halfadder_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT halfadder
PORT(
x : IN std_logic;
y : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic := '0';
signal y : std_logic := '0';
--Outputs
signal s : std_logic;
signal c : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: halfadder PORT MAP (
x => x,
y => y,
s => s,
c => c
);
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
x <= not x;
end process;
stim_procl: process
begin
wait for 50 ns;
y <= not y;
end process;
END;
Output
Full Adder
Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end FA;
architecture Behavioral of FA is
begin
process(x,y,z)
begin
if(x='0' and y='0' and z='0') then
s <= '0';
c <= '0';
elsif(x='0' and y='0' and z='1') then
s <= '1';
c <= '0';
elsif(x='0' and y='1' and z='0') then
s <= '1';
c <= '0';
elsif(x='0' and y='1' and z='1') then
s <= '0';
c <= '1';
elsif(x='1' and y='0' and z='0') then
s <= '1';
c <= '0';
elsif(x='1' and y='0' and z='1') then
s <= '0';
c <= '1';
elsif(x='1' and y='1' and z='0') then
s <= '0';
c <= '1';
elsif(x='1' and y='1' and z='1') then
s <= '1';
c <= '1';
end if;
end process;
end Behavioral;
Data FLow
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FA_TB IS
END FA_TB;
ARCHITECTURE behavior OF FA_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FA
PORT(
x : IN std_logic;
y : IN std_logic;
z : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic := '0';
signal y : std_logic := '0';
signal z : std_logic := '0';
--Outputs
signal s : std_logic;
signal c : std_logic;
BEGIN
uut: FA PORT MAP (
x => x,
y => y,
z => z,
s => s,
c => c
);
process1: process
begin
wait for 100 ns;
x <= not x;
end process;
process2: process
begin
wait for 50 ns;
y <= not y;
end process;
process3: process
begin
wait for 25 ns;
z <= not z;
end process;
END;
Structural
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : in STD_LOGIC;
s : out STD_LOGIC;
c : out STD_LOGIC);
end FA;
architecture Structural of FA is
component HA
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
m : out STD_LOGIC;
n : out STD_LOGIC);
end component;
component ORG
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
r : out STD_LOGIC);
end component;
signal hs, hc1, hc2 : STD_LOGIC;
begin
HA1: HA port map ( x, y, hs, hc1);
HA2: HA port map ( hs, z, s, hc2);
ORG1: ORG port map ( hc1, hc2, c);
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity HA is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
m : out STD_LOGIC;
n : out STD_LOGIC);
end HA;
architecture BehaviorHA of HA is
begin
m <= a xor b;
n <= a and b;
end BehaviorHA;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ORG is
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
r : out STD_LOGIC);
end ORG;
architecture BehaviorOR of ORG is
begin
r <= p or q;
end BehaviorOR;
Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY FA_TB IS
END FA_TB;
ARCHITECTURE behavior OF FA_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FA
PORT(
x : IN std_logic;
y : IN std_logic;
z : IN std_logic;
s : OUT std_logic;
c : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic := '0';
signal y : std_logic := '0';
signal z : std_logic := '0';
--Outputs
signal s : std_logic;
signal c : std_logic;
BEGIN
uut: FA PORT MAP (
x => x,
y => y,
z => z,
s => s,
c => c
);
process1: process
begin
wait for 100 ns;
x <= not x;
end process;
process2: process
begin
wait for 50 ns;
y <= not y;
end process;
process3: process
begin
wait for 25 ns;
z <= not z;
end process;
END;
Output
Parallel Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PA is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C0 : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
C4 : out STD_LOGIC);
end PA;
architecture Structural of PA is
component FA is
port(
a, b, c: IN STD_LOGIC;
sum: OUT STD_LOGIC;
carry: out STD_LOGIC);
end component;
signal C1, C2, C3: STD_LOGIC;
begin
FA0 : FA port map(a => A(0), b => B(0), c => C0, sum => S(0), carry => C1);
FA1 : FA port map(a => A(1), b => B(1), c => C1, sum => S(1), carry => C2);
FA2 : FA port map(a => A(2), b => B(2), c => C2, sum => S(2), carry => C3);
FA3 : FA port map(a => A(3), b => B(3), c => C3, sum => S(3), carry => C4);
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
port(
a, b, c: IN STD_LOGIC;
carry: out STD_LOGIC;
sum: out STD_LOGIC);
end FA;
architecture Dataflow of FA is
begin
sum <= a xor b xor c;
carry <= (a and b) or (b and c) or (c and a);
end Dataflow;
Test Bench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PA_TB IS
END PA_TB;
ARCHITECTURE behavior OF PA_TB IS
COMPONENT PA
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
C0 : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
C4 : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal C0 : std_logic := '0';
--Outputs
signal S : std_logic_vector(3 downto 0);
signal C4 : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PA PORT MAP (
A => A,
B => B,
C0 => C0,
S => S,
C4 => C4
);
stim_proc_A: process
begin
A<="0100";
wait for 10 ns;
A<="0111";
wait;
end process;
stim_proc_B: process
begin
B<="1111";
wait for 10 ns;
B<="0011";
wait;
end process;
stim_proc_Cin: process
begin
C0<='0';
wait for 10 ns;
wait;
end process;
END;
Output
