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VLSI Design Engineer Profile

Pavithran is seeking a position in VLSI design. He has a M.Tech in VLSI Design from Amrita School of Engineering and B.Tech in Electronics and Communication. He has over 2 years of experience in verification of IP's and tools at Synopsys India using SystemVerilog and UVM. He is proficient in Verilog, SystemVerilog, C, C++ and tools like ModelSim. He has done projects in areas like UVM based verification and image processing.

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Pavi T M
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48 views2 pages

VLSI Design Engineer Profile

Pavithran is seeking a position in VLSI design. He has a M.Tech in VLSI Design from Amrita School of Engineering and B.Tech in Electronics and Communication. He has over 2 years of experience in verification of IP's and tools at Synopsys India using SystemVerilog and UVM. He is proficient in Verilog, SystemVerilog, C, C++ and tools like ModelSim. He has done projects in areas like UVM based verification and image processing.

Uploaded by

Pavi T M
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Pavithran TM

M.Tech in VLSI Design


Phone: +91-9447564009
email :- pavi3401@gmail.com

Work Experience
Jul 2017 - Present Intern (Technical Engineering) at Synopsys India Pvt.Ltd,
Banglore, India
Verification Group
Developed test cases for verification of IP’s (Debug IP) and (HSTDM) which are as-
sociated with Protocompiler tool from Synopsys.Integration of UVM based test-
bench and tool. Writing perl and tcl scripting for running simulations

June 2015 - Mar 2016 Graduate Engineering Trainee at Unity Appliances Ltd, Mana-
madurai, Tamilnadu
Plant Engineering
Employed in Plant maintenance activities, Supervision of installation of various
machines in production line.

Educational Qualification
2016-Present Amrita School of Engineering, Amritapuri Campus.
Masters of Technology in VLSI Design.
Affiliated to Amrita Vishwa Vidyapeetham, Coimbatore.
| Current CGPA : 8.33 / 10

2010-2014 Sreepathy Institute of Management and Technology.


Bachelors of Technology in Electronics and Communication.
Affiliated to Calicut University, Kerala.
| CGPA : 7.6/10

2010 Carmel CMI School, Shoranur, Palakkad, Kerala.


AISSCE.
| percentage : 77.8%

2008 Carmel CMI School, Shoranur, Palakkad, Kerala.


AISSE.
| percentage: 84.2%

Projects
Project III UVM Based Testbench Architecture for Logic Subsystem Verification.
Developed UVM based testbench environment for verification of components
in logic subsystem.
Language: System Verilog
Project II Reversible Data Hiding in Encrypted Images.
Software Used: - Matlab 2010b
Project I Real Time Industry Monitoring System Using GSM.
Area Of Interest
• Technology: Digital VLSI Design, Verification (SV, UVM), STA
• Extra Curricular: Traveller, Bike Riding, Cricket

Technical Proficiency
• Tools: Protocompiler, VCS, Altera Quartus, , Altera Quartus, Xilinx ISE, Model Sim.
• HDL: VeriLog, System Verilog.
• Platforms: Windows XP/7/10, Redhat Linux.
• Languages Known: C, C++, Perl, Tcl
• Protocols Known: AMBA AXI 4

Achievements and Certificates


2017 Attended System Verilog TB training by Synopsys India Pvt.Ltd at Bangalore.
2013-2014 Secretary, Dept. of ECE, SIMAT.
2007-2010 Member of school basketball team.
2008 Participated in CBSE state sports meet - Discuss throw.

Languages
Malayalam: Mothertongue
English: Fluent
Hindi: Basic Knowledge
Tamil: Can Speak

Personal Data
Place and Date of Birth: Kunnamkulam, India | 05 May 1992
Address: Thiyyanoor Mana, Koonathara(P.O), Palakkad(Dist.), Kerala
Father’s Name: T M Parameswaranunni

References
• Available upon request

Date: 06 February 2018 Pavithran T M


Banglore

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