Status Flags Floating-Point, MMX, XMM Registers
• Carry • Eight 80-bit floating-point data registers
• unsigned arithmetic out of range • ST(0), ST(1), . . . , ST(7) ST(0)
• Overflow
• arranged in a stack ST(1)
• signed arithmetic out of range ST(2)
• Sign • used for all floating-point
ST(3)
• result is negative arithmetic
ST(4)
• Zero • Eight 64-bit MMX registers
ST(5)
• result is zero • Eight 128-bit XMM registers for single-
instruction multiple-data (SIMD) operations ST(6)
• Auxiliary Carry
• SIMD (Single Instruction Multiple Data) An ST(7)
• carry from bit 3 to bit 4
architecture with a single point of control that
• Parity
execute the same instruction simultaneously
• sum of 1 bits is an even number on multiple data values. e.g; vector
processors and array processors.
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Intel Microprocessor History Early Intel Microprocessors
• Intel 8080
• 64K addressable RAM
• Intel 8086, 80286 • 8-bit registers
• IA-32 processor family • CP/M (Control Program for Microcomputers)
• P6 processor family operating system
• S-100 BUS architecture
• CISC and RISC
• 8-inch floppy disks!
• Intel 8086/8088
• IBM-PC Used 8088
• 1 MB addressable RAM
• 16-bit registers
• 16-bit data bus (8-bit for 8088)
• separate floating-point unit (8087)
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The IBM-AT Intel IA-32 Family
• Intel 80286
• Intel386
• 16 MB addressable RAM • 4 GB addressable RAM, 32-bit
registers, paging (virtual memory)
• Protected memory
• several times faster than 8086 • Intel486
• introduced IDE bus architecture • instruction pipelining
• 80287 floating point unit • Pentium
• superscalar, 32-bit address bus, 64-bit
internal data path
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1
Intel P6 Family CISC and RISC
• CISC – complex instruction set
• Pentium Pro
• large instruction set
• advanced optimization techniques in • high-level operations
microcode • requires microcode interpreter
• Pentium II • examples: Intel 80x86 family
• MMX (multimedia) instruction set • RISC – reduced instruction set
• Pentium III • simple, atomic instructions
• SIMD (streaming extensions) • small instruction set
instructions • directly executed by hardware
• examples:
• Pentium 4
• ARM (Advanced RISC
• NetBurst micro-architecture (Complete Machines)
redesign), tuned for multimedia • DEC Alpha (now Compaq)
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2
IA-32 Memory Management Real-Address mode
• 1 MB RAM maximum
• Real-address mode addressable
• Calculating linear addresses • Application programs can
• Protected mode access any area of memory
• Multi-segment model • Single tasking
• Paging
• Supported by MS-DOS
operating system
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Segmented Memory Calculating Linear Addresses
Segmented memory addressing: absolute (linear)
address is a combination of a 16-bit segment value • Given a segment address, multiply it by
added to a 16-bit offset
16 (add a hexadecimal zero), and add it
F0000 to the offset
• Example: convert 08F1:0100 to a linear
E0000 8000:FFFF
D0000
address
C0000
B0000 one segment
A0000
90000
Adjusted Segment value: 0 8 F 1 0
80000
70000
Add the offset: 0 1 0 0
60000
Linear address: 0 9 0 1 0
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000
seg ofs2003.
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00000
Your turn . . . Your turn . . .
What linear address corresponds to the What segment addresses correspond to the linear
segment/offset address 028F:0030? address 28F30h?
Seg address = (linear – offset ) >>4
028F0 + 0030 = 02920
Many different segment-offset addresses can
produce the linear address 28F30h. For
example:
Always use hexadecimal notation for addresses.
28F0:0030, 28F3:0000, 28B0:0430, . . .
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3
Protected Mode (1 of 2) Protected mode (2 of 2)
• 4 GB addressable RAM • Segment descriptor tables
• (00000000 to FFFFFFFFh) • Program structure
• Each program assigned a memory • code, data, and stack areas
partition which is protected from other
• CS, DS, SS segment descriptors
programs
• global descriptor table (GDT)
• Designed for multitasking
• MASM Programs use the Microsoft
• Supported by Linux & MS-Windows
flat memory model
Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 47 Irvine, Kip R. Assembly Language for Intel-Based Computers, 2003. 48
Flat Segment Model Multi-Segment Model
• Single global descriptor table (GDT). • Each program has a local descriptor table (LDT)
• All segments mapped to entire 32-bit address space • holds descriptor for each segment used by the program
FFFFFFFF RAM
(4GB)
not used
Segment descriptor, in the
Global Descriptor Table
00040000 Local Descriptor Table
base address limit access
00000000 00040
physical RAM
---- 26000
base limit access
00026000 0010
00008000 000A
00003000 0002 8000
00000000
3000
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Paging
• Supported directly by the CPU
• Divides each segment into 4096-byte blocks called
pages
• Sum of all programs can be larger than physical
memory
• Part of running program is in memory, part is on disk
• Virtual memory manager (VMM) – OS utility that
manages the loading and unloading of pages
• Page fault – issued by CPU when a page must be
loaded from disk
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4
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