GOVERNMENT ENGINEERING COLLEGE

TRAINING REPORT
ON
VLSI DESIGN

Submitted by–
Submitted to – Bharat Suthar
Branch – ECE
Training Coordinator Batch – C1
Electronics & Communication Roll No. – 14EEBEC016
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Acknowledgement
I am grateful to Sir H. P. Vyas and Sir Lomesh Acharaya for giving guidelines to
make the training successful and am very thankful to lomesh sir which did hard
work on us. In training i have improved my programming skills and learn
technical things about VSLI.

You’re sincerely

Bharat Suthar
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Training Summary (Abstract)

I have completed a two month summer training form 16/5/2017 to 15/7/2017 in
the field of Digital VLSI Design.
This training was focused on simulation & implementation of digital circuits on
FPGA board using hardware description language.
The training is divided into three parts –
In first part I learned basic about Very Large Scale Integration and various
methods to design a circuit.
In second part I learned about hardware description language and designed some
sequential circuits.
In third part I have designed some sequential circuits such as flip-flop, registers,
memory, counters and finite state machine.
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List of Abbreviation

FPGA Field programmable gate array

VSLI Very-large-scale integration
VHSIC Very High Speed Integrated
Circuit
VHDL VHSIC Hardware Description
Language
RTL Register transfer level
SISO Serial in serial out shift register
Mux Multiplexer
PISO Parallel in parallel out shift
register
FSM Finate state machine
LCD Liquid crystal display
EVM Electronic voting machine
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List of Table

Table Number Page no.

3.1 Truth table of 1-bit Mag comp 40

3.2 2-bit mag comp 47
4.1 Table 1.3-JK Flip Flop 52
4.2 – LCD Commands 68
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List of Figure

Figure no. Page no.

1.1 – FPGA Architecture 10

1.2- FPGA Design flow 12

1.3- Full Custom Layout 17
1.4- Standard cell Layout 18
1.5- Altera FPGA Board (Front 20
View)
1.6- Altera FPGA Board (Back 21
View)
1.7- Block diagram of Altera 21
Board
2.1-Waveform of XOR gate 28
2.2-AND Gate 34
2.3-Mux 35
2.4-Ripple Carry Adder 36
3.1-half adder 38
3.2- Full adder 39
3.3- seven segment 41
3.4-Binary to grey code 42
conversion
3.5-Ripple Carry Adder 44
3.6-16x1 Mux 45
3.7-Encoder 48
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3.8- Waveform of encoder 50

4.1-Block Diagram of 51
Sequential circuit
4.2-RTL level circuit of jk flip 53
flop
4.3-D Flip Flop 54
4.4-SISO 55
4.5-RTL level of SISO 56
4.6-PIPO 56
4.7-RTL level of Ring counter 62
4.8-Johnson Counter 63
4.9- RTL level diagram of 66
sequence detector
4.10-FSM of 1001 67
4.11-LCD 67
5.1-EVM 70
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Contents

Chapter 1:.......................................................................................................9
1.1 What is an FPGA?........................................................................................9
1.2 Why do we need FPGAs? ..........................................................................10
1.3 Steps in VSLI Chip Design ........................................................................11
1.4 Moore’s Law ..............................................................................................14
1.5 Available Implementation Technologies ...................................................15
Chapter 2:.....................................................................................................23
1.1 VHDL :- ....................................................................................................23
2.2 Data Type in VHDL...................................................................................29
2.3 Sequential Processing:- ..............................................................................33
Chapter 3: .....................................................................................................38
3.1 Combinational Circuits ..............................................................................38
3.1.1 Circuit-1:- Desgin a Half-Adder .............................................................38
3.1.2 Circuit-2:-Design a Full-Adder ...............................................................39
3.1.3 Circuit-3:- Design a 1 bit magnitude comparator....................................39
3.1.4 Circuit-4:- Design a BCD code to seven segment ..................................41
3.1.5 Circuit-5:- Design a Binary to grey code conversion and display result on
seven segment. .................................................................................................42
3.1.6 Circuit-6:-Desgin a Ripple Carry adder using structural modelling. ......43
3.1.7 Circuit-7:-Design a 16x1 Mux using 8x1 and 2x1 Mux .........................45
3.1.8 Circuit-8:- Design a 2-bit magnitude comparator ...................................47
3.1.9 Circuit-9:-Design a 8x3 Encoder ............................................................48
Chapter 4:.....................................................................................................51
4.1 Sequential Circuit.......................................................................................51
Flip Flop.............................................................................................................51
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4.1.1 Circuit 1:- Design a JK Flip Flop ............................................................52

4.1.2 Circuit 2:- Design a D-Flip Flop .............................................................53
4.1.3 Circuit 3:- Design a Serial in Serial Out Shift Register. .........................54
4.1.4 Circuit 4:- Design Parallel in Parallel Out Shift Register (PIPO). ..........56
4.1.5 Circuit 5:- Design a up counter. ..............................................................57
4.1.6 Circuit 6:-Design 4-bit UP/down Counter with halt input and display the
result on seven segment. ..................................................................................58
4.1.7 Circuit 7:- Design a Ring Counter. .........................................................60
4.1.8 Circuit 8:- Design a Johnson counter. .....................................................62
4.2 FINATE STATE MACHINCE (FSM) ......................................................64
4.2.1 Circuit 9:- Design a circuit to detect sequence 1001...............................64
4.3 LCD INTERFERNCE................................................................................67
Chapter 5:.....................................................................................................69
5.1 Implemented digital circuits.......................................................................69
5 .2 Electronic Voting Machines......................................................................70
References ....................................................................................................74
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Chapter 1:
1.1 What is an FPGA?
Field Programmable Gate Arrays are two dimensional array of logic blocks and
flip-flops with an electrically programmable interconnections between logic
blocks.
At the highest level, FPGAs are reprogrammable silicon chips. Using prebuilt
logic blocks and programmable routing resources, you can configure these chips
to implement custom hardware functionality without ever having to pick up a
breadboard or soldering iron.
The interconnections consist of electrically programmable switches which is why
FPGA differs from Custom ICs, as Custom IC is programmed using integrated
circuit fabrication technology to form metal interconnections between logic
blocks.
In an FPGA logic blocks are implemented using multiple level low fan-in gates,
which gives it a more compact design compared to an implementation with two-
level AND-OR logic. FPGA provides its user a way to configure:
1. The intersection between the logic blocks and
2. The function of each logic block.
Logic block of an FPGA can be configured in such a way that it can provide
functionality as simple as that of transistor or as complex as that of a
microprocessor. It can used to implement different combinations of
combinational and sequential logic functions. Logic blocks of an FPGA can be
implemented by any of the following:

1. Transistor pairs
2. combinational gates like basic NAND gates or XOR gates
3. n-input Lookup tables
4. Multiplexer’s
5. Wide fan-in And-OR structure

As shown in figure 1.1 below

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FPGA
Architecture

Figure 1.1 – FPGA Architecture

1.2 Why do we need FPGAs?

By the early 1980’s large scale integrated circuits (LSI) formed the back bone
of most of the logic circuits in major systems. Microprocessors, bus/IO
controllers, system timers etc. were implemented using integrated circuit
fabrication technology.

Systems typically consisted of few large scale integrated components and large
number of SSI (small scale integrated circuit) and MSI (medium scale integrated
circuit) components.

Initial attempt to solve this problem led to development of Custom ICs which
were to replace the large amount of interconnect. This reduced system complexity
and manufacturing cost, and improved performance. However, custom ICs have
their own disadvantages. They are relatively very expensive to develop, and delay
 11

introduced for product to market (time to market) because of increased design

time. There are two kinds of costs involved in development of

Custom ICs:

1. cost of development and design

2. Cost of manufacture

Therefore the custom IC approach was only viable for products with very high
volume, and which not time to market sensitive were.

FPGAs were introduced as an alternative to custom ICs for implementing entire

system on one chip and to provide flexibility of reprogramability to the user.
Introduction of FPGAs resulted in improvement of density relative to discrete
SSI/MSI components (within around 10x of custom ICs). Another advantage of
FPGAs over Custom ICs is that with the help of computer aided design (CAD)
tools circuits could be implemented in a short amount of time (no physical layout
process, no mask making, no IC manufacturing).

1.3 Steps in VSLI Chip Design

1.3.1 FPGA Design Flow
Configuration of target device in FPGA design flow in carried out in three steps:

Synthesis

Implement Design

Configuration of target device

Diagram shown as below in figure 1.2

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Test Vector
Design specification

VHDL/Verilog
Behavioral
Codes Design Entry
Simulation
Codes
Device Selection

Synthesis Directive Synthesis

Netlist

Translate

Mapping

Place & Route

Programming Unit

Figure 1.2- FPGA Design flow

1. Design Specification: - Firstly the designer describe the functionality,

interface, working and the architecture of the digital IC circuit to be
designed.
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2. RTL Description: - In this step the designer describe the design in form of
coding. For VLSI many hardware description languages are used. Verilog,
VHDL etc. are example of hardware description language. The coded form
of design is known as RTL description.

3. Functional Verification and Testing: - After writing the HDL code for
design, test vectors are applied to design and simulated. In simulation
process the functionality of design is tested and output is compared with
requirements.

4. Gate-Level Netlist: - RTL description is then converted to a gate-level net

list using logic synthesis tool. The logical representation of RTL is known as
Netlist. Gate-Level Netlist is a description of the circuit in terms of gates
and connections between them. This net list meet the timing, power and
area specifications of design.

5. Floor Planning, Place and Route: - A floor planning is the process of

placing blocks/macros in the chip or semiconductor wafer. Floor plan
determines the size of design and placement of I/O pins. Routing is the
process of making interconnection between different blocks/macros in
design. After completion of this step the complete physical layout of the
design is ready.
6. Layout Verification: - The physical design is then tested and verified.

7. Implementation and Fabrication: - If the verification of physical layout is

successful then the design is ready for implementation and fabrication. In
fabrication process the layout design is fabricated on semiconductor wafer
layer by layer. There are so many steps involved in fabrication process.
After completion of fabrication process, the result is ASIC
8. Layout Verification: - The physical design is then tested and verified.
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9. Implementation and Fabrication: - If the verification of physical layout is

successful then the design is ready for implementation and fabrication. In
fabrication process the layout design is fabricated on semiconductor wafer
layer by layer. There are so many steps involved in fabrication process.
After completion of fabrication process, the result is ASIC (Application
Specific Standard Circuit). This ASIC design is can’t be altered and it is the
final outcome of VLSI chip design process.

10.Packaging, Testing and Debugging: - After fabrication the block of

semiconductor material is enclosed in s supporting case that prevent it
from damage and corrosion. This is called packaging.

1.4 Moore’s Law

Moore's law refers to an observation made by Intel co-founder Gordon Moore in
1965. He noticed that the number of transistors per square inch on integrated
circuits had doubled every year since their invention.
Moore's law predicts that this trend will continue into the foreseeable future.
Although the pace has slowed, the number of transistors per square inch has since
doubled approximately every 18 months. This is used as the current definition of
Moore's law.

BREAKING DOWN 'Moore's Law'

Because Moore's law suggests exponential growth, it is unlikely to continue
indefinitely. Most experts expect Moore's law to hold for another two decades.
Some studies have shown physical limitations could be reached by 2017.
The extension of Moore's law is that computers, machines that run on
computers, and computing power all become smaller and faster with time, as
transistors on integrated circuits become more efficient. Transistors are simple
electronic on/off switches embedded in microchips, processors and tiny electrical
 15

circuits. The faster microchips process electrical signals, the more efficient a
computer becomes.
Costs of these higher-powered computers eventually came down as well,
usually about 30 percent per year. When designers increased the performance of
computers with better integrated circuits, manufacturers were able to create better
machines that could automate certain processes. This automation created lower-
priced products for consumers, as the hardware created lower labor costs
Societal Impact
Fifty years after Moore's law, contemporary society sees dozens of benefits from
his vision. Mobile devices, such as smartphones and tablet computers, would not
work without very small processors. Smaller and faster computers improve
transportation, health care, education and energy production. Just about every
facet of a high-tech society benefits from the concept of Moore's law put into
practice

The Future
Thanks to nanotechnology, some transistors are smaller than a virus. These
microscopic structures contain carbon and silicon molecules aligned in perfect
fashion that help move electricity along the circuit faster. Eventually, the
temperature of the transistors make it impossible to create smaller circuits,
because cooling the transistors takes more energy than what passes through the
transistors. Experts show that computers should reach physical limits of Moore's
law sometime in the 2020s. When that happens, computer scientists can examine
entirely new ways of creating computers.

1.5 Available Implementation Technologies

1. Full Custom

2. Standard Cell
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2. Gate Array

Implementation Choices-
Integrated Circuits could be:-

-PLD 100’s

-Gate Array 1000’s

-Standard Cell 10,000’s

-Full Custom millions

With increasing numbers of logic gates going from 100 gates to 10 M gates.

Implementation Technologies
We can implement a design with many different implementation technologies-

-different implementation technologies offer different tradeoffs

-VHDL synthesis offers an easy way to target a model towards different

implementations

-There are also retargeting tools which will convert a net list from one
technologies to another.

(From a standard cell implementation to a field Programmable Gate Array

implementation).

1. Full Custom
Designer hand draws geometries which specify transistors and other devices for
and integrated circuits.

-Designer must be an expert in VLSI (very Large Scale Integration) design.

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Can achieve very high transistor density (transistor per square micron);
unfortunately, design time can be very long (multiple months).

Involves the creation of a completely new chip, which consists of about a dozen
masks (for the photolithographic manufacturing process).

-Mask creation is the expensive part.

Offers the chance for optimum performance.

-performance is based on available process technology, designer skill, and CAD

tool assistance.

Fabrication costs are high- all custom marks must be made so non-recurring
engineering costs (NRE) is high (in the thousands of dollars).

-if required number of chip is high then can spread these NRE costs across the
chips.

The first custom chip costs you about $200,000, but each additional one is much
cheaper.

Fabrication time geometry submission to returned chips is at least 6-8 weeks.

Full custom is currently the only option for mixes Analog/Digital chips.An
example VLSI layout is shown below in figure 1.3

Fig 1.3- Full Custom Layout

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2.Standard Cell
Desginer uses a library of standard cells; an automatic place and route tool does
the layout.

-Designer does not have to be a VLSI expert.

Trasistor density and performance degradation depends on type of design begin

done.

-Not bad for random logic, can be significant for data path type designs.

Quality of available library and tools make a significant differnence.

Design time can be musch faster than full custom because layout is automatically
generated.

Still inviles creatio of cistom chip so all masdks must stillbe made; manufacturing
costs same custom. as full

Fabrication time same as full custom.

Layout shown as below in figure 1.4

Figure 1.4- Standard cell Layout

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3.Gate Array
Desginer uses a library of a standard cells.

The designer is mapped onto and arrat of transistor which os already created on a
wafer; wafers with trasnistor arrays can be created ahead of time.

A routing tool creates the masks for the routing layers and customize the pre-
created gate array for the user’s design.

Transistor density can be almost as food as standard cell.

Design time advantages are the same as for standard cell.

Performance can be very good;

-again, depends on qualoty of available library and routing tools.

Fabrication costs are cheaper than standard cell or full custom because the gate
array wafers are ,ass produced;

The non recrring engineering costs are lower

-because only a few (1-3) unique masks have to be created for each design.

Fabrication time can be extremely short (1-2 weeks)

-because the wafers are already created and are only missing the routing
layers.

-The more routing layers, the higher the cost,the longer the fabrication
time,but the better usage of the available transistor on the array.

Almost all high volume produstion of complex digital designs are done in either
Standard Cell or Gate Array.

-Gate Arrays used to be more popular, but recently Standard Cells has shown
aresurgence in use.
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1.7 Advantages
Full custom can give best density and performance.Faster design time and ease of
design are principle advantages of gate array and standard cell over full custom.

Fast fabrication time and lower cost are principle advantages of gate arrays over
standard cell.

Gate arrays offer much higher density over FPGAs and are cheaper than FPGAs
in volume production.

FPGAs principle advantage over gate arrray is instant fabrication time

(programmed on desktop).

FPGAs are also cheaper than gate arrays in low volume.

Densities are reaching 100’s of thousands of gates/chips.

Can be used to prototype full custom/standard cell designs.

PLD’s still hold a speed advantage over most FPGAs are usefull primarily for
high speed decoding and speed critical glue logic.

I have worked on Altera DE0-Nano FPGA board as shown in fig 1.5

Fig 1.5- Altera FPGA Board (Front View)

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Back view of the board

Fig 1.6- Altera FPGA Board (Back View)

Fig 1.7- Block diagram of Altera Board

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Features of DE0-Nano FPGA Board –

 This board contains 4 dip switches, 2 push buttons for input.
 Push button remain at logic 1 in rest position.
 It also contain 8 LED for displaying output.
 It has 80 general purpose input-output (GPIO) pins.
 A crystal oscillator of 50 MHz is available on board.
 A 16 pin analog-degital converter is also available.
 For storage this board has 32MB SDRAM.
 For this board 3.3V is logic 1.
 A digital accelerometer is also there on board. The digital accelerometer
 is used to measure acceleration and force in any direction
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Chapter 2:
1.1 VHDL :-

The VHSIC Hardware Description Language is an industry standard language

used to describe hardware from the abstract to the concrete level. VHDL resulted
from work done in the ’70s and early ’80s by the U.S. Department
Of Defense. Its roots are in the ADA language, as will be seen by the overall
structure of VHDL as well as other
VHDL statements.

- VHDL stands for VHSIC Hardware Description Language and VHSIC stands
for Very High Scale Integrated Circuit. VHDL is a programming language which
is used to describe the behavior of a digital circuit. VHDL is commonly used to
write text models that describe a logic circuit. This text model of a circuit is
simulated by various tools.

 VHDL provide concurrent and sequential execution.

 VHDL is a case insensitive language.
 Top level hierarchy can be accomplished.
 VHDL is a strongly typed language.
 VHDL code can be simulated by applying test vectors.

Terminology in VHDL

1. Entity:- All designs are expressed in terms of entities. An entity is the most
basic building block in a design. The uppermost level of the design is the
top-level entity. If the design is hierarchical, then the top-level description
will have lower-level descriptions contained in it. These lower-level
descriptions will be lower-level entities contained in the top-level entity
description.
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Ex.1
Entity xor_g is
port (a,b:in std_logic ; c:out std_logic);
end xor_g;

entity_name is the name given to the design.

2. Architecture:- The internal details of an entity are specified by an

architecture body using any of the following modeling styles:
a. As a set of interconnected components (to represent structure),
b. As a set of concurrent assignment statements (to represent dataflow),
c. As a set of sequential assignment statements (to represent behavior),
d. Any combination of the above three.
On the basis of type of architecture there are three different approaches to
describe a hardware -
1. Data Flow
2. Behavioural
3. Structural

1. Data Flow:-
In this modeling style, the flow of data through the entity is expressed primarily
using concurrent signal assignment statements. The structure of the entity is not
explicitly specified in this modeling style, but it can be implicitly deduced.
For example half adder implement using dataflow-
Ex.2
entity hf_adder is
port(a,b:in std_logic ; s,c:out std_logic);
end hf_adder;
architecture dataflow of hf_adder is
 25

begin
s<=a xor b;
c<=a and b;
end dataflow;

2. Behavioural:-
The behavioral style of modeling specifies the behavior of an entity as a set of
statements that are executed sequentially in the specified order. This set of
sequential statements, that are specified inside a process statement, do not
explicitly specify the structure of the entity but merely specifies its
functionality. A process statement is a concurrent statement that can appear
within an architecture body.
For example Mux is implement using behavioral-
Ex.3
entity mux2x1 is
port(sum,minus: in std_logic_vector(1 downto 0);
sel:in std_logic;
output: out std_logic_vector(1 downto 0));
end entity;
architecture behav of mux2x1 is
begin
process(sum,minus,sel)
begin
case sel is
when '0' => output<=minus;
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when '1' => output<=sum;

when others => output <="00";
end case;
end process;
end architecture;
3. Structural: - In structural description we break the design in small modules
and use each module that is designed before. The main entity has several
sub entities. Sub designs are already designed and we use them in creating
higher-level design. In structural modelling hierarchy is developed.
For example a full adder is implement using structural modelling-

Ex.4
entity full_adder is
port(a,b,cin:in std_logic ;
sum,cout:out std_logic);
end entity;
architecture struct of full_adder is
component and_g is
port(a,b:in std_logic ; c:out std_logic);
end component;
component or_g is
port(a,b:in std_logic ; c:out std_logic);
end component;
component xor_g is
port(a,b:in std_logic ; c:out std_logic);
end component;

signal w1,w2,w3,w4,w5: std_logic;

begin
xor1: xor_g port map(a,b,w1);
xor2: xor_g port map(w1,cin,sum);
 27

and1: and_g port map(a,b,w2);

and2: and_g port map(b,cin,w3);
and3: and_g port map(cin,a,w4);

or1: or_g port map(w2,w3,w5);

or2: or_g port map(w4,w5,cout);
end architecture;

2. TestBench: - Test Bench is also a HDL code. This is not used to describe a
hardware, but to simulate a design. In test bench we call the component
or entity to be tested. Test vectors are applied to design and result is
verified in simulation process.
Now how to write testbench first let’s see the testbench of XOR gate
Ex.5
entity xor_tb is
end xor_tb;
architecture TestBench of xor_tb is
component xor_g is
port(a,b:in std_logic ; c:out std_logic);
end component;
signal a,b,c:std_logic;
begin
A1:xor_g port map(a,b,c);
process
begin
--case 1;
 28

a<='0'; b<='0';
wait for 10 ns;
--case 2;
a<='0'; b<='1';
wait for 10 ns;
--case 3
a<='1'; b<='0';
wait for 10 ns;
--case 4;
a<='1'; b<='1';
wait for 10 ns;
end process;
end architecture;
After simulation in ModelSim altera waveform as shown in figure 2.1

Figure 2.1-Waveform of XOR gate

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2.2 Data Type in VHDL

2.2.1 Object type: - A VHDL object consists of one of the following:

1. Signal, which represents interconnection wires that connect component

Instantiation ports together.
2. Variable, which is used for local storage of temporary data, visible
Only inside a process.
3. Constant, which names specific values.
1. Signal: - Signal objects are used to connect entities together to form models.
Signals
Are the means for communication of dynamic data between entities. A
Signal declaration looks like this:

SIGNAL signal_name : signal_type [:= initial_value];

The keyword SIGNAL is followed by one or more signal names. Each
signal name creates a new signal. Separating the signal names from the
signal type is a colon. The signal type specifies the data type of the information
that the signal contains. Finally, the signal can contain an initial value specifies so
that the signal value may be initialized.
Signals can be declared in entity declaration sections, architecture declarations,
and package declarations. Signals in package declarations are also referred to as
global signals because they can be shared among entities.

signal adder: std_logic_vector (7 downto 0);

2. Variable: - Variable is used as a local storage/wire in process or subprogram.

Variable is considered as a local object. Each process have their own variables.
variable variable_name : variable_type : = initial value;
example –
variable I : integer range 0 to 7 := 0;
-Variables are inherently more efficient because assignments happen
immediately, while signals must be scheduled to occur.
 30

-Variables take less memory, while signals need more information

to allow for scheduling and signal attributes.
-Using a signal would have required a WAIT statement to synchronize the signal
assignment to the same execution iteration as the usage.

3. Constant: - Constant objects are names assigned to specific values of a type.

Constants give the designer the ability to have a better-documented model, and a
model that is easy to update. For instance, if a model requires a fixed value in a
number of instances, a constant should be used.

constant constant_name : constant_type : = value;

example –
constant pi : real := 3.14;
‘real’ is a data type.

2.2.2 Data Type:-

1. Scalar:- Scalar types describe objects that can hold, at most, one value at
a time.
The type itself can contain multiple values, but an object that is declared scalar
type can hold, at most, one of the scalar values at any point in time. Referencing
the name of the object references the entire object.
Scalar types encompass these four classes of types:
-Integer types
-Real types
-Enumerated types
-Physical types

a. Integer type: - Integer type is same as mathematical integers. Its range is

-2,147,483,647 to +12,147,483,647.
example – port (a,b:in integer range 0 to 12 := 5);

b. Real type: - Real type is used to declare object the contain fractional
values/real numbers. The minimum range of real numbers is also specified by
 31

the Standard package in the Standard Library, and is from -1.0E+38 to +1.0E+38.
Time cannot be assigned to a real value.
example – port(a:in real := 3.132e-2);

c. Std_Logic: - Std_logic type is an extension of the standard bit type. It define

nine values. Std_logic is resolved version of std_ulogic. Resolved means that a
signal can be driven by multiple sources in a program. It is defined in
std_logic_1164 package.
A std_logic type object can have following 9 type of values –
 ‘U’: uninitialized. This signal hasn’t been set yet.
 ‘X’: unknown. Impossible to determine this value 0 or 1.
 ‘0’: logic 0
 ‘1’: logic 1
 ‘Z’: high impedance
 ‘W’: weak signal, it can be 0 or 1.
 ‘L’: weak signal that should probably go to 0.
 ‘H’: weak signal that should probably go to 1.
 ‘-‘: don’t care.
example – port(a,b:in std_logic:= ‘1’);

d. Enumerated type: - Enumerated type is data type that is created by designer

according to requirement. All values of this type of object are user defined.
Syntax to create data type –
type type_name is (set of possible values);
example – type state is (s0, s1, s2, s3, s4, s5);
type day is (sun, mon, tue, wed, thu, fri, sat);
type instruction is (add, sub, hlt, rst);
Syntax to use created data type –
object_type object_name : type_name;
 32

example – signal w:day:= sun;

variable ps,ns:state:=s0;
2. Composite Types:-
A composite type represents a collection of values. There are two composite
types: an array type and a record type. An array type represents a collection of
values all belonging to a single type; on the other hand, a record type represents a
collection of values that may belong to same or different types. An object
belonging to a composite type, therefore, represents a collection of sub objects,
one for each element of the composite type. An element of a composite type could
have a value belonging to either a scalar type, a composite type, or an access type.
For example, a composite type may be defined to represent an array of an array
of records. This provides the capability of defining arbitrarily complex composite
types.
i. Array type:- Array types group one or more elements of the same
type together as a single object. Each element of the array can be accessed by one
or more array indices. Elements can be of any VHDL type.
For example-

TYPE data_bus IS ARRAY(0 TO 31) OF BIT;

ii. Record type:- Record types group objects of many types together
as a single object. Each element of the record can be accessed by its field
name. Record elements can include elements of any type, including arrays
and records. The elements of a record can be of the same type or different
types. Like arrays, records are used to model abstract data elements.
Following is an example of a record type declaration:

TYPE optype IS ( add, sub, mpy, div, jmp );

TYPE instruction IS
RECORD
opcode : optype;
src : INTEGER;
dst : INTEGER;END RECORD;
 33

convert binary data into integer – In VHDL we use a function to convert binary
data into integer.
y<=conv_integer(x);
where y is an integer object and x is an std_logic type object.

2.3 Sequential Processing:-

1. Process Statement: - In VHDL we define sequential statements in process.

The behavioural description of a hardware is written in process. All kind of
looping and conditional statements are written in process. Process
statement has three parts
2. The list of signals in parentheses after the keyword “process” is called the
sensitivity list. This list contains the signals on which the execution of
process depends.
3. The area between sensitivity list and keyword “begin” is declarative part.
This part can contain variable declaration that can be used locally in the
process.
4. The statement part of the process starts at the keyword “begin” and ends at
the “end process” line. All the statements enclosed in this region are
executed in sequential order.

Sequential statements exist inside the boundaries of a process statement

as well as in subprograms. In this chapter, we are most concerned with
sequential statements inside process statements.
The sequential statements that we discuss are:
i. IF
ii. CASE
iii. LOOP
iv. WAIT

(i)if statement: - An if statement selects a sequence of statements for execution

based on the value of a condition. The condition can be any expression that
evaluates to a boolean value. The general form of an if statement is
 34

if [boolean-expressionthen
sequential-statements
[ elsif boolean-expression then
sequential-statements
[ else -- else clause.
sequential-statements ]
end if;

Ex.6

Fig 2.2-AND Gate

entity and_gb is
port(a,b:in std_logic; y:out std_logic);
end and_gb;
architecture behav of and_gb is
begin
process(a,b)
begin
if(a='1' and b='1') then
y<='1';
else
y<='0';
end if;
 35

end process;
end architecture;

(ii) Case Statement:- The case statement is used whenever a single expression
value can be used to select between numbers of action. Case statement is written
under process. Case statement starts with ‘case’ keyword and ends with ‘end case’
keyword. Keyword ‘when’ is used to define choices.
If the value of instruction is one of the choices listed in the WHEN clauses, then
the statement following the WHEN clause is executed.
case expression is
when choices => sequential-statements -- branch #1
when choices => sequential-statements -- branch #2
-- Can have any number of branches.
[ when others => sequential-statements ] -- last branch
end case;

Ex.7 Mux 4x1 using case statement

Fig 2.3-Mux
entity mux is
port(s:in std_logic_vector(1 downto 0);
i:in std_logic_vector(3 downto 0);
y:out std_logic);
end mux;
architecture behave of mux is
 36

begin
process(s,d)begin
case s is
when “00” => y<=i(0);
when “01” => y<=i(1);
when “10” => y<=i(2);
when “11” => y<=i(3);
when others => y<=’0’;
end case;
end process;

(iii) Loop Statement: - A loop statement is used to iterate through a set of

sequential statements. The syntax of a loop statement is
[ loop-label : ] iteration-scheme loop
sequential-statements
end loop [ loop-label ] ;
There are three types of iteration schemes. The first is the for iteration scheme
that has the form
for identifier in range
An example of this iteration scheme is
FACTORIAL := 1;
for NUMBER in 2 to N loop
FACTORIAL := FACTORIAL * NUMBER;
end loop;

Ex.8:-
Ripple carry adder using loop

Fig 2.4-Ripple Carry Adder

 37

entity rca is
port(a:in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
cin:in std_logic;
sum:out std_logic_vector (3 downto 0);
cout:out std_logic);
end entity;
architecture lv of rca is
begin
process (a,b,cin)
variable c: std_logic_vector(4 downto 0);
begin
c(0):= cin;
for i in 0 to 3 loop
sum(i)<=(a(i) xor b(i) xor c(i));
c(i+1):= ((a(i) and b(i)) or (b(i) and c(i)) or (a(i) and
c(i)));
end loop;
cout<= c(4);
end process;
end architecture;
 38

Chapter 3:
3.1 Combinational Circuits

Combinational logic circuits are circuits in which the output at any time depends
upon the combination of the input signals at that instant only and does not depends
upon past value.

3.1.1 Circuit-1:- Desgin a Half-Adder

The half adder is an example of a simple, functional digital circuit built from two
logic gates. The half adder adds two one-bit binary numbers (AB). The output is
the sum of the two bits (S) and the carry (C).figure shown below.

Fig 3.1-half adder

library ieee;
use ieee.std_logic_1164.all;
entity hf_adder is
port(a,b:in std_logic ; s,c:out std_logic);
end hf_adder;
architecture dataflow of hf_adder is
begin
s<=a xor b;
 39

c<=a and b;
end dataflow;

3.1.2 Circuit-2:-Design a Full-Adder

The full adder is an example of a simple, functional digital circuit built from five
logic gates. The full adder adds two three-bit binary numbers (ABC). The output
is the sum of the three bits (S) and the carry (C) figure shown below.

Fig 3.2- Full adder

library ieee;
use ieee.std_logic_1164.all;
entity full_adder is
port(a,b,cin:in std_logic ; s,cout:out std_logic);
end full_adder;
architecture dataflow of full_adder is
begin
s<=a xor b xor cin;
cout<=(a and b) or (b and cin) or ( a and cin);
end dataflow;

3.1.3 Circuit-3:- Design a 1 bit magnitude comparator

 40

Magnitude comparator is used to compare two binary number and make decision
that whether the numbers are equal or which number is larger and which is
smaller.
Truth table as shown in figure below.

Table 3.1-Truth table of 1-bit Mag comp

library ieee;
use ieee.std_logic_1164.all;
entity mag_comparator is
port(a,b:in std_logic ; x,y,z:out std_logic);
end entity;
architecture dataflow of mag_comparator is
begin
x<=a and (not b);
y<= a xnor b;
z<= (not a)and b;
end architecture;
 41

3.1.4 Circuit-4:- Design a BCD code to seven segment

A seven-segment display is commonly used in electronic display device for

decimal numbers from 0 to 9 and in some cases, basic characters. Use of light
emitting diodes (LEDs) in seven segment displays made it more popular, whereas
of late liquid crystal displays (LCD) displays have also come into use.
These are basically 2 types of 7 segment LED display.

Common Anode: All the Negative terminals (cathode) of all the 8 LEDs are
connected together. All the positive terminals are left alone.
Common Cathode: All the positive terminals (anode) of all the 8 LEDs are
connected together. All the negative thermals are left alone.

Fig 3.3- seven segment

library ieee;
use ieee.std_logic_1164.all;
entity bcd_7_segment is
port (w,x,y,z:in std_logic; a,b,c,d,e,f,g:out std_logic);
 42

end bcd_7_segment;
architecture datalflow of bcd_7_segment is
begin
a<= w or y or (x xnor z);
b<= (not x) or (y xnor z);
c<= x or (not y) or z;
d<= w or (y and (not z)) or (x xor (y or (not x)));
e<= (not z) and ((not x) or y);
f<= w or ((not y) and (not z))or(xand((not y)or (not z)));
g<= (w or (y and (not z)) or (x xor y));
end architecture;

3.1.5 Circuit-5:- Design a Binary to grey code conversion and display result
on seven segment.

Fig 3.4-Binary to grey code conversion

library ieee;
use ieee.std_logic_1164.all;
entity binary_grey_7 is
port(w,x,y,z:in std_logic; a:out std_logic_vector(6
downto 0); b:out std_logic_vector(6 downto 0) );
 43

end binary_grey_7;
architecture mix of binary_grey_7 is
signal s:std_logic_vector (3 downto 0);
begin
s(3)<= w;
s(2)<= w xor x;
s(1)<= x xor y;
s(0)<= y xor z;
process(s)
begin
case s is
when "0000"=> a<="1111110" ;b<="1111110";
when "0001"=> a<="1111110" ;b<="0110000";
when "0011"=> a<="1111110" ;b<="1111001";
when "0010"=> a<="1111110" ;b<="1101101";
when "0110"=> a<="1111110" ;b<="1011110";
when "0111"=> a<="1111110" ;b<="1110000";
when "0101"=> a<="1111110" ;b<="1011011";
when "0100"=> a<="1111110" ;b<="0110011";
when "1100"=> a<="0110000" ;b<="1101101";
when "1101"=> a<="0110000" ;b<="1111001";
when "1111"=> a<="0110000" ;b<="1011011";
when "1110"=> a<="0110000" ;b<="0110011";
when "1010"=> a<="0110000" ;b<="1111110";
when "1011"=> a<="0110000" ;b<="0110000";
when "1001"=> a<="1111110" ;b<="1111011";
when "1000"=> a<="1111110" ;b<="1111111";
when others => a<="1111110" ;b<="1111110";
end case;
end process;
end architecture;

3.1.6 Circuit-6:-Desgin a Ripple Carry adder using structural modelling.

 44

Figure as shown below:

Fig 3.5: Ripple carry adder

A ripple carry adder is a logic circuit in which the carry-out of each

full adder is the carry in of the succeeding next most significant full adder. It
Is called a ripple carry adder because each carry bit gets rippled into the next
stage.
VDHL code for ripple carry adder is

library ieee;
use ieee.std_logic_1164.all;
entity ripple_adder is
port(a:in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
cin:in std_logic;
sum:out std_logic_vector (3 downto 0);
cout:out std_logic);
end ripple_adder;
architecture struct of ripple_adder is
component full_adder is
port(a,b,cin:in std_logic ;
sum,cout:out std_logic);
end component;
signal c: std_logic_vector (2 downto 0);
begin
 45

fulladder1:full_adder portmap(a(0),b(0),cin,sum(0),c(0));
fulladder2:full_adder portmap(a(1),b(1),c(0),sum(1),c(1));
fulladder3:full_adder portmap(a(2),b(2),c(1),sum(2),c(2));
fulladder4:full_adder portmap(a(3),b(3),c(2),sum(3),cout);
end architecture;

3.1.7 Circuit-7:-Design a 16x1 Mux using 8x1 and 2x1 Mux

In electronics, a multiplexer (or mux) is a device that selects one of several analog
or digital input signals and forwards the selected input into a single line. A
multiplexer of 2n inputs has ⌈n⌉ select lines, which are used to select which input
line to send to the output.
Figure a shown below:

Fig 3.6-16x1 Mux

 46

VDHL code for this circuit is:

library ieee;
use ieee.std_logic_1164.all;
entity mux_16x1 is
port (i:in std_logic_vector (15 downto 0);
lines: in std_logic_vector (3 downto 0);
z:out std_logic);
end entity;
architecture struct of mux_16x1 is
component mux_8x1 is
port(d:in std_logic_vector (7 downto 0);
sel:in std_logic_vector (2 downto 0);
y:out std_logic);
end component;
component mux_2x1 is
port(w:in std_logic_vector(1 downto 0);
sel:in std_logic; y:out std_logic );
end component;
signal d1,d2:std_logic_vector(7 downto 0);
signal d0: std_logic_vector(1 downto 0);
signal x1,x2: std_logic;
signal sel: std_logic_vector(2 downto 0);
signal y: std_logic_vector (7 downto 0);

begin
d1<=(i(15)&i(14)&i(13)&i(12)&i(11)&i(10)&i(9)&i(8));
d2<=(i(7)&i(6)&i(5)&i(4)&i(3)&i(2)&i(1)&i(0));
d0<=(x1&x2);
sel<=(lines(2)&lines(1)&lines(0));

mux1: mux_8x1 port map (d1,sel,x1);

mux2: mux_8x1 port map (d2,sel,x2);
mux2x1: mux_2x1 port map (d0,lines(3),z);

end architecture;
 47

3.1.8 Circuit-8:- Design a 2-bit magnitude comparator

Table 3.2- 2-bit mag comp

Inputs Outputs
A B X(A>B) Y(A=B) Z(A<B)
00 10 0 0 1
10 11 0 0 1
11 01 1 0 0
01 01 0 1 0
11 10 1 0 0
01 00 1 0 0

library ieee;
use ieee.std_logic_1164.all;
entity bit2_mag_comp is
port (a,b:in std_logic_vector (1 downto 0); q,w,e:out
std_logic);
end entity;
architecture struct of bit2_mag_comp is
component mag_comparator is
port(a,b:in std_logic ; x,y,z:out std_logic);
end component;
signal t3,t2,t1,r3,r2,r1: std_logic;
begin
mag1: mag_comparator port map (a(1),b(1),t3,t2,t1);
mag2: mag_comparator port map (a(0),b(0),r3,r2,r1);
process(t,r)
begin
if (t="010") then
if(r="010") then
 48

q<='0';w<='1';e<='0';

elsif (r="100") then

q<='1';w<='0';e<='0';

else
q<='0';w<='0';e<='1';
end if;
elsif (t="100") then
q<='1';w<='0';e<='0';
else
q<='0';w<='0';e<='1';
end if;
end process;
end architecture;

3.1.9 Circuit-9:-Design a 8x3 Encoder

An encoder is a digital circuit that performs the inverse operation of a decoder.

An encoder has 2^n (or fewer) input lines and n output lines.
Figure as shown below:

Fig 3.7- Encoder

VHDL code for 8x3 encoder is –

library ieee;
 49

use ieee.std_logic_1164.all;
entity encoder is
port(D:in std_logic_vector(7 downto 0); y:out
std_logic_vector(2 downto 0); en:in std_logic);
end encoder;
architecture behav of encoder is
begin
process(en,D)
begin
if (en='1') then
case D is
when "00000001" => y<="000";
when "00000010"=> y<="001";
when "00000100"=> y<="010";
when "00001000"=> y<="011";
when "00010000"=> y<="100";
when "00100000"=> y<="101";
when "01000000"=> y<="110";
when "10000000"=> y<="111";
when others => y<="000";
end case;
else
y<="000";
end if;
end process;
end architecture;

After simulation in Modal Sim Altera we got this Waveform as shown below in
fig 3.8.

the basic problem is that we have 8 input data lines but on board we have only 4
dip switch keep in mind that we can also use external switch but how to do with
4 switches.
Basic idea is you can store 8 bits data in a signal or u can define inout mode in
entity.
 50

Fig 3.8- Waveform of encoder

 51

Chapter 4:
4.1 Sequential Circuit

The combinational circuit does not use any memory. Hence the previous state of
input does not have any effect on the present state of the circuit. But sequential
circuit has memory so output can vary based on input. This type of circuits uses
previous input, output, clock and a memory element.

Fig 4.1-Block Diagram of Sequential circuit

Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes
its outputs only at particular instants of time and not continuously. Flip flop is
said to be edge sensitive or edge triggered rather than being level triggered like
latches.

A sequential circuit is specified by a time sequence of inputs, outputs, and internal

states.
Sequential circuits are of two types –
 52

1. Synchronous (with clock) – In these kind of circuits synchronization is achieved

by a timing device which generates a periodic train of clock pulses. Each device
is triggered by same clock pulses.
2. Asynchronous (without clock) – In asynchronous circuits no clock is used and
these circuits are faster than synchronous circuits.

4.1.1 Circuit 1:- Design a JK Flip Flop

Truth table of JK flip flop as shown below

Table 4.1-JK Flip Flop

VHDL code is

library ieee;
use ieee.std_logic_1164.all;
entity jk_ff is
port(j,k,clk,rst: in std_logic;
q,qbar:out std_logic);
end entity;
architecture behav of jk_ff is
signal w: std_logic;
begin
process(j,k,clk,rst)
begin
if(clk'event and clk='1') then
if (rst='1') then
 53

w<='0';

elsif (j<='0' and k<='0') then

w<=w;
elsif (j<='0' and k<='1') then
w<='0';
elsif (j<='1' and k<='0') then
w<='1';
elsif (j<='1' and k<='1') then
w<=not w;
else
w<='0';
end if;
end if;
end process;
q<=w;
qbar<=not w;
end architecture;

RTL or gate level diagram is

Fig 4.2-RTL level circuit of jk flip flop

4.1.2 Circuit 2:- Design a D-Flip Flop

 54

Fig 4.3- D Flip Flop

VHDL Code for this circuit is follow:

library ieee;
use ieee.std_logic_1164.all;
entity d_ff is
port ( d,rst,clk:in std_logic ;
q ,qbar:out std_logic);
end entity;
architecture behav of d_ff is
signal w: std_logic;
begin
process (d,rst,clk)
begin
if(clk'event and clk='1') then
if (rst='1') then
w<='0';
else
w<=d;
end if;
end if;
end process;
q<=w;
qbar<= not w;
end architecture;

4.1.3 Circuit 3:- Design a Serial in Serial Out Shift Register.

 55

Serial In Serial Out (SISO) shift registers are a kind of shift registers where
both data loading as well as data retrieval to/from the shift register occurs in
serial-mode. Figure 1 shows a n-bit synchronous SISO shift register sensitive to
positive edge of the clock pulse. Here the data word which is to be stored is fed
bit-by-bit at the input of the first flip-flop. Further it is seen that the inputs of all
other flip-flops (except the first flip-flop FF1) are driven by the outputs of the
preceding ones say for example, the input of FF2 is driven by the output of FF1.
At last the data stored within the register is obtained at the output pin of the
nth flip-flop in serial-fashion.
Figure show below in fig1.7

Fig 4.4-SISO

library ieee;
use ieee.std_logic_1164.all;
entity serial_iso is
port(d,clk,rst:in std_logic;
x:out std_logic);
end entity;
architecture behav of serial_iso is
signal w: std_logic_vector (3 downto 0);
begin
process(d,clk,rst)
begin
if(clk'event and clk='1') then
if (rst='1') then
w<="0000";
else
w(0)<=d;
 56

w(1)<=w(0);
w(2)<=w(1);
w(3)<=w(2);
end if;
end if;
end process;
x<=w(3);
end architecture;

RTL level diagam as shown below:

Fig 4.5-RTL level of SISO

4.1.4 Circuit 4:- Design Parallel in Parallel Out Shift Register (PIPO).

Fig 4.6-PIPO
 57

VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity pipo is
port(d:in std_logic_vector (3 downto 0);
clk,rst:in std_logic;
x:out std_logic_vector (3 downto 0));
end entity;
architecture behav of pipo is
begin
process(d,clk,rst)
begin
if(clk'event and clk='1') then
if (rst='1') then
x<="0000";
else
x<=d;
end if;
end if;
end process;
end architecture;

4.1.5 Circuit 5:- Design a up counter.

A digital circuit which is used for a counting pulses is known counter. Counter is
the widest application of flip-flops. It is a group of flip-flops with a clock signal
applied.

VDHL CODES:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 58

entity up_counter is
port(clk,rst:in std_logic;
y:out std_logic_vector(3 downto 0));
end entity;
architecture behav of up_counter is
signal temp : std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if (rst='1') then
temp<="0000";
elsif (clk'event and clk='1') then
temp<=temp + '1';
end if;
end process;
y<=temp;
end architecture;

4.1.6 Circuit 6:-Design 4-bit UP/down Counter with halt input and display
the result on seven segment.

VHDL Code for this design is:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity downcount is
port(clk,rst,hlt,ud:in std_logic;
a,b:out std_logic_vector(6 downto 0));
end entity;
architecture behav of counter_7segment is
signal pulse_counter: std_logic_vector (3 downto 0);
signal pulse :std_logic;
signal temp : std_logic_vector(3 downto 0);
begin
process(clk)
 59

begin
if (clk'event and clk='1') then
if ( pulse_counter < X"2FAF080") then
pulse_counter <= pulse_counter+X"1";
pulse<='1';
else
pulse_counter<=(others=>'0');
pulse<='0';
end if;
end if;
end process;

process(pulse,rst)
begin
if (rst='1') then
temp<="0000";
elsif (pulse'event and pulse='1') then
if (ud='1') then
if (hlt='1') then
temp<=temp + '1';
else
temp<=temp;
end if;
else
if (hlt='1') then
temp<=temp-'1';
else
temp<=temp;
end if;
end if;
end if;
end process;
process(temp)
begin
case temp is
when "0000"=> a<="1111110" ;b<="1111110";
when "0001"=> a<="1111110" ;b<="0110000";
 60

when "0011"=> a<="1111110" ;b<="1111001";

when "0010"=> a<="1111110" ;b<="1101101";
when "0110"=> a<="1111110" ;b<="1011111";
when "0111"=> a<="1111110" ;b<="1110000";
when "0101"=> a<="1111110" ;b<="1011011";
when "0100"=> a<="1111110" ;b<="0110011";
when "1100"=> a<="0110000" ;b<="1101101";
when "1101"=> a<="0110000" ;b<="1111001";
when "1111"=> a<="0110000" ;b<="1011011";
when "1110"=> a<="0110000" ;b<="0110011";
when "1010"=> a<="0110000" ;b<="1111110";
when "1011"=> a<="0110000" ;b<="0110000";
when "1001"=> a<="1111110" ;b<="1111011";
when "1000"=> a<="1111110" ;b<="1111111";
when others => a<="1111110" ;b<="1111110";
end case;
end process;
end architecture;

4.1.7 Circuit 7:- Design a Ring Counter.

A ring counter is a Shift Register (a cascade connection of flip-flops) with the

output of the last flip flop connected to the input of the first. It is initialized such
that only one of the flip flop output is 1 while the remainder is 0. The 1 bit is
circulated so the state repeats every n clock cycles if n flip-flops are used. The
"MOD" or "MODULUS" of a counter is the number of unique states. The MOD
of the n flip flop ring counter is n.
It can be implemented using D-type flip-flops (or JK-type flip-flops).
VHDL CODE:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ring_counter is
port (clk,rst: in std_logic;
 61

y: out std_logic_vector(3 downto 0));

end entity;
architecture behav of ring_counter is
signal pulse_counter: std_logic_vector (31 downto 0);
signal pulse :std_logic;
signal q : std_logic_vector (3 downto 0);
--signal d: std_logic:='1';

begin
process(clk)
begin
if (clk'event and clk='1') then
if ( pulse_counter < X"2FAF080") then
pulse_counter <= pulse_counter+X"1";
pulse<='1';
else
pulse_counter<=(others=>'0');
pulse<='0';
end if;
end if;
end process;
process
begin
if (pulse'event and pulse='1') then
if (rst='1' ) then
q<="0001";
else
q(3)<=q(0);
q(2)<=q(3);
q(1)<=q(2);
q(0)<=q(1);

end if;
end if;
end process;
y<=q;
end architecture;
 62

RTL Level Diagram as shown:

Fig 4.7-RTL level of Ring counter

4.1.8 Circuit 8:- Design a Johnson counter.

A Johnson counter is a circular shift register with the complemented output of the
last flip‐flop connected to the input of the first flip‐flop. This counter is similar to
Ring counter except for one thing that in ring counter the input to first flip flop is
the non-complemented output of last flip-flop.
 63

Fig 4.8- Johnson counter

VHDL CODES:

library ieee;
use ieee.std_logic_1164.all;
entity jcount is
port(clk,rst:in std_logic;
y:out std_logic_vector(3 downto 0));
end jcount;
architecture behav of jcount is
signal w:std_logic_vector(3 downto 0):="0000";
begin
process(clk)
begin
if(rst='0')then
w<="0000";
elsif(clk'event and clk='0')then
w(3)<=(not w(0));
w(2)<=w(3);
w(1)<=w(2);
w(0)<=w(1);
 64

end if;
end process;
y<=w;
end behav;

4.2 FINATE STATE MACHINCE (FSM)

A finite-state machine (FSM) or finite-state automaton (FSA,

plural: automata), finite automaton, or simply a state machine, is a
mathematical model of computation. It is an abstract machine that can be in
exactly one of a finite number of states at any given time. The FSM can change
from one state to another in response to some external inputs; the change from
one state to another is called a transition. An FSM is defined by a list of its states,
its initial state, and the conditions for each transition.

There are two types of finite state machines that generate output −

 Mealy Machine- A Mealy Machine is an FSM whose output depends on

the present state as well as the present input.
 Moore machine - Moore machine is an FSM whose outputs depend on only
the present state.

4.2.1 Circuit 9:- Design a circuit to detect sequence 1001.

VHDL CODES:

library ieee;
use ieee.std_logic_1164.all;
entity fsm_1001 is
port(x,clk,rst:in std_logic;
 65

y:out std_logic);
end entity ;
architecture behav of fsm_1001 is

type state is (s0,s1,s2,s3);

signal ns,ps: state ;
begin
seq: process (clk,rst,ns)
begin

if (rst='1') then
ps<=s0;
elsif (clk'event and clk='1') then
ps<=ns;
end if;
end process;

comb: process (x,ps)

begin
case ps is
when s0=>
if (x='1') then
ns<=s1;
else
ns<=s0;
end if;
when s1=>
if (x='1') then
ns<=s1;
else
ns<=s2;
end if;
when s2=>
if (x='1') then
ns<=s3;
else
ns<=s2;
 66

end if;
when s3=>
if (x='1') then
ns<=s1;
else
ns<=s2;
end if;
end case;
end process;

y<='1' when ps=s3 else '0';

end architecture;

RTL Level:

Fig 4.9- RTL level diagram of sequence detector

Now according to mealy machine we have to show finate state diagram of

sequence 1001
 67

Fig 4.10- FSM of 1001

4.3 LCD INTERFERNCE

LCD (Liquid Crystal Display) screen is an electronic display module
and find a wide range of applications. A 16x2 LCD display is very basic
module and is very commonly used in various devices and circuits.
These modules are preferred over seven segments and other multi
segment LEDs. The reasons being: LCDs are economical; easily
programmable; have no limitation of displaying special & even custom
characters (unlike in seven segments), animations and so on.

Fig 4.11- LCD

 68

LCD diagram as shown above:

And all pin description as shown below:

Table 4.2 – LCD Commands

 69

Chapter 5:
5.1 Implemented digital circuits
Implemented digital circuits on Altera FPGA board in my summer
training session and digital circuits list as shown below.
i. All basic gate for e.g. AND, OR, NOT, XOR etc.
ii. Half adder
iii. Full adder
iv. Half add/sub
v. Full add/sub
vi. Mux
vii. BCD
viii. Binary to Grey
ix. BCD to 7-segment
x. Ripple carry adder
xi. Magnitude comparator
xii. Design a 16x1 mux using 8x1 and 2x1 mux’s
xiii. Carry look ahead adder
xiv. Ripple carry adder using loop
xv. Encoder
xvi. Decoder
xvii. Flip flop
xviii. Flip flop using other flip flop
xix. Serial in serial out shift register
xx. Parallel in parallel out shift register
xxi. Serial in parallel out shift register
xxii. Parallel in serial out shift register
xxiii. Counter
xxiv. Up/down counter with halt input
xxv. Frequency divider circuit
xxvi. Counter using data flow modelling
xxvii. Ring counter
xxviii. Johnson counter
 70

xxix. Memory (RAM,ROM)

xxx. Finate state machine
xxxi. Sequence detector
xxxii. Lcd interference
xxxiii. FIFO (First in first out)
xxxiv. EVM (Electronic Voting Machines)

5 .2 Electronic Voting Machines

As the days of elections begin, voters line-up to vote for their preferred
candidates. The entire voting process might be the very first one for many. One
of the many interesting things about the process is the Electronic Voting
Machine on which we place our votes.

Fig 5.1-EVM
When cast_vote is enable counters start working than if voter votes candidate P1
counter 1 counts and vote counts if Vote_done is enable. Like this circuits works
and I have this using behavioural modelling.
 71

VHDL CODES:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity evm1 is
port(p1,p2,p3,cast_vote,clk,rst:in std_logic;
count1,count2,count3:out std_logic_vector(3 downto
0);
vote_done: out std_logic );
end entity;
architecture behav of evm1 is
signal c1,c2,c3: std_logic_vector(3 downto 0);
begin
process(clk,rst,p1,p2,p3)
begin
if(rst='1') then
c1<="0000";
c2<="0000";
c3<="0000";
vote_done<='0';
elsif(clk'event and clk='1') then
if(p1='1' and p2='0' and p3='0' and cast_vote='1')
then
 72

c1<=c1 + '1';
vote_done<='1';
elsif(p1='0' and p2='1' and p3='0' and cast_vote='1')
then
c2<=c2 + '1';
vote_done<='1';
elsif(p1='0' and p2='0' and p3='1' and cast_vote='1')
then
c3<=c3 + '1';
vote_done<='1';
else
c1<=c1;
c2<=c2;
c3<=c3;
vote_done<='0';
end if;
end if;
end process;
count1<=c1;
count2<=c2;
count3<=c3;
end architecture;

And currently working on these digital circuits as list shown below:

 73

i. Binary Multiplier.
ii. Wallace Multiplier.
iii. Booth Multiplier.
iv. Modified Booth Multiplier.
v. EVM using Structural Modelling.
vi. Universal shift register.
 74

References

1. Wikipedia www.wikipedia.com
2. VHDL Programming By Example Douglas Perry.
3. VHDL primer by J bhasker.
4. Altera https://www.altera.com/
5. Xilinx - All Programmable https://www.xilinx.com/