FPGA Implementation of a Fix-Point Digital Baseband Pre-Distorter for

the Linearization of Wireless Transmitters

F. I. Yasuda1, R. A. S. Cavalheiro1, F. J. L. Luiz1, A. A. Mariano1, O. C. Gouveia Filho1, E. G. Lima1
1
Grupo de Circuitos Integrados e Sistemas (GICS) – Departamento de Engenharia Elétrica

Universidade Federal do Paraná, Curitiba, Brasil

Abstract — Digital baseband predistortion (DPD) is a cost the signal prior to its amplification by the PA, in a way that
effective solution to improve the energetic efficiency of power the signal at the PA output is a linear replica of the input
amplifiers (PA) for wireless communication systems. This paper signal. The DPD is subject to many other recent papers [1, 2,
addresses the design of DPD in fix-point arithmetic, suitable for
real-time implementation in a low-cost hardware such as a Field
4, 5], which the common objectives is to raise the RF PAs
Programmable Gate Array (FPGA). The design starts in efficiency even more by considering memory effects [1].
floating-point double-precision arithmetic for the parameter In this work, it is presented a fix-point design of a DPD
identification of a DPD having a memory polynomial topology. that is suitable for implementation in a Field Programmable
Then, the not straightforward conversion to fix-point arithmetic Gate Array (FPGA). The implemented DPD overcomes the
is discussed. The presented fix-point design allows for the real-
PA non-linear effects, raising its efficiency. Thus, the
time applicability of the DPD, by processing the polynomials as
Look-Up-Tables (LUT) and by using a sequential logic circuit linearization and high efficiency becomes possible.
that exploits as much as possible the parallel processing. For the This work is organized as follows. Section II describes the
FPGA Xilinx Virtex 5 and for numbers having 16 bits, it was modeling and identification of a DPD in floating-point
verified that a DPD frequency as high as 60 MHz can be used double-precision arithmetic. Section III addresses the design
and the DPD power consumption is approximately 0.5 W. The of a DPD in fix-point arithmetic and for real-time processing
validation of the accuracy of the designed fix-point DPD is done
based on computer simulations performed on a PA behavioral in a FPGA. Based on numerical simulations performed on a
model excited by a 3GPP WCDMA signal. It is verified that, if behavioral model of a class AB PA, in Section IV the
the PA is operated with a constant average output power in the accuracy of the designed fix-point DPD is validated. Finally,
cases with and without DPD, then the inclusion of the DPD Section V includes the conclusions of this work.
improves the ACPR metric at the PA output by 25 dB.

II. DPD design in float-point double-precision arithmetic

Index Terms — FPGA, linearization, memory polynomial,
power amplifiers, VHDL language. The purpose of a DPD system is that the output signal in a
cascade connection of the pre-distorter (PD) followed by a
power amplifier (PA) be a linear version of the input signal
I. Introduction
applied to the series connection [6], as shown in Fig. 1.
Wireless communication systems must provide a high rate
of data transfer in the reduced frequency band available. This
is obtained by modulating both the amplitude and phase a
carrier. As a consequence, wireless communication standards
impose limits in order to keep the linearity of the transmitted
signal [1], [2]. The most important element in the wireless
transmitters is the power amplifier (PA). Independent of the Fig. 1. Cascade connection of a pre-distorter followed by a PA.
class of operation, PAs exhibit intrinsically a compromise
between linearity and efficiency. With the rapid growth of The first step in the design of a DPD system is the selection
wireless technologies in the market, the needs of reduction of the pre-distorter topology. In this work, it was chosen the
the loss of power in the transmitter became relevant [1]. memory polynomial (MP) architecture [7], because it
Furthermore, the battery consumption by the users and provides a good trade-off between accuracy and
environmental issues demands for more efficient transmitters computational complexity. The MP model is a particular
[3], [4]. instance of a Volterra system, in which the complex-valued
To improve efficiency without compromising linearity, the low-pass equivalent baseband signals at the PD input,
alternative is to linearize the PA. Among the available
u (n ) and output x ( n) are related by:
linearization schemes, digital base-band predistortion (DPD)
is a cost effective solution. It consists of purposely distorting
 P M
x ( n)= ∑ ∑ h p ( m) u( n−m)∣u( n−m ) ∣p−1 (1)
p=1 m=0

where hp(.) are complex-valued coefficients, P is the

polynomial order truncation and M is the memory length. As
recommended in [8], (1) includes both odd and even powers
of the input amplitudes. In order to extract the parameters
hp(.), the indirect learning architecture was used [9]. In this
algorithm, as shown in Fig. 2, it is identified the parameters
of a post-distorter (PoD), e.g. an inverse system that is also
connected in cascade with the PA, put placed after it. The MP
is a model linear in its parameters and the identification can
be performed by least-squares in MATLAB software [10].
Since the PoD and DPD have the same Volterra-based
topologies, it can be shown that their parameters are
theoretically the same [9]. So, the parameters of the DPD are
just copies of the extracted PoD parameters.

Fig. 2. Block diagram of the indirect learning.

Observe that (1) can be rearranged to:

M
x ( n)= ∑ u( n−m) f m(∣u(n−m ) ∣2 ) (2)
m=0
where fm(.) are complex-valued functions having just one
independent real-valued variable. In the fix-point design Fig. 3. Block diagram of the fix-point DPD.
presented in the next section, the formulation in (2) is
exploited and each one-dimensional (1D) function fm(.) is As shown in Fig. 3, the real and imaginary parts from the
implemented by 2 Look-Up-Tables (LUTs): one for getting its signal to be pre-distorted, at the instantaneous time sample
real part and other to get its imaginary part. (n) and past time sample (n-1) are both squared. Their results
are summed and then indexed by 2 LUTs: one LUT for the
instantaneous time sample and the other LUT for the past
III. DPD design in fix-point arithmetic time sample. Each LUT provides 2 outgoing values to a
In order to make the data handling possible in fix-point, single input: a real component and an imaginary component.
the floating-point double-precision data must be normalized, The real components at the LUTs outputs are multiplied by
for instance to guarantee that the any data will exceed the their respective (e.g. at the same time sample) real
unity in floating-point arithmetic. Then, the normalized components of the DPD input signal (input signal without
floating-point double-precision data must be converted to fix- changes). The imaginary components at the LUTs outputs are
point data. This can be performed in MATLAB software [10]. multiplied by their respective (e.g. at the same time sample)
In fix-point arithmetic, in here, negative numbers are imaginary components of the DPD input signal (input signal
represented by 2’s complement. The block diagram of the without changes). In the sequence, for each time sample, the
DPD suitable for fix-point arithmetic is shown in Fig.3. subtraction of those multiplications aforementioned are
Observe that it implements (2) when the memory length M is computed and, finally, the real component at the DPD output
truncated to 1. is just the sum of the results at each time sample. The
imaginary component at the DPD output is acquired by
performing similar multiplication and sum operations, as
illustrated in Fig. 3.
 The block diagram is then written in VHDL language. To estimate the DPD power consumption, again computer
Observe that the VHDL code must be capable of: adding two simulations were performed in the software ISE Design Suite
signals, processing a signal through a LUT having 1 input [11] for the specific FPGA Xilinx Virtex5 LX50T. Once
and 2 outputs and multiplying two signals. The codes to more, the number of bits was fixed to 16, e.g. 15 precision
perform these operations can be handled to make the bits plus 1 parity bit. The power consumption for the
operations faster and more efficient. The Adders and sequential circuit is not too high. The FPGA uses
Multipliers needed were provided by the VHDL library. approximated 4,401 slices LUTs and the same number of
However, using the standard libraries, the optimization LUT flip flops. The estimated power consumption is 0.560
cannot be done. Some tests were made, and whatever W. This quantity is very low compared with total slices LUTs,
changes were, there were no better results than the ordinary for instance, it corresponds for just 15% of the total one.
libraries codes. Yet, the LUTs were created and optimized as
possible.
IV. Validation
To evaluate the accuracy of the designed DPD, the real and
imaginary components at the DPD output can be converted
from fix-point to float-point data. This can be performed in Computer simulations were performed to validate the DPD
MATLAB software [10]. design. The fix-point MP DPD scheme shown in Fig. 3 was
simulated on the ISE Design Suite from Xilinx. The device-
A. Real-time DPD processing under-test (DUT) is a PA behavioral model that represents
As the DPD must be applicable in real-time and it must experimental data measured on a GaN-based PA, operating in
have an operating frequency as high as 100 MHz, the total class AB and having a center frequency of 900 MHz. The MP
time for processing a signal through the DPD cannot exceed topology of (1) was also chosen for the PA behavioral model.
10 ns. Furthermore, observe that, in according to Fig. 3, the The excitation signal is a 3GPP WCDMA signal. To
processing of a signal through the DPD demands for a measure the linearity (or, conversely, the distortion) provided
minimal sequence of 6 operations, where each operation by the PA under test, it is used the ACPR (Adjacent Channel
depends of the outcome of the former. These operations are Power Ratio) metric. ACPR is obtained by the ratio between
restricted to the addition, multiplication or processing the powers in the adjacent and main signal channels. In this
through a LUT. section, it was used a bandwidth of 3.84 MHz for both
Computer simulations were performed in the software ISE channels and also a 5 MHz separation between the center
Design Suite [11] for the specific FPGA Xilinx Virtex5 in frequencies of the adjacent and main channels.
specify LX50T. Specifically, Post-and-route simulations were To assess the accuracy of the designed fix-point DPD, the
done to estimate the time delays in computing each one of the ACPR metric at the PA output is computed for the cases with
three basic operations. The number of bits was fixed to 16, and without pre-distortion. For a fair comparison, the PA
e.g. 15 precision bits plus 1 parity bit. Simulation results average output power is the same in both scenarios. Fig. 4
show that the time delay generated by the addition operation shows the power spectral densities (PSD) at the PA output.
is about to 9 ns, by the multiplication operation is about to 16 Note that, by the inclusion of the designed DPD, the ACPR at
ns and by the processing through the LUT is about to 10 ns. the PA output was reduced by xx dB, in this way validating
With these delays, the real-time implementation of the DPD the presented linearizer design.
based solely on combinational logic is not feasible because the
total delay limits the maximum operating frequency of the
DPD in 60 MHz. -50
It then becomes necessary to include sequential logic. If input signal
this is done, the maximum operating frequency of the DPD is
Po we r Sp e ctra l D e n sity (d B)

linearized out PA
limited only by the larger individual delay, which in this case unlinearized out PA
is the multiplication delay and, therefore, the DPD frequency
can be as high as 60 MHz. A consequence of including -100
sequential logic in the design is that the DPD output signal
has a delay, with respect to the DPD input signal, larger than
one clock period. Based on Fig. 3, it can be seen that a
possible DPD implementation in real-time using also
-150
sequential logic requires that the DPD output has a fixed
delay, with respect to the DPD input, of at least 6 clock 880 890 900 910 920 930
Frequency (MHz)
periods.
Fig. 4. Power Spectral Density.
B. DPD Power Consumption
Finally, in Fig. 5 is shown the amplitude of the PA output
signal as a function of the amplitude of the excitation signal
(the AM-AM plot) for the unlinearized and linearized PA. Acknowledgement
Observe that the unlinearized PA exhibits memory effects (by
The authors would also like to acknowledge the financial
the scattering pattern of the AM-AM plot). The DPD was
support provided by UPFR/TN under the Program UFPR
able to compensate for mostly of the nonlinear and memory
Iniciação Científica 2012-2013.
effects.
A m p litu d e o f th e o u tp u t v o lt a g e

0.4 References
[1] Gilabert,P.L; Cesari, A; Montoro, G; Bertran, E; Dilhac, J.
0.3 Multi-Lookup Table FPGA Implementation of an Adaptive
Digital Predistorter for Linearizing RF Power Amplifiers With
Memory Effects. IEE TRANSACTIONS ON MICROWAVE
THEORY AND TECHNIQUES, v. 56, n. 2, 2008.
0.2 [2] Guan, Lei; Zhu, Anding; Low-Cost FPGA Implementation of
Volterra Series-Based Digital Predistorter for RF Power
Amplifiers. IEE TRANSACTIONS ON MICROWAVE
0.1 linearized PA THEORY AND TECHNIQUES, v. 58, n. 4, 2010.
[3] GONZÁLEZ, D.R.L. Automatic Design-Space Exploration of
unlinearized PA Integrated Multi-Standard Wireless Radio Receivers.
Stockolm, 2006. Tese (Licenciatura) – KTH Information and
0 Communication Technology.
0 0.1 0.2 0.3 0.4 [4] Cui, Xian. Efficient Radio Frequency Power Amplifiers for
Amplitude of the input voltage Wireless Communications. Ohio, 2007. Tese (Doutorado em
Engenharia Elétrica) – The Ohio State University.
Fig. 5. AM-AM plot of unlinearized and linearized PA. [5] Kwan, A; Ghannouchi, F.M; Hammi, O; Helaoui, M; Smith,
M.R. Look-up table-based digital predistorter implementation
V. Conclusions for field programmable gate arrays using long-term evolution
signals with 60 MHz bandwidth. IET SCIENCE,
In this paper it was presented a fix-point design of a MEASUREMENT AND TECHNOLOGY, 2012.
[6] P. B. Kenington, High Linearity RF Amplifier Design.
digital pre-distorter for linearizing wireless transmitters in
Norwood, MA: Artech House, 2000.
order to improve its efficiency. The DPD has a memory [7] J. Kim and K. Konstantinou, “Digital predistortion of wideband
polynomial topology. The most important aspects concerning signals based on power amplifier model with memory,”
its practical implementation (real-time and power Electron. Lett., vol. 37, no. 23, pp. 1417–1418, Nov. 2001.
consumption) in a low-cost hardware such as a FPGA were [8] E. Lima, T. Cunha, H. Teixeira, M. Pirola, J. Pedro, “Base-band
investigated in order to assert the applicability of the designed derived volterra series for power amplifier modeling’’,
microwave symposium digest, 2009. mtt '09. ieee mtt-s
DPD. The accuracy of the designed DPD was validated based international, pp. 1361-1364, 2009.
on computer simulations under a PA behavioral model, [9] C. Eun and E. J. Powers, “A new Volterra predistorter based on
illustrating an improvement in the ACPR metric at the PA the indirect learning architecture,” IEEE Trans. Signal
output of 25 dB. Process., vol. 45, no. 1, pp. 223–227, Jan. 1997.
[10]MATLAB The MathWorks Inc., Natick, MA.
http://www.mathworks.com/help/matlab/
[11] ISE Design Suite 14.5 Xilinx, 2013.