FILE FORMATS

FILES:

1. .LIB
2. .LEF
3. .DEF
4. .GDS II
5. .SPEF
6. PV RULE DECKS

1. . LIB

Contents:

 Operating conditions (PVT)

 WLM (Wire Load Model)
 Control Parameters
 Delay information in terms TLU (table look-up model)
 Cell level Information

Operating Conditions

It contains operating conditions like BC, WC, Typical, which are based on PVT (Process
Voltage Temperature) condition.

wire_load_table (WLM)

You can use the wire_load_table to estimate accurate connect delay. This WLM is more
flexible, because wire capacitance and resistance no longer have to be strictly
proportional to each other.

Control parameters

K-Factors: The K-Factors are nothing but Scaling factors.

Delay information

Delay values will be captured in terms of TLU (table look-up model) based on the input
transition versus output load.

Cell level Information contains:

 Cell Name
 Area
 Power
 Functionality
 Delay
 Maximum capacitance
 Maximum transition

Area: Area can be represented in two ways.

NAND Equivalent area
Absolute area

Power

Power is defined in library in three ways:

 Switching Power: power is calculated when input and output transition occurs.
 Leakage Power: due to diffusion to substrate current and transistor current in non-
conducting mode.
 Internal Power: This power is calculated when input is changing and output is not
changing.

Maximum capacitance

Maximum transition

Directions for the pins defined

Ex: direction: "input";
Example

library ("cs104mn_uc_aob_t_p25_12v") {

delay_model : "table_lookup"; /* delay model is defined

in_place_swap_mode : "match_footprint"; (TLU) */
time_unit : "1ps"; /* units are defined in
voltage_unit : "1V"; this section */
current_unit : "1mA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1pW";
capacitive_load_unit(1.000000, \
"pf");
slew_upper_threshold_pct_rise : 80; /* slew is defined here */
slew_lower_threshold_pct_rise : 20;
slew_upper_threshold_pct_fall : 80;
slew_lower_threshold_pct_fall : 20;
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
nom_process : 1; /* nominal PVT condition
nom_voltage : 1.2; is set here */
nom_temperature : 25;
simulation : true;
library_features("report_delay_calculation");
k_process_setup_fall : 0; /* Here control parameters
k_process_setup_rise : 0; are defined */
k_process_hold_fall : 0;
k_process_hold_rise : 0;
k_process_recovery_fall : 0;
k_process_recovery_rise : 0;
k_process_removal_fall : 0;
k_process_removal_rise : 0;
k_process_min_pulse_width_high : 0;
k_process_min_pulse_width_low : 0;
k_process_min_period : 0;
k_process_cell_rise : 0;
k_process_cell_fall : 0;
k_process_wire_res : 0;
k_process_cell_leakage_power : 0;
k_process_internal_power : 0;
k_process_wire_cap : 0;
k_process_rise_transition : 0;
k_process_fall_transition : 0;
 k_process_pin_cap : 0;
k_temp_setup_fall : 0;
k_temp_setup_rise : 0;
k_temp_hold_fall : 0;
k_temp_hold_rise : 0;
k_temp_min_period : 0;
k_temp_min_pulse_width_high : 0;
k_temp_min_pulse_width_low : 0;
k_temp_recovery_fall : 0;
k_temp_recovery_rise : 0;
k_temp_cell_rise : 0;
k_temp_rise_transition : 0;
k_temp_cell_fall : 0;
k_temp_fall_transition : 0;
k_temp_pin_cap : 0;
k_temp_wire_cap : 0;
k_temp_wire_res : 0;
k_temp_cell_leakage_power : 0;
k_temp_internal_power : 0;
k_volt_setup_fall : 0;
k_volt_setup_rise : 0;
k_volt_hold_fall : 0;
k_volt_hold_rise : 0;
k_volt_min_period : 0;
k_volt_min_pulse_width_high : 0;
k_volt_min_pulse_width_low : 0;
k_volt_recovery_fall : 0;
k_volt_recovery_rise : 0;
k_volt_cell_rise : 0;
k_volt_rise_transition : 0;
k_volt_cell_fall : 0;
k_volt_fall_transition : 0;
k_volt_pin_cap : 0;
k_volt_wire_cap : 0;
k_volt_wire_res : 0;
k_volt_cell_leakage_power : 0;
k_volt_internal_power : 0;
slew_derate_from_library : 1;
default_fanout_load : 1;
default_max_fanout : 100;
default_inout_pin_cap : 0;
default_input_pin_cap : 0;
default_output_pin_cap : 0;
default_cell_leakage_power : 0;
power_supply () {
default_power_rail : "VDD3";
 power_rail("VDD3",1.200000);
}
operating_conditions (t_p25_12v) { /* operating conditions are set
process : 1; based on PVT condition */
temperature : 25;
voltage : 1.2;
tree_type : "best_case_tree";
power_rail("VDD3",1.200000);
}

lu_table_template ("delay_template_7x7") { /* This is the TLU */

variable_1 : "total_output_net_capacitance";
variable_2 : "input_net_transition";
index_1("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0, 1006.0");
index_2("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0, 1006.0");
}
power_lut_template ("energy_template_7x7") {
variable_1 : "total_output_net_capacitance";
variable_2 : "input_transition_time";
index_1("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0, 1006.0");
index_2("1000.0, 1001.0, 1002.0, 1003.0, 1004.0, 1005.0, 1006.0");
}
default_operating_conditions : "t_p25_12v"; /* This PVT is defined for
cell (SCGAOBWSCLXL1) { a specific cell */
area : 480; /* area and leakage
cell_leakage_power : 2924.76; power */
rail_connection("VDDG", \
"VDD3");
cell_footprint : "MAOBWSCL";
always_on : true;
pin (A) { /* input pin of the cell
direction : "input"; and it’s attributes are
input_signal_level : "VDD3"; defined */
capacitance : 0.00606645;
rise_capacitance : 0.00606645;
fall_capacitance : 0.00605854;
fanout_load : 1;
max_transition : 600;
always_on : true;
internal_power () {
power_level : "VDD3";
power (scalar) {
values("0");
}
}
 }
pin (Y) { /* output pin of the cell and it’s
direction : "output"; attributes */
output_signal_level : "VDD3";
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 2.07334;
function : "A";
timing () {
related_pin : "A";
timing_sense : "positive_unate";
cell_rise ("delay_template_7x7") {
cell_rise ("delay_template_7x7") {
index_1("0.001, 0.01, 0.031, 0.082, 0.306, 1.02, 2.244");
index_2("2.999, 59.948, 119.462, 249.302, 499.468, 986.563, 1978.26");
values("23.953, 41.679, 51.607, 64.947, 81.077, 99.969, 122.007", \
"29.655, 47.737, 58.297, 72.803, 90.023, 110.201, 133.667", \
"40.071, 58.425, 69.339, 85.078, 104.605, 127.949, 155.353", \
"62.673, 81.178, 92.096, 108.1, 129.495, 157.364, 192.815", \
"159.286, 177.949, 188.864, 204.697, 226.026, 255.969, 300.458", \
"466.779, 485.412, 496.216, 511.842, 533.06, 563.114, 612.062", \
"993.647, 1012.39, 1023.07, 1038.36, 1060.05, 1090.36, 1139.03");
}
internal_power () {
related_pin : "A";
power_level : "VDD3";
rise_power ("energy_template_7x7") {
index_1("0.001, 0.01, 0.031, 0.082, 0.306, 1.02, 2.244");
index_2("2.999, 59.948, 119.462, 249.302, 499.468, 986.563, 1978.26");
values("0.012579, 0.012612, 0.013686, 0.016711, 0.023619, 0.038246, 0.069164", \
"0.013018, 0.012613, 0.013456, 0.016067, 0.022269, 0.035976, 0.065692", \
"0.013628, 0.012873, 0.013492, 0.015841, 0.021559, 0.034307, 0.062474", \
"0.014049, 0.013219, 0.01379, 0.015887, 0.021271, 0.033434, 0.06021", \
"0.01428, 0.013665, 0.014222, 0.016225, 0.021374, 0.032895, 0.058347", \
"0.014337, 0.013854, 0.014442, 0.016505, 0.021636, 0.033016, 0.057885", \
"0.014325, 0.013859, 0.014466, 0.016607, 0.021743, 0.03306, 0.05784");
}
fall_power ("energy_template_7x7") {
index_1("0.001, 0.01, 0.031, 0.082, 0.306, 1.02, 2.244");
index_2("1.492, 59.887, 119.751, 249.567, 496.399, 987.818, 2026.1");
values("0.019538, 0.020094, 0.021296, 0.0246, 0.031562, 0.046431, 0.079092", \
"0.020358, 0.020167, 0.021088, 0.023861, 0.030076, 0.04402, 0.075786", \
"0.021195, 0.020554, 0.021329, 0.023713, 0.02937, 0.04222, 0.071929", \
"0.021637, 0.021051, 0.021751, 0.023977, 0.029295, 0.041439, 0.069474", \
"0.021858, 0.021512, 0.022249, 0.024482, 0.029679, 0.041371, 0.068229", \
 "0.021924, 0.021661, 0.022448, 0.024753, 0.02998, 0.041687, 0.068107", \
"0.021938, 0.021703, 0.022514, 0.024819, 0.030094, 0.041797, 0.068263");
}
}
}
}
cell (SCGAOBWSCLXP1) {
area : 576;
cell_leakage_power : 5606.21;
rail_connection("VDDG", \
"VDD3");
cell_footprint : "MAOBWSCL";
always_on : true;
pin (A) {
direction : "input";
input_signal_level : "VDD3";
capacitance : 0.0115693;
rise_capacitance : 0.0115693;
fall_capacitance : 0.0115561;
fanout_load : 1;
max_transition : 600;
always_on : true;
internal_power () {
power_level : "VDD3";
power (scalar) {
values("0");
}
}
}
pin (Y) {
direction : "output";
output_signal_level : "VDD3";
capacitance : 0;
rise_capacitance : 0;
fall_capacitance : 0;
max_capacitance : 4.09729;
function : "A";
timing () {
related_pin : "A";
timing_sense : "positive_unate";
cell_rise ("delay_template_7x7") {
index_1("0.001, 0.02, 0.061, 0.162, 0.608, 2.025, 4.455");
index_2("2.999, 59.979, 119.38, 249.308, 499.526, 986.242, 1977.42");
values("24.073, 40.955, 50.158, 62.433, 75.913, 89.999, 101.547", \
"30.358, 47.545, 57.26, 70.462, 85.119, 100.54, 113.582", \
"40.912, 58.31, 68.307, 82.519, 99.283, 117.683, 134.223", \
 "63.766, 81.397, 91.484, 106.054, 124.175, 146.446, 170.922", \
"161.123, 178.93, 188.821, 203.259, 221.456, 245.607, 278.405", \
"469.363, 486.962, 496.916, 511.198, 529.713, 553.748, 590.217", \
"997.524, 1015.07, 1025.32, 1039.53, 1057.04, 1081.56, 1118.21");
}
rise_transition ("delay_template_7x7") {
index_1("0.001, 0.02, 0.061, 0.162, 0.608, 2.025, 4.455");
index_2("2.999, 59.979, 119.38, 249.308, 499.526, 986.242, 1977.42");
values("9.046, 10.679, 12.831, 16.758, 23.079, 33.398, 51.137", \
"15.059, 16.458, 18.453, 22.368, 28.929, 39.42, 57.18", \
"27.517, 28.504, 29.864, 32.911, 39.572, 51.295, 70.798", \
"59.098, 59.552, 60.055, 61.562, 65.68, 75.737, 98.058", \
"201.747, 201.973, 202.024, 202.408, 203.352, 207.047, 219.452", \
"656.932, 657.05, 657.02, 656.836, 657.484, 659.276, 664.523", \
"1437.82, 1438.13, 1437.95, 1437.35, 1437.79, 1438.59, 1439.3");
}

Cell_fall
Fall_transition

2. Physical Library(.LEF - Library Exchange format)

This file is mainly characterized into three types

 Technology LEF
 Cell LEF
 Macro LEF

Technology LEF: A technology LEF file contains all of the LEF technology information
for a design, such as placement and routing design rules, and process information for
layers. A technology LEF file can include any of the following LEF statements:

 Available metal layers

 Design rules
 Spacing between the layers
 Minimum width of the layer
 Pitch
 Minimum area
 Minimum hole
 Capacitance per square unit
 Resistance per square unit
 Layer directions
  Via information
 Bottom layer
 Cut layer
 Top layer

Cell LEF: A cell library LEF file contains the standard cell information for a design. A
library LEF file can include any of the following statements:

 Dimensions of standard cell

 Area
 Pins information like direction of pins

Macro LEF: A Macro library LEF file contains the Macro information which includes
the following statements:

 Macro dimensions
 Metal layer information like how many layers used in this macro
 Direction of the pins
 Blockage information.

LEF file format:

Routing Layer definition

LAYER layerName
TYPE ROUTING ;
DIRECTION {HORIZONTAL | VERTICAL} ;
PITCH distance;
WIDTH defWidth;
OFFSET distance ;
SPACING minSpacing;
RESISTANCE RPERSQ value ;
Specifies the resistance for a square of wire, in ohms per square. The resistance of a wire
can be defined as RPERSQU x wire length/wire width

Same-Net Spacing
SPACING
SAMENET layerName layerName minSpace [STACK] ; ...
END SPACING
Defines the same-net spacing rules. Same-net spacing rules determine minimum
spacing between geometries in the same net and are only required if same-net spacing
is smaller than different-net spacing, or if vias on different layers have special
stacking rules. These specifications are used for design rule checking by the routing and
verification tools. Spacing is the edge-to-edge separation, both orthogonal and diagonal.
Macro Pin Statement
PIN pinName
FOREIGN foreignPinName [STRUCTURE [pt [orient] ] ] ;
[DIRECTION {INPUT | OUTPUT [TRISTATE] | INOUT | FEEDTHRU} ;]
[USE { SIGNAL | ANALOG | POWER | GROUND | CLOCK } ;]
[SHAPE {ABUTMENT | RING | FEEDTHRU} ;]
[MUSTJOIN pinName ;]
{PORT
[CLASS {NONE | CORE} ;]
{layerGeometries} ...
END} ...
END pinName]

EG:

MACRO LEF file contents:

MACRO dpram_4096x32
CLASS BLOCK ;
FOREIGN dpram_4096x32 0 0 ;
ORIGIN 0.000 0.000 ;
SIZE 1797.220 BY 879.720 ;
SYMMETRY X Y R90 ;
PIN A1[2]
DIRECTION INPUT ;
ANTENNAPARTIALMETALSIDEAREA 10.536 LAYER M3 ;
ANTENNADIFFAREA 0.001 LAYER M3 ;
ANTENNAPARTIALCUTAREA 0.068 LAYER V3 ;
ANTENNAGATEAREA 0.671 LAYER M3 ;
PORT
LAYER M2 ;
RECT 904.740 0.000 905.020 0.740 ;
LAYER M3 ;
RECT 904.740 0.000 905.020 0.280 ;
END
END A1[2]
PIN A1[3]
DIRECTION INPUT ;
ANTENNAPARTIALMETALSIDEAREA 5.576 LAYER M3 ;
ANTENNADIFFAREA 0.001 LAYER M3 ;
ANTENNAPARTIALCUTAREA 0.068 LAYER V3 ;
ANTENNAGATEAREA 0.671 LAYER M3 ;
PORT
LAYER M2 ;
RECT 904.180 0.000 904.460 0.740 ;
 LAYER M3 ;
RECT 904.180 0.000 904.460 0.280 ;
END

Tech LEF:

LAYER M1
TYPE ROUTING ;
WIDTH 0.230 ;
SPACING 0.230 ;
SPACING 0.6 RANGE 10.0 35.0 ;
SPACING 0.6 RANGE 35.001 100000.0 ;
PITCH 0.560 ;
DIRECTION HORIZONTAL ;
CAPACITANCE CPERSQDIST 3.84e-05 ;
RESISTANCE RPERSQ 12.0e-2 ;
EDGECAPACITANCE 9.02e-05 ;
HEIGHT 1.135 ;
THICKNESS 0.53 ;
AREA 0.202 ;
MINIMUMCUT 2 WIDTH 1.40 ;
AntennaSideAreaRatio 400 ;
AntennaDiffSideAreaRatio PWL ( ( 0 400 ) ( 0.203 400 ) ( 0.204 2281.6 ) ( 1 2600 ) ) ;
END M1

STD. CELL LEF:

MACRO xr03d7
CLASS CORE ;
FOREIGN xr03d7 0 0 ;
ORIGIN 0.000 0.000 ;
SIZE 13.440 BY 5.600 ;
SYMMETRY X Y R90 ;
SITE CoreSite ;
PIN Z
DIRECTION OUTPUT ;
ANTENNADIFFAREA 4.960 LAYER M1 ;
PORT
LAYER M1 ;
RECT 10.880 2.660 13.320 2.900 ;
RECT 12.900 1.230 13.320 2.900 ;
RECT 9.340 1.230 13.320 1.470 ;
RECT 10.880 2.660 11.120 4.340 ;
RECT 9.490 3.520 11.120 3.760 ;
END
END Z
 PIN A3
DIRECTION INPUT ;
ANTENNAGATEAREA 0.394 LAYER M1 ;
PORT
LAYER M1 ;
RECT 0.620 2.670 1.060 3.580 ;
END

3. SPEF:

SPEF stands for Standard Parasitic Exchange Format. It contains the parasitics extracted
from the layout. PD Engineers needs this information to do post layout STA.

SPEF file example

 General Syntax
A typical SPEF file will have 4 main sections
 A header section,
 A name map section,
 A top level port section and
 The main parasitic description section.
Generally, SPEF keywords are preceded with a *. For example, *R_UNIT, *NAME_MAP
and *D_NET.
Comments start anywhere on a line with // and run to the end of the line. Each line in a
block of comments must start with //.

 Header Information
The header section is 14 lines containing information about
– the design name,
– the parasitic extraction tool,
– naming styles
– and units.
When reading SPEF, it is important to check the header for units as they vary across
tools. By default, SPEF from Astro will be in pF and kOhm while SPEF from Star-RCXT will
be in fF and Ohm.

 Name Map Section

To reduce file size, SPEF allows long names to be mapped to shorter numbers preceded
by a *. This mapping is defined in the name map section. For example:
*NAME_MAP
*509 F_C_EP2
*510 F_C_EP3
*511 F_C_EP4
*512 F_C_EP5
*513 TOP/BUF_ZCLK_2_pin_Z_1
*514 TOP/BUF_ZCLK_3_pin_Z_1
*515 TOP/BUF_ZCLK_4_pin_Z_1
Later in the file, F_C_EP2 can be referred to by its name or by *509.

 Port Section
The port section is simply a list of the top level ports in a design. They are also annotated
as input, output or bidirect with an I, O or B. For example:
*PORTS
*1 I
*2 I
*3 O
*4 O
*5 O
*6 O
*7 O
*8 B
*9 B

 Parasitics
Each extracted net will have a *D_NET section. This will usually consist of a *D_NET line,
a *CONN section, a *CAP section, *RES section and a *END line.
*D_NET regcontrol_top/GRC/n13345 1.94482
*CONN
*I regcontrol_top/GRC/U9743:E I *C 537.855 9150.11 *L 3.70000
*I regcontrol_top/GRC/U9409:A I *C 540.735 9146.02 *L 5.40000
*I regcontrol_top/GRC/U9407:Z O *C 549.370 9149.88 *D OR2M1P
*CAP
1 regcontrol_top/GRC/U9743:E 0.936057
2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z 0.622675
3 regcontrol_top/GRC/U9407:Z 0.386093
*RES
1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916
2 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9409:A 8.07710
3 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U9407:Z 11.9156
*END
The *D_NET line tells the net name and the net's total capacitance. This capacitance will
be the sum of all the capacitances in the *CAP section.

 *CONN Section
The *CONN section lists the pins connected to the net. A connection to a cell instance
starts with a *I. A connection to a top level port starts with a *P.
The syntax of the *CONN entries is:
*I <pin name> <direction> *C <xy coordinate> <loading or driving information>
  CAP Section
The *CAP section provides detailed capacitance information for the net. Entries in the
*CAP section come in two forms, one for a capacitor lumped to ground and one for a
coupled capacitor.
A capacitor lumped to ground has three fields,
 an identifying integer,
 a node name and
 the capacitance value of this node
E.g
 1 regcontrol_top/GRC/U9743:E 0.936057
A coupling capacitor has four fields,
 an identifying integer,
 two node names and
 The values of the coupling capacitor between these two nodes
E.g
 2 regcontrol_top/GRC/U9409:A regcontrol_top/GRC/U10716:Z
0.622675
If netA is coupled to netB, the coupling capacitor will be listed in each net's *CAP
section.

 RES Section
The *RES section provides the resistance network for the net.
Entries in *RES section contain 4 fields,
 an identifying integer,
 two node names and
 the resistance between these two nodes.
 E.g
 1 regcontrol_top/GRC/U9743:E regcontrol_top/GRC/U9407:Z 10.7916
The resistance network for a net can be very complex. SPEF can contain resistor loops or
seemingly ridiculously huge resistors even if the layout is a simple point to point route.
This is due how the extraction tool cuts nets into tiny pieces for extraction and then
mathematically stitches them back together when writing SPEF.

4. DEF:

Design Exchange Format (DEF) is an open specification for representing physical

layout of an integrated circuit in an ASCII format. It represents the netlist and circuit
layout. DEF is used in conjunction with Library Exchange Format (LEF) to represent
complete physical layout of an integrated circuit while it is being designed.
VERSION 5.7 ;
DIVIDERCHAR "/" ;
BUSBITCHARS "[]" ;
DESIGN ********* ;
UNITS DISTANCE MICRONS 1000 ;

PROPERTYDEFINITIONS
COMPONENTPIN designRuleWidth REAL ;
DESIGN FE_CORE_BOX_LL_X REAL -2749.680 ;
DESIGN FE_CORE_BOX_UR_X REAL 2750.000 ;
DESIGN FE_CORE_BOX_LL_Y REAL -2719.680 ;
DESIGN FE_CORE_BOX_UR_Y REAL 2720.000 ;
END PROPERTYDEFINITIONS

DIEAREA ( -3000000 -2970000 ) ( 3000000 2970000 ) ;

ROW IO_ROW_0 IOSite 2773990 -2960000 N DO 21601 BY 1 STEP 10 0 ;

ROW CORE_ROW_0 CoreSite -2749680 -2719680 FS DO 9820 BY 1 STEP 560 0 ;

- via45Array_265
+ VIARULE via45Array
+ CUTSIZE 260 260
+ LAYERS M4 V5 M5
+ CUTSPACING 290 290
+ ENCLOSURE 220 245 220 245
+ ROWCOL 36 27
;

REGIONS 7 ;
- *********** ( 2210240 -2708480 ) ( 2466160 -2658080 ) ;
END REGIONS

COMPONENTS ****
- ******** + PLACED ( -1125120 -1118080 ) S
;
END COMPONENTS
END DESIGN;
DEF Routing

+ ROUTED M2 20000 + SHAPE STRIPE ( -1335180 -2743760 ) ( * -121410 )

+ FIXED TOP_M 30000 + SHAPE STRIPE ( -1174090 -2713005 ) ( * -121510 )
+ ROUTED M3 3000 + SHAPE BLOCKWIRE ( -1497230 -113490 ) ( -1469855 * )
NEW M3 3000 + SHAPE BLOCKWIRE ( -1497230 -59410 ) ( -1469855 * )
NEW M3 3000 + SHAPE BLOCKWIRE ( -1497230 -5330 ) ( -1469855 * )
NEW M1 1480 + SHAPE COREWIRE ( -1345180 -147180 ) ( -1138040 * )
NEW M1 1480 + SHAPE COREWIRE ( -1345180 -135980 ) ( -1136920 * )
NEW M1 1480 + SHAPE COREWIRE ( -1345180 -124780 ) ( -1136920 * )
NEW M3 3000 + SHAPE BLOCKWIRE ( -1194815 -113490 ) ( -1145740 * )
NEW M3 3000 + SHAPE BLOCKWIRE ( -1194815 -59410 ) ( -1145740 * )
NEW M3 3000 + SHAPE BLOCKWIRE ( -1194815 -5330 ) ( -1145740 * )
+ FIXED M4 10000 + SHAPE STRIPE ( -2749100 -151510 ) ( * 2728590 )
NEW M4 20000 + SHAPE STRIPE ( -1818880 -151510 ) ( * 2728590 )
NEW M4 20000 + SHAPE STRIPE ( -1487230 -151510 ) ( * 901365 )
NEW M4 20000 + SHAPE STRIPE ( -1155740 -151510 ) ( * 914960 )
+ ROUTED M2 20000 + SHAPE STRIPE ( -593135 -2743625 ) ( * 2742420 )
+ FIXED TOP_M 30000 + SHAPE STRIPE ( -381485 -2713005 ) ( * 2728590 )
+ ROUTED M3 3000 + SHAPE BLOCKWIRE ( -2754100 38420 ) ( -2730595 * )
NEW M3 3000 + SHAPE BLOCKWIRE ( -2754100 92500 ) ( -2730595 * )
 NEW M5 10000 + SHAPE BLOCKWIRE ( -2784045 37095 ) ( -2744100 * )
NEW M5 10000 + SHAPE BLOCKWIRE ( -2784045 98040 ) ( -2744100 * )

5. .GDS (Graphic Database System) :

GDS II stream format, is a database file format which is the industry standard for data
exchange of integrated circuit or IC layout artwork. It is a binary file format representing
planar geometric shapes, text labels, and other information about the layout in
hierarchical form.

GDS II files are usually the final output product of the IC design cycle and are given to
IC foundries for IC fabrication.

Layer information is represented in numbers. Mapping of layers to numbers is provided

by Fab/Technology vendor.

Layer purposes are

 Drawing
 Dummy
 Slot
 Pin
 Label

The file has the following four columns:

1. layerObjName: Specifies one of the following objects

a) LEF layer name: Specifies a LEF layer from the LAYER statement in the
LEF technology file.
b) COMP: Specifies component outlines.
c) DIEAREA: Specifies the chip boundary.
d) NAME: Specifies a text label for the layer name and associated object
type.

2. layerObjType: Specifies one of the following object types

a) ALL: In routing layers, ALL is equivalent to NET, SPNET, VIA, IN,
LEFPIN, FILL,LEFOBS, and VIAFILL. In cut layers, ALL is equivalent
to VIA and VIAFILL.
b) BLOCKAGE: Equivalent to DEF BLOCKAGES without + FILLS.
c) BLOCKAGEFILL: Equivalent to DEF BLOCKAGES with + FILLS.
d) CUSTOM: Applies to addCustomText and addCustomBox information
only.

3. layer Number: Specifies the GDSII layer number. The number must be an
integer between 1 and 65535.
4. data Type: Specifies the GDSII data type. The data type must be an
Integer between 0 and 65535.
Example of a gds file:

METAL1 NET 1 0
METAL1 SPNET 999 0
METAL1 PIN 1000 0
METAL1 LEFPIN 2000 0
METAL1 FILL 3000 0
METAL1 VIA 4000 0
METAL1 VIAFILL 5000 0
METAL1 LEFOBS 10000 0
NAME METAL1/NET 20000 0

LOG SUMMARY REPORT:

Stream Out Information Processed for GDS version 3:

Units: 1000 DBU

Object Count
----------------------------------------
Instances 625477

Ports/Pins 73
metal layer M3 44
metal layer M5 29

Nets 2921470
metal layer M1 15506
metal layer M2 1440283
metal layer M3 1036845
metal layer M4 307679
metal layer M5 85242
metal layer TOP_M 35915

Via Instances 3093078

Special Nets 2826

metal layer M1 1221
metal layer M2 25
metal layer M3 682
metal layer M4 204
metal layer M5 291
metal layer TOP_M 403
Via Instances 5599
Metal Fills 0
Via Instances 0
Metal FillOPCs 0
Via Instances 0
Text 0
Blockages 0
Custom Text 0
Custom Box 0

6. PV RULE DECKS
Rule decks we have in PV are:
 DRC Rule deck
 LVS Rule deck

DRC Rule deck

Typical Rule Deck definitions

 Control Settings
 Input , output Variables

 Layer Mapping

 Layer operations, Derived Layers

 Geometry rule Check definitions

Control Setting

Control Setting or Optional setting customize the general purpose rule specific to design
needs.

Eg:

 //DRC INCREMENTAL CONNECT YES

 //DRC EXCLUDE FALSE NOTCH YES // Please enable this line to
fix violations caused by FALSE NOTCH feature. But the DRC runtime
will increase.

 //LAYOUT ALLOW DUPLICATE CELL YES

 #DEFINE 3.3V // when HIGH_VOLTAGE = 3.3V

  //#DEFINE 2.5V // when HIGH_VOLTAGE = 2.5V

 //#DEFINE 1.8V // when HIGH_VOLTAGE = 1.8V

 #DEFINE FULL_CHIP // when chip corner/sealring is

considered : comment this for block level analysis(sub module)

 #DEFINE BigDieChipCorner // when pentagon shape corner is

wanted for small size chip

 //#DEFINE GUIDELINE // when you want to check ESD

guideline

 //#DEFINE SUGGESTED // when you want to check suggested

rule

 //#DEFINE SRAMDMY_USED_ONLY // replace EXCL and

DMSRM with LOGO and SRAM_DUMMY layers

 //#DEFINE CHECK_DENSITY_IN_ODBLK // include the ODBLK

region to be checked with OD density rules

 //#DEFINE CHECK_DENSITY_IN_DMxEXCL_ONLY // check

metal density only inside the DMxEXCL regions

 //#DEFINE THICK_TOP2_METAL // when M5 and M6 are thick

metal

 //#DEFINE THICK_TOP3_METAL // when M4, M5 and M6 are

thick metal

 //#DEFINE CUP // when CUP (Circuit Under Pad) structure

is used )

Input , Output Variables

Example:

 LAYOUT SYSTEM GDSII

 LAYOUT PATH "GDSFILENAME"

 LAYOUT PRIMARY "TOPCELLNAME"

 DRC RESULTS DATABASE "DRC_RES.db"

 DRC SUMMARY REPORT "DRC.rep"

 LAYOUT ERROR ON INPUT NO // to enable DRC runs without

complete GDS
Layer Mapping

Rule deck has foundry/process specific layer mapping definitions to extract drawn layer
geometries from input GDSII

Example:

 LAYER DNWELLi 1 // DNWELL deep-nwell

 LAYER NWELLi 3 // NWELL nwell technology

 LAYER DIFFi 6 // OD/DIFF diffusion areas

 LAYER PDIFFi 7 // PDIFF diffusion areas

 LAYER NDIFFi 8 // NDIFF diffusion areas

 LAYER DOD 340 // Dummy OD (DIFF)

Geometry rule Check definitions

Rule check statements are active entities of DRC, whereas layer definitions are passive.
The output from a rule check statement can consist of derived polygon layers, derived
edge layers, or derived error layers, or combinations of the three

Example: (comments are represented by “@” “//” or “/* */”)

G.2.METAL5i { @ METAL5i shapes with acute angles between line segments are not allowed.

INT METAL5i < 0.1 ABUT < 90 INTERSECTING ONLY

EXT METAL5i < 0.1 ABUT < 90 INTERSECTING ONLY

G.2.M5SLOTi { @ M5SLOTi shapes with acute angles between line segments are not allowed.

INT M5SLOTi < 0.1 ABUT < 90 INTERSECTING ONLY

EXT M5SLOTi < 0.1 ABUT < 90 INTERSECTING ONLY }

LVS Rule Deck:

Performs comparison Layout versus Schematic in a flat or hierarchical manner.

Calibre LVS extracts nets, devices along with connectivity information from GDS( as
defined in Rule deck) and generated spice netlist for comparison with source spice
(extracted from schematic/ verilog)
 Input & Control variables

 LAYOUT PRIMARY "DEV_013S_NEW“ // top cell name

 LAYOUT PATH
"/dsdhome/hmtseng/LVS_TSMC/013/ALL_PROCESS_COMBO_LVS_DECK/
GDS/DEV_013S_NEW.gds"

 LAYOUT SYSTEM GDSII

 //LAYOUT PATH "layout.net"

 //LAYOUT SYSTEM SPICE

 SOURCE PRIMARY "DEV_013S_NEW"

 SOURCE PATH "DEV_013S_NEW.spi.runo"

 SOURCE SYSTEM SPICE

 LVS REPORT "lvs.rep"

 LVS REPORT MAXIMUM 1000 // ALL

 #IFDEF RC_DECK

 //MASK SVDB DIRECTORY "svdb" QUERY

 #ELSE

 MASK SVDB DIRECTORY "svdb" QUERY

 #ENDIF

 LVS POWER NAME “VDD” “VDDxyz”

 LVS GROUND NAME “VSS” “GND”

Connectivity Extraction

Connectivity extraction recognizes electrically-connected regions in the layout called

nets. Nets are recognized from layout geometries through analysis of the relations
between layout shapes and other objects on various layers. The analysis is driven by
statements you specify in the rule file.

Some of the connectivity extraction operations are:

 Attach
 Connect

 SConnect

Attach: The primary use of the Attach operation is for assigning names to extracted nets.

ATTACH Layer1 Layer2

Connect: Establishes connectivity between abutting or overlapping polygons. Establishes

connectivity through a connecting layer if the BY keyword is used.

Eg:

SCONNECT: Establishes soft connections from an upper layer to lower layers through a
contact layer or without a contact layer.

SCONNECT A B BY CONT

SCONNECT D C

Port Texting

 Port layer specification statements allow you to specify ports in

GDSII
 The Port Layer Text specification statement supports text objects
where the port’s layer, location, and name are the same as the layer,
location, and value of the text object, respectively
Snap shot from rule deck for port text identification & creating connections to nets.

LAYOUT TEXT “PORT_XYZ” <X> <Y> 131 <top_cell>

TEXT DEPTH PRIMARY

PORT DEPTH PRIMARY

TEXT LAYER 131 ATTACH 131 metal1

PORT LAYER TEXT 131

TEXT LAYER 132 ATTACH 132 metal2

PORT LAYER TEXT 132

TEXT LAYER 133 ATTACH 133 metal3

PORT LAYER TEXT 133

Text “PORT_XYZ” on 131 will treated as a PORT and will attached to net on metal1 at
location “X , Y”

Snap shot of Rule Deck

//* Define device -- nmos nch_sram_hvt

ngate_s_hvt = ngate_s4 AND HVTSRM // HVT SRAM NMOS

//* Define device -- nmos NL

gate = gate1 NOT DMSRM

gatennw = gate NOT nxwell // gate not inside nwell

tngate1 = gatennw AND NP

tngate2 = tngate1 NOT OD2

nlgate1 = tngate2 AND NTN

nlgate2 = nlgate1 NOT VTL_N

nlgate3 = nlgate2 NOT VTH_N

nlgate = nlgate3 NOT DNW // CORE Native Devies

DEVICE MN(nch_sram_hvt) ngate_s_hvt poly(G) tndiff(S) tndiff(D) psub(B) <nthin>[

property W,L,AS,AD,PD,PS,NRD,NRS

W=(perimeter_coincide(ngate_s_hvt, tndiff ) + perimeter_inside(ngate_s_hvt, tndiff)) / 2

L=area(ngate_s_hvt) / W

PI_S_OD = perimeter_inside(S,nthin)

IF(PI_S_OD > 0) {

AS = area(S) * W /PI_S_OD

PS = perimeter(S) * W /PI_S_OD

} ELSE { AS=0 PS=0 }

PI_D_OD = perimeter_inside(D,nthin)

IF(PI_D_OD > 0) {

AD = area(D) * W /PI_D_OD

PD = perimeter(D) * W /PI_D_OD

} ELSE { AD=0 PD=0 }

NRS = AS / W / W

NRD = AD / W / W