Features

• Compatible with MCS-51®Products

• 8K Bytes of In-System Programmable (ISP) Flash
Memory – Endurance: 1000 Write/Erase Cycles
• 4.0V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Fast Programming Time
• Flexible ISP Programming (Byte and Page Mode)

Description
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on
a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a 8-bit
highly-flexible and cost-effective solution to many embedded control applications.
Microcontroller
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, with 8K Bytes
a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S52 is designed with static logic for operation In-System
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and Programmable
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next Flash
interrupt or hardware reset.
AT89S52
 1919B–MICRO–11/03

PIN
CONFIGURATION

(T2) P1.0 1 40 VCC

(AD0
(T2 EX) P1.1 2 39 P0.0 )

(AD1
P1.2 3 38 P0.1 )

(AD2
P1.3 4 37 P0.2 )

(AD3
P1.4 5 36 P0.3 )

(AD4
(MOSI) P1.5 6 35 P0.4 )

(AD5
(MISO) P1.6 7 34 P0.5 )

(AD6
(SCK) P1.7 8 33 P0.6 )

(AD7
RST 9 32 P0.7 )

1
(RXD) P3.0 0 31 EA/VPP

1
(TXD) P3.1 1 30 ALE/PROG
 1
(INT0) P3.2 2 29 PSEN

1
(INT1) P3.3 3 28 P2.7 (A15)

1
(T0) P3.4 4 27 P2.6 (A14)

1
(T1) P3.5 5 26 P2.5 (A13)

1
(WR) P3.6 6 25 P2.4 (A12)

1
(RD) P3.7 7 24 P2.3 (A11)

1
XTAL2 8 23 P2.2 (A10)

1
XTAL1 9 22 P2.1 (A9)

2
GND 0 21 P2.0 (A8)
Pin Description
Supply
VCC voltage.

GND Ground.

Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink
eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-
ups.
Port 0 also receives the code bytes during Flash programming and outputs the code
bytes during program verification. External pull-ups are required during program
verification.

Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled
high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
exter-
nally being pulled low will source current (IIL) because of the internal pull-ups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count
input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and
verification.
Port Pin Alternate Functions
P1.0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)

Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled
high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
exter-
nally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2
emits
the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash
programming and verification.

Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled
high
 by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are
exter-
nally being pulled low will source current (IIL) because of the pull-ups.

AT89S5
2
 AT89S5
2
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S52, as shown
in
the following table.
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)

RST Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives high for 98 oscillator periods after the Watchdog times
out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature.
In

the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG Address Latch Enable (ALE) is an output pulse for latching the low byte of the address
during accesses to external memory. This pin is also the program pulse input (PROG)

during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency
and
may be used for external timing or clocking purposes. Note, however, that one

ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With
the
bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in

external execution mode.

Program Store Enable (PSEN) is the read strobe to external program memory.
PSE
N
When the AT89S52 is executing code from external program memory, PSEN is acti-
vated twice each machine cycle, except that two PSEN activations are skipped during

each access to external data memory.

EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (V
PP) during Flash
programming.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

 A map of the on-chip memory area called the Special Function Register (SFR) space is
Special Function shown in Table 1.
Registers
Note that not all of the addresses are occupied, and unoccupied addresses may not be
implemented on the chip. Read accesses to these addresses will in general return ran-
dom data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in
future products to invoke new features. In that case, the reset or inactive values of the
new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in
Table 2) and T2MOD (shown in Table 6) for Timer 2. The register pair (RCAP2H,
RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit
auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two pri-
orities can be set for each of the six interrupt sources in the IP register.

Table 1. AT89S52 SFR Map and Reset Values

0FF
H

0F8H

0F7
0F0H B H
00000000

0EF
0E8H H

0E7
0E0H ACC H
00000000

0DF
0D8H H

0D7
0D0H PSW H
00000000

0CF
0C8H T2CON T2MOD RCAP2L RCAP2H TL2 TH2 H
00000000 XXXXXX00 00000000 00000000 00000000 00000000

0C7
0C0H H

0BF
0B8H IP H
XX000000
 0B7
0B0H P3 H
11111111

0AF
0A8H IE H
0X000000

0A7
0A0H P2 AUXR1 WDTRST H
11111111 XXXXXXX0 XXXXXXXX

98H SCON SBUF 9FH

00000000 XXXXXXXX

90H P1 97H
11111111

88H TCON TMOD TL0 TL1 TH0 TH1 AUXR 8FH

00000000 00000000 00000000 00000000 00000000 00000000 XXX00XX0

80H P0 SP DP0L DP0H DP1L DP1H PCON 87H

11111111 00000111 00000000 00000000 00000000 00000000 0XXX0000

AT89S5
6 2
1919B–MICRO–11/03
 AT89S5
2

Table 2. T2CON – Timer/Counter 2 Control Register

T2CON Address =
0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
7 6 5 4 3 2 1 0

Symbol Function
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK =
TF2 1
or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit
clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
EXEN2 Timer
2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Start/Stop control for Timer 2. TR2 = 1 starts the
TR2 timer.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
C/T2 triggered).
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
 7

1919B–MICRO–11/03
Table 3.
AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00XX0B
Not Bit Addressable
– – – WDIDLE DISRTO – – DISALE
Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DISALE Disable/Enable ALE
DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
DISRTO Disable/Enable Reset out
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode

WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data
Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1
selects DP0 and DPS = 1 selects DP1. The user should ALWAYS initialize the DPS bit to the appropriate value before
accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power
up. It can be set and rest under software control and is not affected by reset.
Table 4. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
– – – – – – – DPS
Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

Data Pointer Register
DPS Select
DPS
Selects DPTR Registers DP0L,
0 DP0H
Selects DPTR Registers DP1L,
1 DP1H
 AT89S5
8 2
1919B–MICRO–11/03
AT89S52

MCS-51
M devices
e have a
m separate
address
or space for
y Program
Or and Data
Memory. Up
ga to 64K bytes
ni each of
za external
Program
tio and Data
n Memory can
be
addressed.
Pr
og If the EA pin
ra is connected
to GND, all
m program
Me fetches are
mo directed to
ry external
memory.
On the
AT89S52, if
EA is
connected
Da to VCC,
ta program
Me fetches to
addresses
mo 0000H
ry through
1FFFH are
directed to
internal
memory and
fetches to
addresses
2000H
through
FFFFH are
to external
memory.

The
AT89S52
implements
256 bytes of
on-chip
RAM. The
upper 128
bytes
occupy a
parallel
add es an
res internal
s location
spa above
ce address
to 7FH, the
the address
Spe mode used
cial in the
Fun instruction
ctio specifies
n whether the
Re CPU
gist accesses
ers. the upper
Thi 128 bytes of
s RAM or the
me SFR space.
ans Instructions
that which use
the direct
upp addressing
er access the
128 SFR space.
byt
For
es
example,
hav
the following
e
direct
the
addressing
sa
instruction
me
accesses
add
the SFR at
res location
ses 0A0H (which
as is P2).
the
MOV
SF
0A0H,
R #data
spa
ce Instructions
but that use
are indirect
phy addressing
sica access the
lly upper 128
sep bytes of
arat RAM. For
e exam-ple,
fro the following
m indirect
SF addressing
R instruction,
spa where R0
ce. contains
0A0H,
Wh accesses
en the data
an byte at
inst address
ruct 0A0H, rather
ion than P2
acc (whose
ess address is
0A0 MOV
H). @R0,
#data
Reset-
out)

W
a
t Using
c the
h WDT
d
o
g

T
i
m
e
r
(
O
n
e
-
t
i
m
e

E
n
a
b
l
e
d

w
i
t
h
 128 bytes
N
of data
o
RAM are
t
available
e
as stack
t
space.
h
a
t The WDT
s is
t intended
a as a
c recovery
k method in
o situations
p where the
e CPU may
r be sub-
a jected to
ti software
o upsets.
n The WDT
s consists of
a a 14-bit
r counter
e and the
e Watchdog
x Timer
a Reset
m (WDTRST
p ) SFR.
l
The WDT
e
is
s
defaulted
o
to disable
f
from
i
exiting
n
reset. To
d
enable the
ir
WDT, a
e
user must
c
write
t
01EH and
a
d 0E1H in
d sequence
r to the
e WDTRST
s regis-ter
s (SFR
i location
n 0A6H).
g When the
, WDT is
s enabled, it
o will
t increment
h every
e machine
u cycle
p while the
p oscillator
e is running.
r The WDT
ti o disable
m the WDT
e except
o through
u reset
t (either
p hardware
e reset or
ri WDT
o overflow
d reset).
i When
s WDT
d overflows,
e it will drive
p an output
e RESET
n HIGH
d pulse at
e the RST
n pin.
t
o
n To enable
t the WDT,
h a user
e must write
e 01EH and
x 0E1H in
t sequence
e to the
r- WDTRST
n register
a (SFR
l location
c 0A6H).
l When the
o WDT is
c enabled,
k the user
fr needs to
e service it
q by writing
u 01EH and
e 0E1H to
n WDTRST
c to avoid a
y WDT
. overflow.
T The 14-bit
h counter
e over-flows
r when it
e reaches
i 16383
s (3FFFH),
n and this
o will reset
w the
a device.
y When the
t WDT is
enabled, it
w the user
ill must reset
i the WDT
n at least
c every
r 16383
e machine
m cycles. To
e reset the
n WDT the
t user must
e write
v 01EH and
e 0E1H to
r WDTRST.
y WDTRST
m is a write-
a only
c register.
h The WDT
i counter
n cannot be
e read or
c written.
y When
c WDT
l overflows,
e it will
w generate
h an output
il RESET
e pulse at
t the RST
h pin. The
e RESET
o pulse
s duration is
c 98xTOSC,
ill where
a TOSC =
t 1/FOSC.
o To make
r the best
i use of the
s WDT, it
r should be
u serviced in
n those sec-
n tions of
i code that
n will
g periodicall
. y be
T executed
h within the
i time
s required to
m prevent a
e WDT
a reset.
n
s
 9

1919B–MICRO–11/03
WDT During Power- In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode, the user does not need to service the WDT. There are two
down and Idle
methods of exiting Power-down mode: by a hardware reset or via a level-activated
external inter-rupt which is enabled prior to entering Power-down mode. When Power-
down is exited with hardware reset, servicing the WDT should occur as it normally does
whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly
different. The interrupt is held low long enough for the oscillator to stabilize. When the
interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting
the device while the interrupt pin is held low, the WDT is not started until the interrupt is
pulled high. It is suggested that the WDT be reset during the interrupt service for the
interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it
is best to reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine
whether the WDT continues to count if enabled. The WDT keeps counting during IDLE
(WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52
while in IDLE mode, the user should always set up a timer that will periodically exit
IDLE, service the WDT, and reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the
count upon exit from IDLE.
UART
The UART in the AT89S52 operates the same way as the UART in the AT89C51 and
AT89C52. For further information on the UART operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select “Products”, then “8051-Architec-
ture Flash Microcontroller”, then “Product Overview”.
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in
the AT89C51 and AT89C52. For further information on the timers” operation, refer to
the ATMEL Web site (http://www.atmel.com). From the home page, select “Products”,
then “8051-Architecture Flash Microcontroller”, then “Product Overview”.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event
counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in
Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down
counting), and baud rate generator. The modes are selected by bits in T2CON, as
shown in Table 5. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer
function, the TL2 reg-ister is incremented every machine cycle. Since a machine cycle
consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
Table 5. Timer 2 Operating Modes
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)
10 AT89S52
1919B–MICRO–11/03
AT89S52
)

Figure 1.
Timer in
Capture
Mode

Ca
ptu
re
Mo
de

A
ut
o-
re
lo
a
d
(U
p
or
D
o
w
n
C
o
u
nt
er
 in one cycle
and a low in
In the next
the cycle, the
Cou count is
nter incremented.
funct The new
ion, count value
the appears in
regis the reg-ister
ter is during S3P1
incre of the cycle
men following the
ted one in which
in the transition
resp was
onse detected.
to a Since two
1-to- machine
0 cycles (24
tran oscillator
sitio periods) are
n at required to
its recognize a
corr 1-to-0 tran-
espo sition, the
ndin maximum
g count rate is
exte 1/24 of the
rnal oscillator
input frequency.
pin, To ensure
T2. that a given
In level is
this sampled at
funct least once
ion, before it
the changes, the
exte level should
rnal be held for at
input least one full
is machine
sam cycle.
pled
duri In the
ng capture
S5P mode, two
2 of options are
ever selected by
y bit EXEN2 in
mac T2CON. If
hine EXEN2 = 0,
cycl Timer 2 is a
e. 16-bit timer
Whe or counter
n which upon
the overflow sets
sam bit TF2 in
ples T2CON. This
sho bit can then
w a be used to
high generate an
inter In addition,
rupt. the transition
If at T2EX
EXE causes bit
N2 = EXF2 in
1, T2CON to be
Tim set. The
er 2 EXF2 bit, like
perf TF2, can
orm generate an
s the interrupt.
sam The capture
e mode is
oper illustrated in
ation Figure 1.
, but
a 1- Timer 2 can
to-0 be
tran programmed
sitio to count up
n at or down
exte when
rnal configured in
input its 16-bit
T2E auto-reload
X mode. This
also feature is
caus invoked by
es the DCEN
the (Down
curr Counter
ent Enable) bit
valu located in
e in the SFR
TH2 T2MOD (see
and Table 6).
TL2 Upon reset,
to the DCEN bit
be is set to 0 so
capt that timer 2
ured will default to
into count up.
RCA When DCEN
P2H is set, Timer
and 2 can count
RCA up or down,
P2L, depending
resp on the value
ectiv of the T2EX
ely. pin.

OSC ÷12
 T2 PIN

TRANSIT

DETECT

T2EX PIN

CONTROL

EXEN2
 11

1919B–MICRO–11/03
Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2
in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also
causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture
ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow
or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can
gen-erate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 2. In
this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes
Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow
also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer
registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2
equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a
17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

Figure
2. Timer 2 Auto Reload Mode (DCEN = 0)

OSC ÷12
C/T2 = 0

TH2 TL2
OVERFLOW

C O NT
R OL
TR2
C/T2 = 1
RELOAD

T2 PIN TIMER 2

RCAP2H RCAP2L INTERRUPT

TF2
TRANSITION

DETECTOR
 EXF2

T2EX PIN

CONTROL

EXEN2

12 AT89S52
1919B–MICRO–11/03
 AT89S52

Table 6. T2MOD – Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
– – – – – – T2OE DCEN
Bit 7 6 5 4 3 2 1 0

Symbol Function
– Not implemented, reserved for future
T2OE Timer 2 Output Enable bit
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter
Figure
3. Timer 2 Auto Reload Mode (DCEN = 1)
TOGGLE
(DOWN COUNTING RELOAD VALUE)

0FFH 0FFH
EXF2

OSC ÷12
OVERFLOW
C/T2 = 0

TH TL TF2
2 2

CONTROL

TR2
C/T2 = 1 TIMER 2

INTERRUPT
T2 PIN

RCAP2H RCAP2L COUNT

DIRECTIO
(UP COUNTING RELOAD VALUE) N
1=UP
0=DOWN

T2EX PIN
 13

1919B–MICRO–11/03
Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON

(Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is

used for the receiver or transmitter and Timer 1 is used for the other function. Setting
RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure
4.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in
TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers
RCAP2H and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to
the following equation.

Timer 2 Overflow Rate

Modes 1 and 3 Baud Rates = -----------------------------------------------------------
16

The Timer can be configured for either timer or counter operation. In most applications,
it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer
2 when it is used as a baud rate generator. Normally, as a timer, it increments every
machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it
increments every state time (at 1/2 the oscillator frequency). The baud rate formula is
given below.

M od es 1a nd 3 O s c illa t o rF r e q u e n c y
---------------------------------------
= - --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---

32 x [65536-
Baud Rate RCAP2H,RCAP2L)]

where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit
unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK
or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not gener-
ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2
but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus, when Timer
2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator
mode, TH2 or TL2 should not be read from or written to. Under these conditions, the
Timer is incremented every state time, and the results of a read or write may not be
accurate. The RCAP2 registers may be read but should not be written to, because a
write might overlap a reload and cause write and/or reload errors. The timer should be
turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
14 AT89S52
1919B–MICRO–11/03
 AT89S5
2
Figure
4. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW

÷2
"0" "1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 SMOD1

OSC ÷

C/T2 = 0 "1" "0"

TH2 TL2 RCLK

Rx

CONTROL ÷16 CLOCK

TR2

C/T2 = 1
"1" "0"

T2
PIN TCLK

RCAP2
H

RCAP2
L
Tx
CLOCK
TRANSITION
÷ 16

DETECTOR

TIMER 2

EXF2
T2EX
PIN
INTERRUPT
 CONTROL

EXEN2

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure
Programmable 5. This pin, besides being a regular I/O pin, has two alternate functions. It can be pro-
Clock Out grammed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle
clock ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency).
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be
cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the
timer.
The clock-out frequency depends on the oscillator frequency and the reload value of
Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.

Clock-Out Frequency
= Oscillator Frequency
------------------------------------------------------------------------------------
4 x [6 55 3 6 -(R C A P 2 H ,R C A P 2L )]

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as
a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note,
however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they
both use RCAP2H and RCAP2L.

15

1919B–MICRO–11/03
 Figure Timer 2 in Clock-Out
5. Mode TL2 TH2
OSC ÷2
(8-BITS) (8-BITS)

TR2

RCAP2L RCAP2H

C/T2 BIT

P1.0
÷2
(T2)

T2OE (T2MOD.1)

TRANSITION

DETECTOR

P1.1 TIMER 2

(T2EX) EXF2 INTERRUPT

EXEN2

The AT89S52 has a total of six interrupt vectors: two external interrupts
Interru (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the
pts serial port interrupt. These interrupts are all shown in Figure 6.
Each of these interrupt sources can be individually enabled or disabled
by setting or clearing a bit in Special Function Register IE. IE also
contains a global disable bit, EA, which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimplemented. User
software should not write a 1 to this bit position, since it may be used in
future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2
in register T2CON. Neither of these flags is cleared by hardware when
the service routine is vec-tored to. In fact, the service routine may have
to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the
cycle in which the timers overflow. The values are then polled by the
circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at
S2P2 and is polled in the same cycle in which the timer overflows.
16 AT89S52
1919B–MICRO–11/03
Table 7. Interrupt Enabl
(MSB)
EA –
Enable Bit = 1 enables the
Enable Bit = 0 disables the

Symbol Po
EA IE.

– IE.
ET2 IE.
ES IE.
ET1 IE.
EX1 IE.
ET0 IE.
EX0 IE.
User software should neve

Figure 6. Interrupt Sourc

1919B–MICRO–11/03
Oscillator XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that
can be configured for use as an on-chip oscillator, as shown in Figure 7. Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock
Characteristics source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure
8. There are no requirements on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum
and maximum voltage high and low time specifications must be observed.

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain
Idle Mode active. The mode is invoked by software. The content of the on-chip RAM and all the
special functions registers remain unchanged during this mode. The idle mode can be
termi-nated by any enabled interrupt or by a hardware reset.

Note that when idle mode is terminated by a hardware reset, the device normally
resumes program execution from where it left off, up to two machine cycles before the
internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM
in this event, but access to the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when idle mode is terminated by a reset, the
instruction following the one that invokes idle mode should not write to a port pin or to
external memory.

Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes
Power-down is the last instruction executed. The on-chip RAM and Special Function
Registers retain their values until the Power-down mode is terminated. Exit from
Power-down mode can be initiated either by a hardware reset or by an enabled
external inter-rupt. Reset redefines the SFRs but does not change the on-chip RAM.
The reset should not be activated before VCC is restored to its normal operating level
and must be held active long enough to allow the oscillator to restart and stabilize.

Figure 7. Oscillator Connections

C2

XTAL2

C1
XTAL1

GND
Note: 1. C1, C2 = 30 pF ± 40 pF ± 10 pF for Ceramic
= Resonators

18 AT89S52
1919B–MICRO–11/03
 AT89S52
Figure
8. External Clock Drive Configuration
NC
XTAL2

EXTERNAL XTAL1
OSCILLATOR
SIGNAL

GND
Table 8.

Status of External Pins During Idle and Power-down Modes

Program
PSE
Mode Memory ALE N PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data

The AT89S52 has three lock bits that can be left unprogrammed (U) or can be pro-
grammed (P) to obtain the additional features listed in the following table.

Table 9. Lock Bit Protection Modes

Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
2 P U U MOVC instructions executed from external program
memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on reset, and
further programming of the Flash memory is disabled
3 P P U Same as mode 2, but verify is also disabled
4 P P P Same as mode 3, but external execution is also disabled

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched dur-ing
reset. If the device is powered up without a reset, the latch initializes to a random value and
holds that value until reset is activated. The latched value of EA must agree with the current
logic level at that pin in order for the device to function properly.

Program Memory
Lock Bits
 19

1919B–MICRO–11/03
Programming the The AT89S52 is shipped with the on-chip Flash memory array ready to be programmed.
The programming interface needs a high-voltage (12-volt) program enable signal and is
Flash – Parallel Mode compatible with conventional third-party Flash or EPROM programmers.

The AT89S52 code memory array is programmed byte-by-byte.

Programming Algorithm: Before programming the AT89S52, the address, data, and
control signals should be set up according to the Flash programming mode table and
Figures 13 and 14. To program the AT89S52, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V.
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits.
The byte-write cycle is self-timed and typically takes no more than 50 µs.
Repeat steps 1 through 5, changing the address and data for the entire
array or until the end of the object file is reached.
Data Polling: The AT89S52 features Data Polling to indicate the end of a byte write
cycle. During a write cycle, an attempted read of the last byte written will result in the
complement of the written data on P0.7. Once the write cycle has been completed, true
data is valid on all outputs, and the next cycle may begin. Data Polling may begin any
time after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY
output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY.
P3.0 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the
programmed code data can be read back via the address and data lines for verification.
The status of the individual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure
as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7
must be pulled to a logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 52H indicates AT89S52
(200H) = 06H
Chip Erase: In the parallel programming mode, a chip erase operation is initiated by
using the proper combination of control signals and by pulsing ALE/PROG low for a
duration of 200 ns - 500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip
Erase instruction. In this mode, chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location will return 00H at the data
output.
 VCC

P1.5/MOS
INSTRUCTION I
INPUT

P1.6/MIS
DATA OUTPUT O

CLOCK IN P1.7/SCK

XTAL2

3-33 MHz

VI
XTAL1 RST H

GND