Federico Faggin nty-five years ago, in November

71, an advertisement appeared in In April of 1969, Intel agreed to develop a

Synaptics, Inc. Electronic News: “Announcing a new set of calculator chips for a Japanese firm.
era in integrated electronics, a micropro- The firm consisted of two companies:
Marcian E. Hofflr. grammable computer on a chip.”The ad was Electro-Technical industries handled prod-
placed by Intel Corporation of Santa Clara, uct development, and Nippon Calculating
Teklicon California, then just over three years old. From Machines Company handled marketing. The
that modest but prophetic beginning, the calculators bore the brand name Busicom.
Stanley Mazor microprocessor market has grown into a Busicom intended to use the chip set in sev-
multibillion-dollar business, and Intel has eral different models of calculators, from a
BEA Systems maintained a leadership position, particularly low-end desktop printing calculator to cal-
in microprocessors for personal computers. culator-like office machines such as billing
Masatoshi Shima In 1968, Bob Noyce and Gordon Moore, machines, teller machines, and cash regis-
who had both just left Fairchild Semicon- ters. The firm made arrangements for three
VM Technology Inc. ductor, founded Intel Corporation, and oper- of its engineers to come to Intel to finish the
ations began in September of the same year. logic design for the calculator chips and to
The new company was committed to devel- work with Intel personnel to transfer the
oping semiconductor mainframe memory designs into silicon. The three engineers from
products using both bipolar and MOS (metal- Japan-Masatoshi Shima and his colleagues
oxide-semiconductor) technologies. Bipolar Masuda and Takayama-arrived in late June.
processes offered faster access times, while Intel assigned Marcian E. Hoff Jr. to act as
MOS processes promised higher chip com- liaison to the Japanese engineers. Hoff had
plexity-that is, more memory bits per chip. received his PhD from Stanford University
Rather than use the established technologies in 1962 and had remained there as a
of the day, Intel was determined to use new research associate working on electronic
bipolar and MOS processes similar to those neural networks until he joined Intel in
Fairchild Semiconductor had just developed. September 1968. At Stanford, Hoff had pro-
For the MOS products, Intel chose a self- grammed and built hardware interfaces for
aligned P-channel silicon-gate process. IBM model 1620 and 1130 computers. He
Intel intended to produce proprietary was Intel’s twelfth employee and received
memory products, rather than a specific the title manager of applications research.
product for each customer. Though this Hoff‘s duties were to help define Intel
strategy offered high potential sales volume, products, meeting with customers and mar-
it increased the design time. To optimize its keting personnel as necessary. In addition,
revenue stream, therefore, Intel remained as Intel products became available, he
open to limited custom work, hoping that would develop applications information to
customers would be ready to use the prod- help customers use those products.
ucts as soon as they were working. The However, because in early 1969 the prod-
company did not project custom products ucts were still in development, and there
to reach the high sales volumes it expected were limited opportunities to question
of the proprietary products, but it hoped potential customers, Hoff had taken on sev-
The 4004 design team they would provide an important source of eral tasks peripheral to his primary duties.
revenue until the memory products were Although Hoff was only supposed to act
tells its stoy . established. as liaison to the Busicom engineering team,

IO /€€€Micro 0272-1732/96/$5.00 0 1996 IEEE

 SYNC
RESET

SYNC
RESET

Qo 01 Q9 Qo Ql 09 010 0 1 1 019

terconnection
1- the 4001/4002

set can have U

ontains 1,280 nibbles
addressable 4-bit I/O PO
put ports via the 400
1- doubles the am
1- chip can store

curiosity about the calculator led him to study the design. design in commercial products since 1968, using transistor-
His first reaction was surprise at how complex the calcula- transistor logic (TTL) and ROM.
tor logic was, particularly when compared to the general- Hoff expressed some of his concerns about packaging and
purpose digital computers he had used. In addition, the design complexity to Intel’s upper management-designing
interconnections between the various chips were extensive, that many chips could be a daunting task for the limited chip
requiring large and expensive packages. Having attended design staff. Bob Noyce particularly encouraged him to pur-
several meetings on the project’s cost objectives, Hoff sue an alternative design if one appeared feasible.
became concerned that the packaging requirements alone Hoff was initially reluctant to deviate too far from the orig-
might prevent Intel from meeting those objectives. inal Busicom design. While some aspects of the proposed
Busicom had proposed a ROM-based, macroinstruction chip set were similar to those of other calculators of the day,
programmable decimal computer consisting of seven differ- it also included some novel capabilities. Most notable were
ent LSI chips: program control, decimal arithmetic unit, tim- the use of ROM for macroinstruction storage and a special-
ing logic, ROM, shift register, printer control, and output ized instruction set that would allow various calculator-
ports. Busicom had already successfully implemented this intensive machines to use the same chips. Another innovative

December 1996 11
 Address Sent t o ROM From CPU -

feature was the variable amount of shift register memory that silicon area than the shift register cell.
the design could use, with the different calculator models One of the first modifications to the Busicom design Hoff
having different numbers of memory registers. considered was adding subroutine capability to the instruc-
Like many calculators of the day, Busicom’s design used tion set. Subroutines of simple instructions could replace
shift registers for memory. Shift registers are quite fast for more complex instructions, which should allow simplifica-
the arithmetic calculations, display, and printing that calcu- tion of the hardwired logic. Although the Busicom engineers
lators require, but are slow for operations requiring random appeared unreceptive to Hoff‘s proposals, with Noyce’s
access. Shift registers used six transistors per bit, like static encouragement, Hoff continued exploring options.
RAM, but a shift register cell was smaller than the RAM cell. Hoff began to consider the design of a general-purpose
The shift register’s size advantage, however, was offset by computer that might be programmed to perform calculator
increased control logic complexity and slower speed for ran- functions. The computer would fetch program instructions
dom access. Any access to even a portion of a memory reg- from a ROM into an arithmetic chip. The arithmetic chip
ister required a complete scan through that register. Such would interpret the instructions, reading and writing as nec-
slow memory access would make a conventional CPU archi- essary to DRAM chips. The arithmetic chip would also have
tecture too slow to be practical. local “scratch-pad” registers. During the time the arithmetic
chip was fetching program instructions from ROM, the
DRAMScould be refreshed, since no instruction execution
Intel had just begun working on dynamic MOS RAM,using would be occurring at that time. The data quantum would be
a three-transistor cell. Hoff, aware of that development, 4 bits to allow binary-coded decimal (BCD) arithmetic.
thought that if he could solve its refresh problem in the cal- Hoff performed these studies of a general architecture in
culator environment, the DRAM would be an ideal alterna- July and August of 1969. During this time, he believed the
tive to the shift register memory. Unlike the shift register, the Busicom team was unresponsive to his idea. On the con-
DRAM could be accessed in as small a quantum as desired. trary, Busicom engineers recognized that Hoff‘s proposal of
In addition, the three-transistor DRAM cell used even less a general-purpose CPU was more advantageous than their

12 IEEEMicra
 SYNC TEST RESET
P ? Q
t I I
INTERNAL
RESET

Block diagram of the 4004 CPU

The 4004 conrains 16 genera-purpose +bit registers; .'Chi" indicates command). There is :tlso a reset pin IC) ini-
one +hit accumulator: ;t four-le\~rl.12-hit push-clonm tialize the system ancl ;I test input pin. Tcst pro\,idcs on~'
address stack containing the program counter and three of the conditions in the conclitiond jump instruction (ICs,,
return aclcltesws fot suhioutine nesting; a hinary and clrc- allc~nhgr h r 400.4 t o pol1 extt~rnslclc-viccas LAICYgcric~-~~~ioii
imal arithmetic unit; instruction rcgictcr. dccoder, ;ind con- procc'ssor5 rl$ilced Test \\.it11 a much more con\.enient
trol logic; timing logic; bus control; and misccllmcous inrcrrupt facility.
conrnd. A~llic~ugh sr.\,r.r.rl prior ~ ~ o t i i ~ ~drc1~itec.ttrre.i
utcr inspirccl
In addition to the pins required for the +bit tristatc data the iOOr (l'Dl'-8. IHJl 1620, ancl so on), it is unique in
bus, tho-phase clock, po\\.er,a i d ground, the 4 ) O i has a inany aspects. Its main value resides in its siinplicity m c l
SYN(: timing output pin ancl fi\v control lines tor addrccs- econoiii!' o l " m ~ s s e n t i a lingrctlients, giwm t l !in)- ~
ing the t W l and t O O L chips ((;\I K 0 . V and CM MM0 5; itcd CapabiliticS of 1CI70 scmiconductor technology.

design The concept was still incomplete, however, and In September 1969, Stanley Mazor joined Intel from
required additional features to function satisfactorily in Fairchild, where he had been since 1964, and where he had
Busicom's products Certain calculator functions, such as helped design the Symbol computer. After Mazor arrived,
decimal adjust and keyboard processing, required too many progress began to accelerate.
bytes of ROM, and there was no mechanism for real-time Working together, Mazor and Hoff further refined the idea
control to synchronize the CPU with external events Also, of a general-purpose design and demonstrated its potential
the RAM chip's organization did not seem well suited for capabilities, addressing the objections raised by the Busicom
storing the decimal position, sign, and other data necessary team. In response to the Busicom engineers' need for
for calculating a decimalstring of digits ~
macroinstruction capability, Mazor proposed adding a Fetch

~ December 1996 13
Indirect instruction and coded a 20-byte interpreter to exe- instruction that would simplify keyboard scanning, and mod-
cute 1-byte macroinstructions Shima, the Busicom engineer ifying the Branch Back instruction
m charge of programming, further iefined Mazor’s interpreter It appeared at the time that a 1-MHz clock would be feasi-
In addition, Shima proposed including a conditional jump ble for the processor’s logic To allow the use of small, inex-
based on the status of an external input pin (test), adding an pensive packages (16 leads), the design could include
extensive multiplexing of intercon-
necting lines. Four data transfer lines The 4004 chip
would permit the processor to trans- The 4004 is the first example of a complex random-logic circuit built using sil-
fer one 4-bit quantum each clock icon-gate MOS technology. Silicon gate was essential in obtaining the small size
cycle. With a 12-bit program address and the high speed (for the day) required by a general-purpose CPU. The chip
and an 8-bit instruction, it would take measures 3.0 mmx4.0 mm and integrates approximately 2,300 transistors.
five clock cycles to address and fetch Under Federico Faggin’s ciinxtbn, three layout draftsmen drew the composite
an instruction. Since most instructions layout offhe 4W using colored lead pencils on mylar at 500 times the actual scale.
would be simple,three cycles for exe- The composite layout translated the abstract circuit diagram into the actual geom-
cution seemed adequate. Those tim- etty of the transistors and their interconnections.Showing all the masking layers
ing parameters and a I-MHz clock required for pwessing, the layout served as a rempIate for the preparation of the
would allow the processor to add “rubies.”A rubyiith consists of a mylar sheet with a thin layer of semitransparent,
multidigit BCD numbers at a rate of red material that can be cut and peeled off. The composite layout, placed under-
80 microseconds per digit. This speed nea&h&e ruby, guided the cuning and peeling operations. One ruby was prepared
was comparable to that of the IBM for each m w k layer required in the wafer processing. The 4004 required six lay-
1620 computer Hoff had used in the ers, including the scratch-protection layer; the other chips in the set required five.
early 1960s. The ruby was then photoreduced to 10 times the 4004’s actual scale to prepare the
By mid September, Intel marketing reticle. The reticle, in turn, was used to create the actual scale mask via a step-and-
was sufficiently confident of the new repeat optical process.
approach to suggest it to Busicom
management as an alternate to the
original design In Ocrober 1969,
Intel held a formal meeting with the
Japanese firm’s management, who
had come to the US to discuss the
project. Intel presented both
approaches, with Hoff and Mazor
arguing that the Intel architecture was
much more flexible than the original.
Busicom’s managers, appreciating
the architecture’s increased simplici-
ty and flexibility, chose the Intel
design, and Intel became committed
to build the first single-chip comput-
er CPU. The Busicom engineers
returned to Japan, except Shima. He
stayed on at Intel until December to
develop many of the calculator’skey
software programs, which he based
on the new architecture and its
instruction set.
When the companies signed a
development contract, Hoff was dis-
appointed to learn that, although Intel had developed the erating applications information for the memory products that
architecture and it differed markedly from the original, the Intel was adding to its product line. One of the more success-
contract gave exclusive rights to Busicom. Intel marketing ful memory products was a line of shift registers that quickly
explained that the project would not have proceeded with- found a market in CRT (cathode-ray tube) computer terminals.
out that concession. One of the customers for shift registers was Computer
Intel was now committed to develop the chips for the new Terminals Corporation of San Antonio, Texas. In December
architecture, but the company had a staffing problem. Neither 1969, an officer of that company inquired if Intel could mod-
Hoff nor Mazor had designed chips, and the proposed chips’ ify an existing Intel static RAM (the 13101, a bipolar 64-bit
complexity would require someone with extensive experi- RAM) to create a 4x16 stack memory for an intelligent ter-
ence. Thus, the design would fall to a different department minal CTC was designing, the Datapoint 2200.
than Applications Research. Since MOS designers were in Mazor and Hoff studied the request and determined that the
short supply, and all of those at Intel were already commit- CTC processor did not appear much more complicated than the
ted to memory projects, Intel would have to recruit someone proposed 4004. They concluded that it would he feasible to
to take over the project’s logic and circuit design and the sil- make a single-chip, 8-bit microprocessor. They drew up a tar-
icon implementation phase. That process would take months. get specification, and CTC contracted with Intel for the devel-
In the meantime, Hoff and Mazor had responsibility for gen- opment of what would be Intel’s second microprocessor. By

December 7996 15
early 1970, Intel was committed to produce two different sin- Faggin, however, had figured out how to make bootstrap loads
gle-chip computers, and still had no staff to do the design. without modifying the process architecture. This circuit trick
was essential to achieve the necessary speed and density with-
e design of the 4004 out exceeding the power budget.
Early in 1970, Leslie Vadasz, who headed Intel’sMOS design Faggin was also happy to find that Intel had adopted the
group, announced he had found someone to do the design of “buried-contact”design. This technique, similar to the one he
the calculator chip set: Federico Faggin. Faggin worked at had developed at Fairchild, permitted direct connections
Fairchild, where he and Tom Klein had developed the origi- between the polysilicon layer and the diffusion layer, allow-
nal MOS silicon-gate process in 1968. He had also designed ing higher circuit densities.The buried contact was essential to
the first commercial circuit to use that technology (the 3708, an achieve a manufacturable chip size for the 4004.
8-bit analog multiplexer with decoding logic). Faggin also had Faggin decided to design the 4001 first, followed by the
experience with computer design, having codesigned and built 4003,the 4002,and finally the 4004.In those days, there was
a small computer for Olivetti in his homeland, Italy, in 1961. little automation of the design process. Although Intel had
Faggin joined Intel in April 1970, as the engineer in charge access to a time-shared mainframe computer for critical cir-
of the design of the calculator set. Internally called the 4000 cuit simulation (via a 10-characters-per-second teletype), the
family,the set consisted of four chips: the ROM program mem- company discouraged Faggin from using it because of its
ory (4001),the RAM register memory (4002),an 1/0 expan- cost. So, Faggin did most of the circuit design with a slide rule
sion shift register chip (4003),and the CPU (4004).A couple and using graphical analysis based on measured static and
of days after Faggin joined Intel, Shima arrived from Japan to dynamic transistor characteristics.
check on the project’s progress. Shima was very disappointed Designing a production integrated circuit took many steps,
that no progress had been made since he left Intel in December starting with the definition of the chip architecture and its
1969; according to him, the schedule for the project had been basic specifications. For the 4000 set, Hoff and Mazor com-
irreparably compromised. Because of this delay, Faggin began pleted these initial steps, with contributions by Shima and the
work at a furious pace, often far into the early moining hours, other Busicom engineers. Next came the logic design, circuit
to make up as much of the lost time as possible. Shima stayed design, layout design, ruby-cutting, mask making, wafer pro-
at Intel for six months to help Faggin with the project. cessing, chip verification and debugging, characterization,
After resolving the few remaining architectural issues, production test-pattern development, and transfer to manu-
Faggin laid down the foundations of the design methodolo- facturing. The entire process, starting from the logic design
gy he was going to use for the chips. Random logic design and ending with working samples, would take a minimum of
with silicon-gate technology required a different methodol- six months for a simple chip, longer for a complex one.
ogy than metal-gate technology, and no one had ever At the peak of the project, Faggin and Shima worked simul-
designed a circuit of the 4004’s complexity. taneously on all four chips at different stages of the develop-
An important element of Faggin’smethodology was its use ment process. The 4004’sdetailed logic design, which Shima
of bootstrap loads. These circuits provided faster output volt- undertook, took place duringJune and July. Shima also did the
age swings, switching to the full supply voltage instead of the logic simulation, while Faggin concentrated on the circuit
supply voltage minus the transistor threshold voltage (aug- design, layout, and overall supervision of the project.
mented by the body effect). Bootstrap loads allowed him to
use pass transistors, simplifying the circuit design and reduc- 04 comes to life
ing the number of transistorsnecessary to perform the required Intel processed the first silicon wafers of the 4001 in
logic functions. In those days, it was common belief that boot- October 1970, and Faggin found the circuit fully functional.
strap loads were not feasible with silicon-gate technology, In preparation for receiving the chips, Shima returned to
unless the design incorporated an additional masking step. Japan to complete writing the software and to build the engi-

16 IEEE Micro
neering prototype of the Busicom calculator. In November, cell. (Intel had avoided a similar problem in its standard
4003 and 4002 wafers came out of the processing line. The DRAM components by using an additional substrate bias, not
4003 was fully functional, and the 4002 had a minor prob- desirable in the 4000 series.) Once Faggin understood the
lem that was soon diagnosed and corrected. problem, he soon found a solution. Fortunately, there was
Finally, at the end of December the big day arrived; Faggin enough room in the chip to make the necessary modifica-
received the first 4004 wafers, less than nine months after he tions to the decoder without a major redesign.
had begun the project. Faggin’s hands were trembling as he Faggin was surprised that no similar problem had ever been
loaded the first wafer in the wafer prober to begin the test, observed in the 4002, which had the same decoder design as
and as he probed around the 4004, he found absolutely no the 4004. To make sure, Faggin created a special test sequence
life. He couldn’t believe his eyes. Within half an hour, how- to see if the 4002 would also fail under properly adverse con-
ever-the longest half hour of his life-Faggin found that ditions. Indeed, the 4002 demonstrated such failures, vali-
one masking step (the buried-contact layer) had been left dating the problematic-decoder hypothesis and leading
out during wafer processing. This manufacturing problem Faggin to change its design in the 4002 as well. These were
explained why the 4004 was dead. the last steps to ensure that the company would manufacture
It wasn’t until January 1971that Intel processed a new run a quality product, averting potential problems in the field.
of 4004 wafers. Faggin received the wafers in the evening Production could then start in eamest, and by August 1971,
and, alone in the lab, tested them through most of the night. the 4000 series became a major source of revenue for Intel.
This time, everything worked as expected. That was the night
the 4004 was born. Marketing the 4004
During the following days, Faggin continued verifying the When Faggin found that the 4000 chip set was exclusive
4004 and found two minor bugs that were soon diagnosed to Busicom, he was very disappointed because he saw the
and corrected. As a result, he achieved fully functional 4004s set’s market potential reaching far beyond calculators.
on the next mask iteration, in March 1971. Though he started lobbying management to obtain the rights
After thoroughly testing the 4004, Faggin sent seved samples to sell the 4000 series to the general market, the sentiment
to Busicom,where Shima was testing the calculatorand debug- at Intel was that the 4004 was good mostly for calculators
ging his software using a RAM-based emulator for the 4001. and calculator-like products. In an effort to prove otherwise,
The Busicom calculatorused one 4004, two 4002, three 4003, Faggin decided to use the 4004 as the controller for the 4004
and four 4001 chips; it used an additional 4001 for the option- production tester he was designing. Conveniently, he was
al square-root function. In other words, the system consisted able to load the software into the new EPROM devices (elec-
of a 4-bit CPU running approximately 100,000instructions per trically programmable, read-only memory, just invented at
second, with 1Kbyte of ROM, 80 bytes of RAM,and approxi- Intel by Dov Frohman-Bentchkovsky), instead of the mask-
mately 50 I/O lines. Today, using 0.35-micronlithography, the programmable 4001s. After successfully completing this pro-
most advanced manufacturing technology in production, these ject, Faggin used the example to prove to management that
functions, without the bonding pads, would occupy less than the 4004 was quite useful and thus marketable for applica-
one tenth of a square millimeter. (Incidentally, the manufac- tions besides calculators.
turing cost would now be approximately half a cent.) Hoff later found that the 4004 simplified the design of a unit
In April, word came that the Busicom calculator was fully for programming the EPROM devices while providing the abil-
functional. That was the final and essential proof that all the ity for rapid upgrades. Because EPROM promised to be ideal
chips were working properly, individually and as a system. for holding programs for the single-chip computers, Hoff and
That same month, Shima sent Intel the final ROM patterns to his group developed a circuit board containing interface circuits
generate the custom metal masks for the calculator’s four that would allow the EPROM to substitute for the 4001 ROM.
4001s. This was the last step preceding volume production, Later, Intel developed a similar board for the 8-bit processor.
which was to start in June. One day, talking over the phone with Shima in Japan,
Faggin discovered that Busicom was having financial prob-
Finishing touches lems. To be more competitive in the marketplace, the firm
During the 4004 characterization, which began in March, needed lower prices for the chip set. Faggin and Hoff then
Faggin observed a very disturbing phenomenon At high tem- pleaded with Noyce and marketing that Intel give a price
perature some 4004s were occasionally failing, but when he concession to Busicom in exchange for nonexclusivity. By
tested them again, they would pass. This problem was mad- May 1971, Intel had obtained the right to sell the calculator
dening, because the lack of repeatability and the lack of diag- chips to others, except for desktop calculator applications.
nostic tools made it very difficult to find the reason for such A brief new product announcement in Datamation mag-
elusive failures. It took a few days to conclusively determine azine mentioned the chip series. However, even_with the
that the problem was caused by the corruption of some of limited rights to sell the chips to other companies, Inel man-
the data stored in the DRAM registers. However, Faggin was agement was reluctant to announce the microprocessors offi-
at a loss to understand the mechanism responsible for it. cially. Marketing had deep concerns about the field sales
After a tense week of tests and analysis, however, he traced staff‘s ability to properly support such complex products.
the problem to a weakness in the RAM decoder’s design, Intel was developing a good reputation based on its mem-
which caused the injection of minority carriers in the sub- ory products and its support of them, and marketing did not
strate to leak away the electrical charge stored in the DRAM want to risk that reputation.

December 1996 17
 Another concern, one shared by Hoff and Mazor, was that rea s
customers accustomed to the power of minicomputers would Intel had changed the chip set’s name from 4000 to MCS-
be unable to adapt to the microprocessors’ poorer perfor- 4,for Micro Computer System 4-bit; the response to the
mance However, both felt that proper presentation would announcement of this first microprocessor was very encour-
prepare customers for the limitations, and that micro- aging. Marketing worked with Hoff, Faggin, Mazor, and Hal
processors would still find many uses Feeney to provide support. The support items included data
In the summer of 1971, major changes in Intel’s market- sheets with application information, user manuals, and print-
ing department brought in a new vice president of market- ed circuit boards. Marketing released literature that also
ing-Ed Gelbach, formerly with Texas Instruments Ed was revealed the coming 8-bit processor, which Intel officially
much braver than his predecessors, and he arranged the for- announced in April 1972 under the name 8008 (twice the
mal announcement of the 4004 in November of 1971 Hank 4004!)as the core of the MCS-8 series.
Smith, working for Gelbach, became the first microcomput- The 8008 could actually have been the world’s first micro-
er marketing manage1 processor. A few weeks before Intel hired Faggin to design

I 78 /€€€Micro
the 4000 set, Hal Feeney had joined Intel to work on the 8-
bit microprocessor for CTC. Feeney worked with Mazor and The market directly related to
CTC to complete the specifications for the chip-internally
called the 1201-and to modify the CTC architecture as nec- the microprocessor is over $100
essary for silicon implementation. Financial problems at CTC,
however, soon reduced the 1201’s priority, so Feeney was billion at OEM component
diverted to other projects. Other potential customers kept
the project alive, but the design did not proceed much past prices. The market value of all
the first few months of work.
The CTC project remained dormant until January 1971,when the products incorporating
Intel reassigned Feeney, now working under Faggin’s super-
vision, to the project. The designers’ recent experience with microprocessors is many times
the 4004 provided a proven design methodology that paved the
way for the 8008. Feeney did the detailed design of the 8008, that figure.
and by March 1972,Intel was producing working chips.
Ironically, during 1970, CTC had also contracted with
Texas Instruments to design the same processor using TI’s
MOS aluminum-gate process. TI’s chip, heralded in the tech- and designed by Faggin and Shima, with architectural con-
nical press in June 1971 as the first CPU on a chip, was more tributions by Mazor and Hoff. This evolution has continued
than twice the size of the 8008. CTC reported that it had on to the present Pentium Pro, with a new generation, on
never fully worked. average, every three years.
Intel promoted both the 4004 and the 8008, and in May of
1972, Hoff and Mazor presented several seminars around the
country. The microprocessors generated much interest, and
many of Intel’s customers began to design products based on THEPERSONAL COMPUTER has become an enormous
them. Of the two, the 4004 offered lower cost and a higher market for microprocessors, and is considered by the pop-
degree of integrationfor the resulting system, because the series ular media the microprocessor’s primary use. When Intel
offered RAM and ROM chips with I/O capability on the same originally announced the microprocessor, however, Faggin,
chip. The 8008 could address a larger memory space (up to 16 Hoff, and Mazor considered its primary market to be con-
Kbytes) and could use any mix of RAM or ROM for its memc- trol devices-applications now described as embedded con-
ry. However, the 8008 required some 20 standard TTL inte- trol. While main microprocessors for personal computers do
grated circuits to provide the interface between the processor, indeed represent a large market, with tens of millions of units
memory, and I/O. While the 8008 instruction cycle was actu- sold each year, many more microprocessors and microcon-
ally somewhat slower than the 4004, most customers perceived trollers go into embedded control applications, with a typi-
it as the preferred processor for more complex applications. cal microcontroller costing between 30Qand $10.
The 4004 and the 8008 became archetypes for today’s two From its modest beginning 25 years ago, the microproces-
primary markets for microprocessors: embedded applications sor industry has grown to such an extent that nearly 70% of
and user-programmable computers. Most microprocessors all semiconductors sold worldwide are either microproces-
used in embedded applications are now integrated with the sors, microcontrollers, or other components used in conjunc-
memory and the I/O functions-true single-chip computers. tion with them, such as memory and I/O devices. Since the
Thus, a low-cost, single chip can typically do all the work worldwide sales of semiconductor components in 1995 was
required in many simple control applications. Such devices approximately $150 billion, this means that the market direct-
are called microcontrollers. Simple 4-bit and 8-bit micro- ly related to the microprocessor is over $100 billion at OEM
controllers control microwave ovens and computer key- component prices. The market value of all the products incor-
boards, for example, while sophisticated microcontrollers porating microprocessors is many times that figure, of
drive cellular phones and laser printers. course-a truly staggering amount.
Currently, the semiconductor industry manufactures a few Over the last 25 years, there has been an explosion of appli-
billion microcontrollers worldwide per year. More than 50% cations. People carry microprocessors with them inside their
of all microcontroller units manufactured in 1995 were still watches, pocket calculators, organizers, and cellular phones;
4-bit devices with capabilities equivalent to those of the MCS- and microprocessors are all around them, in their homes,
4 set. Nonetheless, the more expensive 8-bit microcontrollers cars, offices, and laboratories. The microprocessor has
have the majority of the market dollar volume. improved the quality, cost, and functionality of traditional
The 8008s first application was a Seiko user-programma- electronic equipment. But, most importantly, it has enabled
ble, scientific calculator, and soon the 8008 led to the per- literally thousands of new applications impossible before its
sonal computer, the quintessential microprocessor advent. Amazingly, the pace of deployment of microproces-
application. In fact, many consider the personal computer’s sors and microcontrollers in new applications is still going
archetype to be the Micral, a French desktop computer using strong, and we expect it to continue for the foreseeable future.
the 8008 CPU, sold in 1973. The 8008 evolved into Intel’s Without question, the microprocessor reality has far exceed-
8080, the first high-performance microprocessor, conceived ed even the most bullish expectations of its creators.

December 1996 19
 including those for an electrochemical memory, the micro-
S processor, and the monolithic telephone codec.
Sack, E.A., R.C. Lyman, and G.Y. Chang, "Evolution of the Concept Hoff holds a BEE degree from Rensselaer Polytechnic
of a Computer on a Slice," Proc. /€E€,IEEE, Piscataway, N.J., 1964. Institute and MS and PhD degrees in electrical engineering
The authors project chips of 100 gates or more as being feasible, from Stanford University. For his role in the invention of the
and predict appreciable computer subfunctions on a single slice. microprocessor, he has received numerous awards and was
Flynn, M.J., "Complex IC Arrays: The Promise and the Problems," inducted into the Inventors Hall of Fame. An IEEE Fellow,
Electronics, July 1 1, 1966. The author predicts 1,000 gates per Hoff received that organization's Centennial Medal. The
chip and hypothesizes the one-chip computer and array :omputer Society has recognized lum as a computer pioneer.
processors.
Beelitz, H.R., and H.S. Miller, "Partitioning for Large-scale
Integration," Proc. int'lSolid-State Circuits Conf, IEEE Computer
Soc., Los Alamitos, Calif., 1967. Discusses partitioning LSI for a Stanley Mazor is training director at BEA
large computer t o improve gate/pin ratios. Systems. Formerly, he worked for Falrchdd
Bairstow, J.N., "LSI Will Demand New Computer Architecture," Semiconductor,an experience from which
Electronic Design, Jan. 4, 1968. Performance will improve, but he shares patents on the Symbol comput-
specialists see no significant cost reduction for the user. er At Intel, after hls work on the 4000 senes
Faggin, F., and T. Klein, "A Faster Generation of MO5 Devices with (for which he shares patents), he proposed
Low Threshold Is Riding the Crest of the New Wave, Silicon- the 8008 CPU chip and later specified the
Gate IC's,'' Electronics, Sept. 29, 1969. Describes the original 8080 CPU chip He began his teaching career in Intel's
MOS silicon-gate technology developed at Fairchild and the Technical Trainmg Group, and later taught classes at Stanford
world's first commercial integrated circuit t o use it, the Fairchild University, the University of Santa Clara, KTH m Stockholm,
3708, an 8-bit analog multiplexer with decoding logic. and Stellenbosh, S.A.
Narud, J.A., C.D. Phillips, and W.C. Seelbach, "Complex Monolithic Mazor studied mathematics and programming at San
Arrays: Some Aspects of Design and Fabrication," Francisco State University He has coauthored a book on a
Microelectronics, Jul. 1969. "Integration at the system level ... chip design language, A Guzde to VHDL, and published 45
too terrifying even to think about." articles and papers on VZSI chips and design
Hoff, M.E., "Impact of LSI on Future Minicomputers," Roc. lEEElnt'l
Conv., IEEE, 1970. States the feasibility of small, single-chip
processors. Masatoshi S h i m a is chair of VM
Hoff, M., S. Mazor, and F. Faggin, Memory system for Multi-Chip Technology Inc. in Japan. Formerly,he was
Digitalcomputer, US patent 3,821,715, t o Intel Corp., June 28, manager of the Intel Japan Design Center.
1974. Covers the novel, and thus patentable, architectural While an employee at Busicom Corp. in
features of the 4000 chip series. Japan, he developed the desktop calcula-
Faggin, F., PowerSupplySeffableBi-StableCircuit, US patent 3,753,Ol 1, tor, for which he introduced ROM-based
to Intel Corp., Aug. 14, 1973.Covers a special circuit that provides stored programming technology with
the power-on reset function in the 4000 series. decimal-plus-binarycomputer architecture. After working on
Faggin, F., and M. Hoff, "Standard Parts and Custom Design Merge the development of the 4000 series products, he joined Intel,
in Four-Chip Processor Kit," Electronics, Apr. 24, 1972, pp. 112- where he developed the 8080 and several peripheral chips as
1 16. The first published article to describe the 4000 series. supervising engineer. As manager of high-end microproces-
Faggin, F., et al., "The MCS-4-An LSI Microcomputer System," Proc. sors at Zilog, he developed the 280 and 28000.
/€E€ Region Six Conf, IEEE , 1972. Describes the 4000 series. Shima received a BS in chemistry from Tohoku University
Faggin, F., M. Shima, and 5. Mazor, Computer Employing a Plurality and a DrEng from Tsukuba University,Japan.
ofseparate Chips, US patent 4,010,499 t o Intel Corp., Mar. 1 ,
1977. Covers the novel architectural features of the 8080 CPU.

Direct questions concerning this article to Federico Faggin,

Federico Faggin's photograph and biography appear on Synaptics, Inc., 2698 Orchard Pkwy., San Jose, CA 95134;
page 9. federico@synaptics.com.

Marcian E. (Ted) Hoff Jr. is a design

consultant for Teklicon Inc. and assists Reader Interest Survey
attorneys dealing with patent litigation. Indicate your interest in this article by circling the appropriate
Formerly, he was vice president of cor- number on the Reader Service Card
porate technology at Atari, Inc., Intel's
manager of applications research, and the Low 153 Medium 154 High 155
first Intel Fellow. He holds 17 US patents,

20 IEEE Micro