Digital Design And Synthesis

2014
Behavioral Verilog
always & initial blocks
Coding flops
if else & case statements
Blocking vs Non-Blocking
Simulator Mechanics part duo
Administrative Matters
 Readings
• Text Chapter 7 (Behavioral Modeling)
• Cummings SNUG Paper (Verilog Styles that Kill) (posted on webpage)

 Cover HW solution for asynch reset and tran count

 Midterm:
• Wednesday 10/21/08
• 5:00PM-6:45PM
• EH ????
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Behavioral Verilog
 initial and always form basis of all behavioral Verilog
• All other behavioral statements occur within these
• initial and always blocks cannot be nested
• All <LHS> assignments must be to type reg

 initial statements start at time 0 and execute once

• If there are multiple initial blocks they all start at time 0
and execute independently. They may finish independently.

 If multiple behavioral statements are needed within

the initial statement then the initial statement can be
made compound with use of begin/end
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More on initial statements
 Initial statement very useful for testbenches
 Initial statements don’t synthesize
 Don’t use them in DUT Verilog (stuff you intend to synthesize)

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initial Blocks
`timescale 1 ns / 100 fs
module full_adder_tb; all initial blocks
reg [3:0] stim; start at time 0
wire s, c;

full_adder(sum, carry, stim[2], stim[1], stim[0]); // instantiate DUT

// monitor statement is special - only needs to be made once,

initial $monitor(“%t: s=%b c=%b stim=%b”, $time, s, c, stim[2:0]);

// tell our simulation when to stop

initial #50 $stop;

initial begin // stimulus generation

for (stim = 4’h0; stim < 4’h8; stim = stim + 1) begin
#5;
end multi-statement
end block enclosed by
endmodule begin and end

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Another initial Statement Example
module stim()
reg m,a,b,x,y;
Time Event
initial
m = 1’b0; 0 m = 1’b0

initial begin 5 a = 1’b1

#5 a = 1’b1;
#25 b = 1’b0; 10 x = 1’b0
Modelsim
end 30 b = 1’b0
initial begin
35 y = 1’b1
#10 x = 1’b0;
#25 y = 1’b1; 50 $finish
end What events at
what times will a
initial verilog simulator
#50 $finish; produce?
endmodule
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always statements
 Behavioral block operates CONTINUOUSLY
• Executes at time zero but loops continuously
• Can use a trigger list to control operation; @(a, b, c)
• In absense of a trigger list it will re-evaluate when the last
<LHS> assignment completes.
module clock_gen (output reg clock);

initial
clock = 1’b0; // must initialize in initial block

always // no trigger list for this always

#10 clock = ~clock; // always will re-evaluate when
// last <LHS> assignment completes
endmodule
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always vs initial
reg [7:0] v1, v2, v3, v4; reg [7:0] v1, v2, v3, v4;

initial begin always begin

v1 = 1; v1 = 1;
#2 v2 = v1 + 1; #2 v2 = v1 + 1;
v3 = v2 + 1; v3 = v2 + 1;
#2 v4 = v3 + 1; #2 v4 = v3 + 1;
v1 = v4 + 1; v1 = v4 + 1;
#2 v2 = v1 + 1; #2 v2 = v1 + 1;
v3 = v2 + 1; v3 = v2 + 1;
end end

 What values does each block produce?

 Lets take our best guess
 Then lets try it in Silos simulator
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Trigger lists (Sensitivity lists)
 Conditionally “execute” inside of always block
• Any change on trigger (sensitivity) list, triggers block
always @(a, b, c) begin
…
end e d ls in
ix too do
m n till ilog
 Original way to specify trigger list e
m t i o s r
So ula day t Ve
always @ (X1 or X2 or X3) sim e to ppor
us t su
 In Verilog 2001 can use , instead of or no 001.
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always @ (X1, X2, X3)
 Verilog 2001 also has * for combinational only
always @ (*) Do you know your design?
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Example: Comparator
module compare_4bit_behave(output reg A_lt_B, A_gt_B, A_eq_B,
input [3:0] A, B);

always@( ) begin

end

endmodule

Flush out this template with sensitivity list and implementation

Hint: a if…else if…else statement is best for implementation

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FlipFlops (finally getting somewhere)
 A negedge is on the transitions
• 1 -> x, z, 0
• x, z -> 0
 A posedge is on the transitions
• 0 -> x, z, 1
• x, z -> 1
 Used for clocked (synchronous) logic (i.e. Flops!)
Hey! What is this
always @ (posedge clk) assignment operator?
register <= register_input;
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Implying Flops (my way or the highway)
reg q;
d q
always @(posedge clk)
q <= d;
clk It can be reg [11:0] DAC_val;
A vector
Standard D-FF too
with no reset
always @(posedge clk)
DAC_val <= result[11:0];

Be careful… Yes, a non–reset flop is smaller than a

reset Flop, but most of the time you need to reset your
flops.

Always error on the side of reseting the flop if you are at

all uncertain.

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Implying Flops (synchronous reset)
reg q; d
q
rst_n
always @(posedge clk)
if (!rst_n) clk
q <= 1’b0; //synch reset
else Cell library might not
contain a synch reset
q <= d;
flop. Synthesis might
How does this synthesize? combine 2 standard
cells

Many cell libraries don’t contain synchronous reset

flops. This means the synthesizer will have to
combine 2 (or more) standard cell to achieve the
desired function… Hmmm? Is this efficient?

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Implying Flops (asynch reset)
rst_n reg q;

R always @(posedge clk or negedge rst_n)

d q if (!rst_n)
q <= 1’b0;
else
clk q <= d;
D-FF with Cell libraries will contain an asynch reset
asynch reset flop. It is usually only slightly larger than
a flop with no reset. This is probably your
best bet for most flops.

Reset has its affect asynchronous from clock. What if reset is

deasserting at the same time as a + clock edge? Is this the cause
of a potential meta-stability issue?

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Know your cell library
 What type of flops are available
• + or – edge triggered (most are positive)
• Is the asynch reset active high or active low
• Is a synchronous reset available?
• Do I have scan flops available?
 Code to what is available
• You want synthesis to be able to pick the least number of
cells to implement what you code.
• If your library has active low asynch reset flops then don’t
code active high reset flops.

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What about conditionally enabled Flops?
reg q;

always @(posedge clk or negedge rst_n)

if (!rst_n)
q <= 1’b0; //asynch reset
else if (en)
q <= d; //conditionally enabled
else
q <= q; //keep old value rst_n

How does this synthesize?

How about using a gated clock? 0 R

q
1
It would be lower power right? d

Be careful, there be dragons here! en clk

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Behavioral: Combinational vs Sequential
 Combinational
• Not edge-triggered
• All “inputs” (RHS nets/variables) are triggers
• Does not depend on clock

 Sequential
• Edge-triggered by clock signal
• Only clock (and possibly reset) appear in trigger list
• Can include combinational logic that feeds a FF or register

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Blocking vs non-Blocking
 Blocking “Evaluated” sequentially
 Works a lot like software (danger!)
 Used for combinational logic
module addtree(output reg [9:0] out,
input [7:0] in1, in2, in3, in4);

reg [8:0] part1, part2; in1 in2 in3 in4

always @(in1, in2, in3, in4) begin
part1 = in1 + in2; + +
part2 = in3 + in4;
out = part1 + part2; part1 part2
end +
endmodule
out
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Non-Blocking Assignments
 “Updated” simultaneously if no delays given
 Used for sequential logic
module swap(output reg out0, out1, input rst, clk);

always @(posedge clk) begin

if (rst) begin D Q
out0 <= 1’b0; out0
out1 <= 1’b1; rst rst to 0
end clk
else begin
out0 <= out1;
out1 <= out0;
D Q
end out1
end rst to 1
endmodule

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Swapping if done in Blocking
 In blocking, need a “temp” variable
module swap(output reg out0, out1, input in0, in1, swap);

reg temp;
always @(*) begin
out0 = in0; in0
out1 = in1; in1 out0
if (swap) begin
temp = out0; swap
out0 = out1;
out1 = temp;
out1
end
end
endmodule

Which values get included on the sensitivity list from *?

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More on Blocking
 Called blocking because….
• The evaluation of subsequent statements <RHS> are
blocked, until the <LHS> assignment of the current
statement is completed.
q1 q2 q3
module pipe(clk, d, q); d

input clk,d;
clk
output q;
reg q; Lets code this
always @(posedge clk) begin
Simulate this in your head…
q1 = d;
q2 = q1; Remember blocking behavior of:
q3 = q2; <LHS> assigned before
<RHS> of next evaluated.
end
Does this work as intended?
endmodule
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More on Non-Blocking
 Lets try that again d
q1 q2 q3

module pipe(clk, d, q); clk

input clk,d; Lets code this
output q;
reg q; With non-blocking statements
always @(posedge clk) begin the <RHS> of subsequent
statements are not blocked.
q1 <= d;
They are all evaluated
q2 <= q1; simultaneously.
q3 <= q2;
End The assignment to the <LHS> is
endmodule; then scheduled to occur.

This will work as intended.

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So Blocking is no good and we should
always use Non-Blocking??
 Consider combinational logic
module ao4(z,a,b,c,d);
input a,b,c,d; The inputs (a,b,c,d) in the sensitivity
output z; list change, and the always block is
evaluated.
reg z,tmp1,tmp2;
New assignments are scheduled for
always @(a,b,c,d) begin tmp1 & tmp2 variables.
tmp1 <= a & b;
tmp2 <= c & d; A new assignment is scheduled for z
z <= tmp1 | tmp2; using the previous tmp1 & tmp2
end values.
endmodule
Does this work?

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 Why not non-Blocking for
Combinational
 Can we make this example work?
module ao4(z,a,b,c,d); module ao4(z,a,b,c,d);

input a,b,c,d; input a,b,c,d;

output z; output z;
Yes
reg z,tmp1,tmp2; reg z,tmp1,tmp2;
Put tmp1
always @(a,b,c,d) begin & tmp2 in always @(a,b,c,d,tmp1,tmp2) begin
the
tmp1 <= a & b; trigger
tmp1 <= a & b;
tmp2 <= c & d; list tmp2 <= c & d;
z <= tmp1 | tmp2; z <= tmp1 | tmp2;
end end
endmodule endmodule

What is the downside of this?

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Cummings SNUG Paper
 Posted on ECE551 website
• Well written easy to understand paper
• Describes this stuff better than I can
• Read it!

 Outlines 8 guidelines for good Verilog coding

• Learn them
• Use them

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Verilog Stratified Event Queue
 Need to be able to model both parallel and sequential
logic
 Need to make sure simulation matches hardware

 Verilog defines how ordering of statements is

interpreted by both simulator and synthesis tools
• Simulation matches hardware if code well-written
• Can have some differences with “bad” code
Simulator is sequential
Hardware is parallel
Race conditions can occur
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Simulation Terminology [1]
 These only apply to SIMULATION
 Processes
• Objects that can be evaluated
• Includes primitives, modules, initial and always blocks,
continuous assignments, tasks, and procedural assignments
 Update event
• Change in the value of a net or register (LHS assignment)
 Evaluation event
• Computing the RHS of a statement
 Scheduling an event
• Putting an event on the event queue

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Simulation Terminology [2]
 Simulation time
• Time value used by simulator to model actual time.
 Simulation cycle
• Complete processing of all currently active events
 Can be multiple simulation cycles per simulation time

 Explicit zero delay (#0)

• Forces process to be inactive event instead of active
• Incorrectly used to avoid race conditions
• #0 doesn’t synthesize!
• Don’t use it

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Verilog Stratified Event Queue [1]
 Region 1: Active Events
• Most events except those explicitly in other regions
• Includes $display system tasks
 Region 2: Inactive Events
• Processed after all active events
• #0 delay events (bad!)
 Region 3: Non-blocking Assign Update Events
• Evaluation previously performed
• Update is after all active and inactive events complete
 Region 4: Monitor Events
• Caused by $monitor and $strobe system tasks
 Region 5: Future Events
• Occurs at some future simulation time
• Includes future events of other regions
• Other regions only contain events for CURRENT simulation time
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Verilog Stratified Event Queue [2]

within a block,
blocking
assignments,
are in order

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Simulation Model
Let T be current simulation time
while (there are events) {
if (no active events) {
if (inactive events) activate inactive events
else if (n.b. update events) activate n.b. update events
else if (monitor events) activate monitor events
else { advance T to the next event time
activate all future events for time T }
}
E = any active event; // can cause non-determinism!
if (E is an update event) { // in y = a | b, the assigning of value to y
update the modified object
add evaluation events for sensitive processes to the event queue
} else { // evaluation event: in y = a | b, the evaluation of a | b
evaluate the process
add update event(s) for LHS to the event queue
}
}
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if…else if…else statement
 General forms… If (condition) If (condition)
begin begin
If (condition) begin <statement1>; <statement1>;
<statement1>; <statement2>; <statement2>;
<statement2>; end end
end else else if (condition2)
begin begin
<statement3>; <statement3>;
Of course the
compound statements <statement4>; <statement4>;
formed with begin/end end end
are optional. else
begin
Multiple else if’s can be <statement5>;
strung along <statement6>;
indefinitely end

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How does and if…else if…else
statement synthesize?
• Does not conditionally “execute” block of “code”
• Does not conditionally create hardware!
• It makes a multiplexer or selecting logic
• Generally:
Hardware for both paths is created
Both paths “compute” simultaneously
The result is selected depending on the condition
If (func_add)
+ alu
alu = a + b; a[7:0] 1
else if (func_and) 0 8
alu = a & b; & 1
Else b[7:0] 0 8
8’h00
alu = 8’h00;
func_and func_add
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if statement synthesis (continued)
if (a) c
func = c & d; d
1
else if (b) 0 d
func = c | d; q func
How does this en
synthesize? a
b
Latch??
What you ask for is what you get!
func is of type register. When neither a or b are Always have an
asserted it didn’t not get a new value. else to any if to
That means it must have remained the value it avoid unintended
was before. latches.

That implies memory…i.e. a latch!

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More on if statements…
 Watch the sensitivity lists…what is missing in this
example? always @(a, b) begin
temp = a – b;
if ((temp < 8’b0) && abs)
out = -temp;
else out = temp;
end

always @ (posedge clk) begin

What is being coded here?
if (reset) q <= 0;
else if (set) q <= 1;
else q <= data; Is it synchrounous or asynch?
end
Does the reset or the set have
higher priority?

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case Statements
 Verilog has three types of case statements:
• case, casex, and casez
 Performs bitwise match of expression and case item
• Both must have same bitwidth to match!
 case
• Can detect x and z! (good for testbenches)
 casez
• Uses z and ? as “don’t care” bits in case items and expression
 casex
• Uses x, z, and ? as “don’t care” bits in case items and
expression
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Case statement (general form)
case (expression)
alternative1 : statement1; // any of these statements could
alternative2 : statement2; // be a compound statement using
alternative3 : statement3; // begin/end
default : statement4 // always use default for synth stuff
endcase

parameter AND = 2’b00; Why always have a default?

parameter OR = 2’b01;
parameter XOR = 2’b10; Same reason as always
having an else with an if
case (alu_op) statement.
AND : alu = src1 & src2;
OR : alu = src1 | src2; All cases are specified,
XOR : alu = src1 ^ src2; therefore no unintended
default : alu = src1 + src2; latches.
endcase
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Using case To Detect x And z
 Only use this functionality in a testbench!

 Example taken from Verilog-2001 standard:

case (sig)
1’bz: $display(“Signal is floating.”);
1’bx: $display(“Signal is unknown.”);
default: $display(“Signal is %b.”, sig);
endcase

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casex Statement
 Uses x, z, and ? as single-bit wildcards in case item and
expression
 Uses first match encountered

always @ (code) begin

casex (code) // case expression
2’b0?: control = 8’b00100110; // case item1
2’b10: control = 8’b11000010; // case item 2
2’b11: control = 8’b00111101; // case item 3
endcase
end
 What is the output for code = 2’b01?
 What is the output for code = 2’b1x?
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casez Statement
 Uses z, and ? as single-bit wildcards in case item and
expression
always @ (code) begin
casez (code)
2’b0?: control = 8’b00100110; // item 1
2’bz1: control = 8’b11000010; // item 2
default: control = 8b’xxxxxxxx; // item 3
endcase
end

 What is the output for code = 2b’01?

 What is the output for code = 2b’zz?
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Use of default case vs casex
 If casex treats x,z,? as don’t care then one can
create a case in which all possible alternatives are
covered.
• This would prevent unintended latches
• Therefore default branch of case would not be needed
• Might synthesize better?
 OK, I can accept that reasoning…but…
• The default branch method is typically easier to
read/understand
• Sometimes it is good to have a default behavior, especially
in next state assignments of state machines.

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